CN102856360A - Semiconductor structure and preparation method thereof - Google Patents
Semiconductor structure and preparation method thereof Download PDFInfo
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- CN102856360A CN102856360A CN2011101748745A CN201110174874A CN102856360A CN 102856360 A CN102856360 A CN 102856360A CN 2011101748745 A CN2011101748745 A CN 2011101748745A CN 201110174874 A CN201110174874 A CN 201110174874A CN 102856360 A CN102856360 A CN 102856360A
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Abstract
The invention provides a semiconductor structure. The structure comprises a substrate, a semiconductor substrate, back gate dielectric layers, back gates, cavities, a gate stack, side walls and source/drain regions, wherein the gate stack is arranged on the semiconductor substrate; the side walls are arranged on the side walls of the gate stack; the source/drain regions are embedded in the semiconductor substrate and are arranged on the two sides of the gate stack; the cavities are embedded in the substrate; the semiconductor substrate is suspended above the cavities; in the direction of the gate length, the middle thickness of the semiconductor substrate is greater than the thickness of the two sides; in the direction of the gate width, the semiconductor substrate is connected with the substrate; the back gate dielectric layers are arranged on the side walls of the semiconductor substrate; and the back gates are arranged on the side walls of the back gate dielectric layers. Correspondingly, the invention also provides a preparation method of the semiconductor structure. The semiconductor structure and the preparation method are beneficial to suppressing the short channel effect, adjusting the threshold voltage of the semiconductor device, improving the device performances, reducing the cost and simplifying the process.
Description
Technical field
The present invention relates to field of semiconductor manufacture, relate in particular to a kind of semiconductor structure and manufacture method thereof.
Background technology
For the performance and the integrated level that improve integrated circuit (IC) chip, device feature size constantly dwindles according to Moore's Law, has entered at present nanoscale.Along with dwindling of device volume, power consumption and leakage current become problems of concern.Silicon-on-insulator SOI (Silicon on Insulator) structure improves the scaled ability of device because suppressing well short channel effect, has become the preferred structure of deep-submicron and Nano-MOS transistors.
Development along with the SOI technology, at prior art document " Silicon-on-Nothing-an Innovative Process for Advanced CMOS " (IEEE electronic device proceedings, the 147th volume o. 11th in 2000) in, Malgorzata Jurcazak, Thomas Skotnicki, the people such as M.Paoli have proposed a kind of with New type of S OI device-SON (the Silicon on Nothing) device architecture of channel region preparation on cavity.
It is the advanced techniques that the CMOS processing procedure of 90nm and following technology node thereof grows up by French CE A-Leti and ST ST Microelectronics that SON (Silicon on Nothing) is one, SON forms the silicon-on-insulator of local under raceway groove by " cavity " structure, described cavity can be that air gap or oxide are filled.Compare with the SOI device, the dielectric constant of cavity structure significantly reduces, greatly reduced the impact of oxygen buried layer two dimensional electric field effect, the DIBL effect can reduce greatly, and can by control silicon film thickness and cavity height, obtain good short ditch characteristic, obtain comparatively steep sub-threshold slope, simultaneously can improve the self-heating effect of SOI device, and can adopt body silicon to replace expensive SOI sheet as raw wafers, be considered to replace a first-selected structure of SOI technology.
The problem of preparation SON device most critical is how to prepare cavity layer.At the beginning of the SON structure proposes, employing be epitaxy Si Ge sacrifice layer process.Follow-up had bibliographical information again and unite the method for injecting additional anneal with helium (He) Implantation additional anneal or hydrogen-helium (H-He) ion and prepare the SON device.Epitaxy Si Ge sacrifice layer process has increased the processing step of element manufacturing, has increased simultaneously the complexity of technique; And along with the dwindling of device feature size, also so that Implantation becomes a difficult problem, prior art will really also be faced with many challenges with in the very lagre scale integrated circuit (VLSIC) manufacturing process up till now to the dark requirement of the super shallow junction of device.
On the other hand, along with semiconductor dimensions reduces, dopant fluctuating etc. causes the threshold voltage control of semiconductor device to become more and more difficult.A solution of knowing is to adopt back of the body grid to come threshold voltage is controlled in semiconductor device.In view of the technique of SON element manufacturing, how in the SON device, to make back grid, further improve the performance of semiconductor device, also have many technical barriers to be solved.
Summary of the invention
The present invention is intended to solve at least above-mentioned technological deficiency, and a kind of semiconductor device structure and manufacture method thereof are provided, and reduces cost, simplify processing step, by in semiconductor device, forming back of the body grid, strengthen the control to threshold voltage simultaneously, reduce short-channel effect, improve the performance of semiconductor device.
For reaching above-mentioned purpose, the invention provides a kind of semiconductor structure, this structure comprises substrate, semiconductor substrate, back of the body gate dielectric layer, back of the body grid, cavity, gate stack, side wall, source/drain region, wherein:
Described gate stack is positioned on the described semiconductor substrate;
Described side wall is positioned on the sidewall of described gate stack;
Described source/drain region is embedded in the described semiconductor substrate, is positioned at the both sides of described gate stack;
Described cavity is embedded in the described substrate;
Described semiconductor substrate is suspended in described cavity top, and along on the direction of grid length, the thickness in the middle of the described semiconductor substrate is greater than the thickness of its both sides, and along on the direction of grid width, described semiconductor substrate both sides link to each other with described substrate;
Described back of the body gate dielectric layer is positioned on the sidewall of described semiconductor substrate;
Described back of the body grid are positioned on the sidewall of described back of the body gate dielectric layer.
Wherein, the material of described back of the body gate dielectric layer is silica, silicon nitride, HfO
2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, Al
2O
3, La
2O
3, ZrO
2, a kind of or its combination among the LaAlO.
For PMOS, the material of described back of the body grid is MoN
x, TiSiN, TiCN, TaAlC, TiAlN, TaN, PtSi
x, Ni
3Si, Pt, Ru, Ir, Mo, HfRu, RuO
xIn a kind of or its combination; For NMOS, the material of described back of the body grid is TaC, TiN, TaTbN, TaErN, TaYbN, TaSiN, HfSiN, MoSiN, RuTa
x, NiTa
x
Correspondingly, the present invention also provides a kind of manufacture method of semiconductor structure, and the method comprises:
(a) provide substrate, form gate stack at described substrate, at the sidewall formation side wall of described gate stack;
(b) substrate in described gate stack both sides forms groove, and the groove of the described gate stack of wet etching both sides makes its break-through, forms cavity, and the substrate that is suspended on the described cavity partly forms semiconductor substrate;
(c) on the sidewall of described semiconductor substrate, form successively back of the body gate dielectric layer, back of the body grid;
(d) formation source/drain region.
Wherein, the method that forms described groove is:
Form mask layer at described substrate and gate stack;
Cover one deck photoresist at described mask layer, form opening by exposure imaging at photoresist, described opening is positioned at the both sides of described gate stack;
Mask layer in the described opening of etching removes described photoresist;
The described substrate of etching forms groove in the both sides of gate stack.
According to semiconductor structure provided by the invention and manufacture method thereof, adopt semiconductor etching process commonly used, on common wafer, can produce SON (silicon-on-nothing) device architecture, greatly simplified technique, reduce cost, improved efficient.Simultaneously, by in semiconductor device, forming back of the body grid, suppress short-channel effect, regulate the threshold voltage of semiconductor device, improve device performance, and reduce cost, simplify technique.
Description of drawings
Above-mentioned and/or the additional aspect of the present invention and advantage are from obviously and easily understanding becoming the description of embodiment below in conjunction with accompanying drawing, wherein:
Fig. 1 is the flow chart of an embodiment of the manufacture method of semiconductor structure, in accordance with the present invention;
Fig. 2 to Fig. 9 is in the cross-sectional view of each fabrication stage according to this semiconductor structure in the manufacturing of the method shown in Fig. 1 semiconductor structure process.
Embodiment
The below describes embodiments of the invention in detail, and the example of described embodiment is shown in the drawings, and wherein same or similar label represents same or similar element or the element with identical or similar functions from start to finish.Be exemplary below by the embodiment that is described with reference to the drawings, only be used for explaining the present invention, and can not be interpreted as limitation of the present invention.Disclosing hereinafter provides many different embodiment or example to be used for realizing different structure of the present invention.Of the present invention open in order to simplify, hereinafter parts and the setting of specific examples are described.Certainly, they only are example, and purpose does not lie in restriction the present invention.In addition, the present invention can be in different examples repeat reference numerals and/or letter.This repetition is in order to simplify and purpose clearly, itself not indicate the relation between the various embodiment that discuss of institute and/or the setting.In addition, the various specific technique that the invention provides and the example of material, but those of ordinary skills can recognize the property of can be applicable to of other techniques and/or the use of other materials.In addition, First Characteristic described below Second Characteristic it " on " structure can comprise that the first and second Characteristics creations are the direct embodiment of contact, also can comprise the embodiment of other Characteristics creation between the first and second features, such the first and second features may not be direct contacts.
The below at first summarizes semiconductor structure provided by the invention, please refer to Fig. 9.This semiconductor structure comprises substrate 100, semiconductor substrate 250, back of the body gate dielectric layer 260, back of the body grid 270, cavity 410, gate stack, side wall 230, source/drain region 500, wherein:
Described gate stack is positioned on the described semiconductor substrate 250;
Described side wall 230 is positioned on the sidewall of described gate stack;
Described source/drain region 500 is embedded in the described semiconductor substrate 250, is positioned at the both sides of described gate stack;
Described cavity 410 is embedded in the described substrate 100;
Described semiconductor substrate 250 is suspended in described cavity 410 tops, and along on the direction of grid length, the thickness in the middle of the described semiconductor substrate 250 is greater than the thickness of its both sides, and along on the direction of grid width, described semiconductor substrate 250 links to each other with described substrate;
Described back of the body gate dielectric layer 260 is positioned on the sidewall of described semiconductor substrate 250;
Described back of the body grid 270 are positioned on the sidewall of described semiconductor substrate 250;
Wherein, the material of described back of the body gate dielectric layer 260 is silica, silicon nitride, HfO
2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, Al
2O
3, La
2O
3, ZrO
2, a kind of or its combination among the LaAlO.
For PMOS, the material of described back of the body grid 270 is MoN
x, TiSiN, TiCN, TaAlC, TiAlN, TaN, PtSi
x, Ni
3Si, Pt, Ru, Ir, Mo, HfRu, RuO
xIn a kind of or its combination; For NMOS, the material of described back of the body grid 270 is TaC, TiN, TaTbN, TaErN, TaYbN, TaSiN, HfSiN, MoSiN, RuTa
x, NiTa
x
The below sets forth the manufacture method of this semiconductor structure.
Please refer to Fig. 1, the method comprises:
Step S101 provides substrate 100, forms gate stack at described substrate 100, at the sidewall formation side wall 230 of described gate stack;
Step S102, the substrate in described gate stack both sides forms groove 400, and the groove 400 of the described gate stack of wet etching both sides makes its break-through, forms cavity 410, and the substrate that is suspended on the described cavity 400 partly forms semiconductor substrate 250;
Step S103 forms back of the body gate dielectric layer 260, back of the body grid 270 successively on the sidewall of described semiconductor substrate 250;
Step S104, formation source/drain region 500.
Below in conjunction with Fig. 2 to Fig. 9 step S101 is described to step S104.Need to prove, the accompanying drawing of each embodiment of the present invention only is for the purpose of illustrating, therefore is not necessarily to scale.
With reference to figure 2, in step S101, provide substrate 100, form gate stack at described substrate 100 subsequently, at the sidewall formation side wall 230 of described gate stack.Described gate stack comprises gate dielectric layer 200 and grid 210, and alternatively, described gate stack also comprises the cover layer 220 that is positioned on the described grid.
In the present embodiment, substrate 100 is monocrystalline silicon.Preferably, the crystal face of substrate is { 100}.According to the known designing requirement of prior art (for example P type substrate or N-type substrate), substrate 100 can comprise various doping configurations.Substrate 100 can also comprise monocrystalline Ge, single crystalline Si Ge or its combination among other embodiment.Typically, the thickness of substrate 100 can be but be not limited to approximately hundreds of micron, for example can be in the thickness range of 400 μ m-800 μ m.
When forming gate stack, at first form gate dielectric layer 200 at substrate 100, in the present embodiment, described gate dielectric layer 200 can be combined to form for silica, silicon nitride or its, and in other embodiments, described gate dielectric layer 200 also can be high K dielectric, for example, HfO
2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, Al
2O
3, La
2O
3, ZrO
2, a kind of or its combination among the LaAlO, its thickness can be 1nm-5nm, such as 2nm, 4nm.Described grid 210 can be the heavily doped polysilicon that forms by deposition, or form first workfunction layers (for NMOS, TaC for example, TiN, TaTbN, TaErN, TaYbN, TaSiN, HfSiN, MoSiN, RuTa
x, NiTa
xDeng, for PMOS, MoN for example
x, TiSiN, TiCN, TaAlC, TiAlN, TaN, PtSi
x, Ni
3Si, Pt, Ru, Ir, Mo, HfRu, RuO
x), its thickness can be 1nm-20nm, such as 3nm, 5nm, 8nm, 10nm, 12nm or 15nm, forms heavily doped polysilicon, Ti, Co, Ni, Al, W or its alloy etc. and forms grid 210 in described workfunction layers again.Form cover layers 220 at grid 210 at last, for example be combined to form by deposited silicon nitride, silica, silicon oxynitride, carborundum or its, in order to protect the top area of grid 210.
Then, the sidewall formation side wall 230 at described gate stack is used for gate isolation is protected.Described side wall 230 can be by silicon nitride, silica, silicon oxynitride, carborundum or its combination, and/or other suitable materials form, and can have sandwich construction.Described side wall 230 can form by comprising deposition-etch technique, and its thickness range can be 10nm-100nm, such as 30nm, 50nm or 80nm.
With reference to figure 3, Fig. 4 and Fig. 5, in step S102, the substrate in described gate stack both sides forms groove 400, the groove 400 of the described gate stack of wet etching both sides, make its break-through, form cavity 410, the substrate that is connected across on the described cavity 400 partly forms semiconductor substrate 250.
At first, form groove 400 at described substrate 100, concrete grammar is, form mask layer 300 at described substrate 100 and gate stack, cover one deck photoresist at described mask layer 300, form opening by exposure imaging at photoresist, described opening is positioned at the both sides of described gate stack, and described photoresist is not shown in the diagram.Mask layer 300 in the described opening of etching forms opening 310 at mask layer, removes described photoresist, as shown in Figure 3.In the present embodiment, one side described opening 310 be connected to described side wall 230.In some other embodiment of the present invention, also can be across the described mask layer 300 of part between described opening 310 and described side wall 230, can reasonably arrange according to size of designed semiconductor device etc.Then the described substrate 100 of etching forms groove 400 in the both sides of gate stack, as shown in Figure 4.The material of described mask layer 300 is silica, silicon nitride, silicon oxynitride or its combination, can be formed on the described substrate by suitable methods such as chemical vapor depositions, the method of the described mask layer of etching comprises dry etching RIE, or adopts suitable corrosive liquid to carry out wet etching.The thickness of described mask layer can be controlled according to designing requirement, and its thickness range is 1～5 μ m.The method that the described substrate of etching forms groove 400 is dry etching RIE, by adjusting and the gas flow of control RIE equipment, component, power consumption etc., can obtain steep sidewall, perhaps as required, so that laterally undercutting increases.In the present embodiment, the groove 400 that dry etching goes out has the steep sidewall of being close to, and in follow-up wet etching, utilizes the anisotropy of wet etching, makes the described groove 400 mutual break-through of gate stack both sides.In some other embodiment of the present invention, also can increase the horizontal undercutting degree that etches groove 400 by adjusting the technological parameter of dry method RIE, help in subsequent step, make described groove 400 break-through.
As shown in Figure 5, after in the substrate of described gate stack both sides, forming groove 400, adopt wet corrosion technique to continue the described groove 400 of corrosion, make the groove break-through of gate stack both sides, form cavity 410, the unsettled substrate that is connected across described cavity top partly forms semiconductor substrate 250, in subsequent process steps, can be in semiconductor substrate 250 formation source/drain region, simultaneously semiconductor substrate 250 is also as the channel region of semiconductor device, along on the direction of grid width, the two ends of described semiconductor substrate link to each other with described substrate 100.In the present embodiment, the crystal face of described substrate is { 100}, the corrosive liquid of wet etching can be potassium hydroxide (KOH), Tetramethylammonium hydroxide (TMAH) or ethylenediamine-catechol (EDP) etc., or its combination, the concentration of corrosive liquid is 5～40% mass percents, and reaction temperature is 40 ℃～90 ℃.Corrosion has anisotropy because the corrosive liquids such as KOH, TMAH are to monocrystalline silicon, to { corrosion rate of 111} crystal face was almost 1: 100 with ratio to the corrosion rate of other crystal faces, therefore to { the 111} crystal face does not corrode substantially, as shown in Figure 5, the sidewall of described cavity 410 is all the etching-stop face, and crystal face is { 111}.Utilize anisotropic etch, so that described groove structure break-through.
Execution in step S103 forms back of the body gate dielectric layer 260, back of the body grid 270, as shown in Figure 6 successively on the sidewall of described semiconductor substrate 250.The material of described back of the body gate dielectric layer 260 is silica, silicon nitride, HfO
2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, Al
2O
3, La
2O
3, ZrO
2, a kind of or its combination among the LaAlO.For PMOS, the material of described back of the body grid 270 is MoN
x, TiSiN, TiCN, TaAlC, TiAlN, TaN, PtSi
x, Ni
3Si, Pt, Ru, Ir, Mo, HfRu, RuO
xIn a kind of or its combination; For NMOS, the material of described back of the body grid 270 is TaC, TiN, TaTbN, TaErN, TaYbN, TaSiN, HfSiN, MoSiN, RuTa
x, NiTa
xThe method that forms described back of the body gate dielectric layer 260, back of the body grid 270 is ald (ALD, Atom Layer Deposition).The concrete technology of described ald all can be adjusted according to product design flexibly such as technological temperature, reaction time and doping particle, repeats no more.Subsequently, carry out the RIE etching, remove at described gate stack and cover back of the body gate dielectric layer 260 and back of the body grid layer 270 on other zones of substrate, as shown in Figure 7.
With reference to figure 8, execution in step S 104, formation source/drain region 500.For PMOS, source/drain region 500 can be that the P type mixes, and for NMOS, source/drain region 500 can be that N-type is mixed.Before formation source/drain region 500, can pass through etched portions side wall 230, with increase source/drain region contact area, and then carry out Implantation, formation source/drain region 500, then described semiconductor structure is annealed, with the doping in activation of source/drain region 500, annealing can be adopted and comprise that other suitable methods such as short annealing, spike annealing form.Subsequently, remove mask layer 300, as shown in Figure 9, can also in cavity 410, fill heavily doped polysilicon or metal (not illustrating in the drawings) according to concrete designs, be used for the contact of back grid and draw.
Although describe in detail about example embodiment and advantage thereof, be to be understood that in the situation of the protection range that does not break away from the restriction of spirit of the present invention and claims, can carry out various variations, substitutions and modifications to these embodiment.For other examples, when those of ordinary skill in the art should easily understand within keeping protection range of the present invention, the order of processing step can change.
In addition, range of application of the present invention is not limited to technique, mechanism, manufacturing, material composition, means, method and the step of the specific embodiment of describing in the specification.From disclosure of the present invention, to easily understand as those of ordinary skill in the art, for the technique, mechanism, manufacturing, material composition, means, method or the step that have existed or be about to later on develop at present, wherein they carry out identical function or the identical result of acquisition cardinal principle of corresponding embodiment cardinal principle who describes with the present invention, can use them according to the present invention.Therefore, claims of the present invention are intended to these technique, mechanism, manufacturing, material composition, means, method or step are included in its protection range.
Claims (15)
1. semiconductor structure, this structure comprise substrate, semiconductor substrate, back of the body gate dielectric layer, back of the body grid, cavity, gate stack, side wall, source/drain region, wherein:
Described gate stack is positioned on the described semiconductor substrate;
Described side wall is positioned on the sidewall of described gate stack;
Described source/drain region is embedded in the described semiconductor substrate, and is positioned at the both sides of described gate stack;
Described cavity is embedded in the described substrate;
Described semiconductor substrate is suspended in described cavity top, and along on the direction of grid length, the thickness in the middle of the described semiconductor substrate is greater than the thickness of its both sides, and along on the direction of grid width, described semiconductor substrate both sides link to each other with described substrate;
Described back of the body gate dielectric layer is positioned on the sidewall of described semiconductor substrate;
Described back of the body grid are positioned on the sidewall of described back of the body gate dielectric layer.
2. semiconductor structure according to claim 1, wherein, the material of described substrate is single crystalline Si, monocrystalline Ge, single crystalline Si Ge or its combination.
3. semiconductor structure according to claim 1, wherein, the crystal face of described substrate is { 100}.
4. semiconductor structure according to claim 1, the material of wherein said back of the body gate dielectric layer is silica, silicon nitride, HfO
2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, Al
2O
3, La
2O
3, ZrO
2, a kind of or its combination among the LaAlO.
5. semiconductor structure according to claim 1, wherein:
For PMOS, the material of described back of the body grid is MoN
x, TiSiN, TiCN, TaAlC, TiAlN, TaN, PtSi
x, Ni
3Si, Pt, Ru, Ir, Mo, HfRu, RuO
xIn a kind of or its combination;
For NMOS, the material of described back of the body grid is TaC, TiN, TaTbN, TaErN, TaYbN, TaSiN, HfSiN, MoSiN, RuTa
x, NiTa
x
6. the manufacture method of a semiconductor structure, the method may further comprise the steps:
(a) provide substrate, form gate stack at described substrate, at the sidewall formation side wall of described gate stack;
(b) substrate in described gate stack both sides forms groove, and the groove of the described gate stack of wet etching both sides makes its break-through, forms cavity, and the substrate that is suspended on the described cavity partly forms semiconductor substrate;
(c) on the sidewall of described semiconductor substrate, form successively back of the body gate dielectric layer, back of the body grid;
(d) formation source/drain region.
7. method according to claim 6, wherein, the material of described substrate is single crystalline Si, monocrystalline Ge, single crystalline Si Ge or its combination.
8. method according to claim 6, wherein, the crystal face of described substrate is { 100}.
9. method according to claim 6, wherein, the method that forms groove in the step (b) is:
Form mask layer at described substrate and gate stack;
Cover one deck photoresist at described mask layer, form opening by exposure imaging at photoresist, described opening is positioned at the both sides of described gate stack;
Mask layer in the described opening of etching removes described photoresist;
The described substrate of etching forms groove in the both sides of gate stack.
10. method according to claim 9, wherein, the method that etching forms described groove is dry etching.
11. method according to claim 6, wherein, in the step (b), the corrosive liquid of the method for wet etching comprises potassium hydroxide (KOH), Tetramethylammonium hydroxide (TMAH), ethylenediamine-catechol (EDP) or its combination.
12. method according to claim 11, wherein, the concentration of described corrosive liquid is 5～40% mass percents, and reaction temperature is 40 ℃～90 ℃.
13. method according to claim 6, the material of wherein said back of the body gate dielectric layer are silica, silicon nitride, HfO
2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, Al
2O
3, La
2O
3, ZrO
2, a kind of or its combination among the LaAlO.
14. method according to claim 6, wherein:
For PMOS, the material of described back of the body grid is MoN
x, TiSiN, TiCN, TaAlC, TiAlN, TaN, PtSi
x, Ni
3Si, Pt, Ru, Ir, Mo, HfRu, RuO
xIn a kind of or its combination;
For NMOS, the material of described back of the body grid is TaC, TiN, TaTbN, TaErN, TaYbN, TaSiN, HfSiN, MoSiN, RuTa
x, NiTa
x
15. method according to claim 6, wherein, in the step (c), the method that forms described back of the body gate dielectric layer, back of the body grid is ald.
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|---|---|---|---|---|
| CN109573940A (en) * | 2017-09-29 | 2019-04-05 | 上海新微技术研发中心有限公司 | Semiconductor device and method of forming the same |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20040014280A1 (en) * | 2002-07-22 | 2004-01-22 | Josef Willer | Non-Volatile memory cell and fabrication method |
| US20060157789A1 (en) * | 2002-09-19 | 2006-07-20 | Kazumi Inoh | Semiconductor device with a cavity therein and a method of manufacturing the same |
| CN101609842A (en) * | 2008-06-20 | 2009-12-23 | 台湾积体电路制造股份有限公司 | Semiconductor device |
| US20100258871A1 (en) * | 2009-04-14 | 2010-10-14 | Hitachi, Ltd. | Semiconductor device and method of manufacturing the same |
| CN102104042A (en) * | 2009-12-21 | 2011-06-22 | 中国科学院微电子研究所 | Semiconductor device |
-
2011
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Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20040014280A1 (en) * | 2002-07-22 | 2004-01-22 | Josef Willer | Non-Volatile memory cell and fabrication method |
| US20060157789A1 (en) * | 2002-09-19 | 2006-07-20 | Kazumi Inoh | Semiconductor device with a cavity therein and a method of manufacturing the same |
| CN101609842A (en) * | 2008-06-20 | 2009-12-23 | 台湾积体电路制造股份有限公司 | Semiconductor device |
| US20100258871A1 (en) * | 2009-04-14 | 2010-10-14 | Hitachi, Ltd. | Semiconductor device and method of manufacturing the same |
| CN102104042A (en) * | 2009-12-21 | 2011-06-22 | 中国科学院微电子研究所 | Semiconductor device |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109573940A (en) * | 2017-09-29 | 2019-04-05 | 上海新微技术研发中心有限公司 | Semiconductor device and method of forming the same |
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