CN102855210B

CN102855210B - Method for realizing intercommunication and data sharing between two single-chip microcomputers

Info

Publication number: CN102855210B
Application number: CN201210307442.1A
Authority: CN
Inventors: 汪晓强; 郭忠慧; 刘晓文
Original assignee: FUJIAN LIDE AUTOMATION EQUIPMENT CO LTD
Current assignee: FUJIAN LIDE AUTOMATION EQUIPMENT CO LTD
Priority date: 2012-08-27
Filing date: 2012-08-27
Publication date: 2015-06-10
Anticipated expiration: 2032-08-27
Also published as: CN102855210A

Abstract

The invention relates to a method for realizing intercommunication and data sharing between two single-chip microcomputers, which is characterized in that the method comprises the following steps of: using an SRAM (static random access memory) for data communication and data sharing buffer memory between the two single-chip microcomputer, and controlling the peripheral memory interfaces of the single-chip microcomputers to be switched between a high-impedance state and a reading-writing state according to states of handshaking signal communication ports of the single-chip microcomputers, so as to ensure that only one single-chip microcomputer accesses to the SRAM at a time. The method is simple to realize; and compared with the prior art, the device cost is saved and the data communication speed is improved.

Description

A kind ofly realize two single-chip microcomputer intercommunications and the method for data sharing

Technical field

The present invention relates to single-chip data communication, technology of sharing field, particularly a kind ofly realize two single-chip microcomputer intercommunications and the method for data sharing.

Background technology

Between two single-chip microcomputers of current existence, data communication and data sharing mainly contain two kinds of methods: one. and universal serial bus realizes data communication between single-chip microcomputer, as UART, spi bus and iic bus etc.; Two. utilize dual port RAM to realize data communication and data sharing between single-chip microcomputer.Utilize above two kinds of methods to realize data communication and mainly there is following problem and shortage:

1. utilize universal serial bus to realize data communication between single-chip microcomputer, the unit transmitted due to universal serial bus is BIT, and the speed of communication receives restriction.

2. utilize universal serial bus to realize data communication between single-chip microcomputer, need to adopt and to improve and complicated communications protocol and transmitting-receiving flow process ensure integrality and the reliability of data, software simulating is comparatively complicated and comparatively take the calculation resources of single-chip microcomputer.

3. the method utilizing dual port RAM to realize data communication and data sharing between single-chip microcomputer needs to adopt extra dual port RAM hardware resource, and dual port RAM hardware belongs to special IC device, and device price is more expensive, and hardware cost certainly will be caused to increase.

4. the method utilizing dual port RAM to realize data communication and data sharing between single-chip microcomputer cannot meet the demand that big data quantity is shared because dual port RAM capacity is less.

Summary of the invention

For overcoming the problems referred to above, the object of this invention is to provide and a kind ofly realize two single-chip microcomputer intercommunications and the method for data sharing.

The present invention adopts following scheme to realize: a kind ofly realize two single-chip microcomputer intercommunications and the method for data sharing, it is characterized in that: adopt a slice SRAM as data communication and data sharing buffer memory between described two single-chip microcomputers, and switch between high-impedance state and read-write state according to the external memory interface of the state control single chip computer of the handshake communication port of single-chip microcomputer, to guarantee that a moment only has a single-chip microcomputer at this SRAM of access.

In an embodiment of the present invention, described handshake communication port is two I/O ports of described single-chip microcomputer.

In an embodiment of the present invention, described two I/O ports are defined as state input port and State-output mouth, during operation, whether what one single-chip microcomputer judged state input port is ' 1 ', SRAM is not read and write if ' 1 ' then identifies another single-chip microcomputer, at this moment State-output mouth set ' 0 ' is first identified this single-chip microcomputer and reads and writes SRAM by this single-chip microcomputer, the then operation that needs SRAM of this single-chip microcomputer; Just State-output mouth set ' 1 ' after this single-chip microcomputer terminates SRAM operation.

In an embodiment of the present invention, the external memory interface of described two single-chip microcomputers adopts mode in parallel to be connected to the external interface of described SRAM.

Implementation method of the present invention is simple, and relatively existing techniques save device cost, improves the speed of data communication.

Accompanying drawing explanation

Fig. 1 is circuit connection diagram of the present invention.

Fig. 2 is embodiment of the present invention single-chip microcomputer read-write schematic flow sheet.

Embodiment

Below in conjunction with drawings and Examples, the present invention will be further described.

As shown in Figure 1, the present embodiment provides a kind of and realizes two single-chip microcomputer intercommunications and the method for data sharing, it is characterized in that: adopt a slice SRAM as data communication and data sharing buffer memory between described two single-chip microcomputers, and switch between high-impedance state and read-write state according to the external memory interface of the state control single chip computer of the handshake communication port of single-chip microcomputer, to guarantee that a moment only has a single-chip microcomputer at this SRAM of access.In the present embodiment, described handshake communication port is two I/O ports of described single-chip microcomputer.

Please refer to Fig. 1 and Fig. 2, during operation, when single-chip microcomputer 1 will carry out read-write operation to SRAM, whether what first judge state input port is ' 1 ', if ' 1 ' mark single-chip microcomputer 2 is not is not read and write SRAM, at this moment State-output mouth set ' 0 ' mark single-chip microcomputer 1 is is first read and write (single-chip microcomputer 2 now can not operate SRAM) SRAM by single-chip microcomputer 1, the then operation that needs of single-chip microcomputer 1 couple of SRAM.Just State-output mouth set ' 1 ' (single-chip microcomputer 2 now can operate SRAM) after single-chip microcomputer 1 pair of SRAM operation terminates.Single-chip microcomputer 2 couples of SRAM(C) read-write operation identical with flow process single-chip microcomputer 1.

The foregoing is only preferred embodiment of the present invention, all equalizations done according to the present patent application the scope of the claims change and modify, and all should belong to covering scope of the present invention.

Claims

1. one kind realizes two single-chip microcomputer intercommunications and the method for data sharing, it is characterized in that: adopt a slice SRAM as data communication and data sharing buffer memory between described two single-chip microcomputers, and switch between high-impedance state and read-write state according to the external memory interface of the state control single chip computer of the handshake communication port of single-chip microcomputer, to guarantee that a moment only has a single-chip microcomputer at this SRAM of access, described handshake communication port is two I/O ports of described single-chip microcomputer, described two I/O ports are defined as state input port and State-output mouth, during operation, whether what one single-chip microcomputer judged state input port is ' 1 ', SRAM is not read and write if ' 1 ' then identifies another single-chip microcomputer, at this moment State-output mouth set ' 0 ' is first identified this single-chip microcomputer and reads and writes SRAM by this single-chip microcomputer, then this single-chip microcomputer operation that SRAM is needed, just State-output mouth set ' 1 ' after this single-chip microcomputer terminates SRAM operation, the external memory interface of described two single-chip microcomputers adopts mode in parallel to be connected to the external interface of described SRAM.