CN102841359B - Two-dimensional capturing method for carrier pseudo codes of direct sequence spread spectrum signals capable of preventing turnover of messages - Google Patents
Two-dimensional capturing method for carrier pseudo codes of direct sequence spread spectrum signals capable of preventing turnover of messages Download PDFInfo
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Abstract
The invention provides a two-dimensional capturing method for carrier pseudo codes of direct sequence spread spectrum signals capable of preventing turnover of messages. The two-dimensional capturing method is characterized in that turnover of messages can be prevented during the capturing progress of the direct sequence spread spectrum signals. The method comprises the specific steps of: obtaining two paths of in-phase and orthorhombic baseband signals; conducting delayed time processing of one time, two times, three times, ..., (N-1) times to the two paths of in-phase and orthorhombic baseband signals respectively, obtaining 2*N paths of parallel baseband signals; generating duplication codes by a pseudo code generator driven by a pseudo code clock, and conducting coherent accumulation operation to the 2*N paths of baseband signals and the duplication codes respectively by using 2*N parallel correlators; and then conducting double angle procession and FFT (Fast Fourier Transform) to a result of the accumulation operation, getting quadratic sums after the FFT; and selecting the maximum value in the quadratic sums and comparing the maximum value with a preset threshold, so as to conduct capturing.
Description
Technical field
The present invention relates to a kind of direct sequence signal carrier wave pseudo-code two dimension catching method of anti-text upset, belong to communication technical field.
Background technology
In actual spread spectrum communication system engineering, the DS mode is that what to use at present is at most, also most typical a kind of, and typical example has: the Galileo in the GPS of the U.S., Muscovite GLONASS, Europe and the Compass of China.
The fast Capture Technique of signal is one of gordian technique of receiver baseband signal processing.On satellite, the observing and controlling receiver produces local pseudo-code sequence, then must move the phase place of this local code, until occur relevant to the pseudo-code of receiving spread frequency signal.Simultaneously, also must transmit on detection ground, the carrier frequency territory carrier frequency of (upward signal) of receiver, method is to produce the local replica carrier frequency to add Doppler, utilizes the similarity of carrier wave and the up-link carrier of correlation detection local replica, realizes carrier synchronization.Therefore, receiver is a two dimension (pseudo-code and carrier frequency or be called the time and frequency) signal replication process to the acquisition procedure of signal.
In the TTC & DT Systems of space, the up direct sequence signal with remote information that space observing and controlling receiver receiving demodulation ground sends.The up remote information of S frequency range is the low-rate modulated application, and General Requirements is 2kbps ~ 16kbps.Simultaneously, receiver will complete the two-dimentional fast Acquisition of carrier doppler and pseudo-code phase.
For space observing and controlling receiver in up direct sequence signal is carried out to two-dimentional fast Acquisition process, the problem of modulating data upset impact.Doppler is estimated in the saltus step meeting of modulated data symbol and pseudorandom codes phase estimation exerts an influence: the spectral leakage of signal, frequency produce to be offset and cause can't detect correct Doppler frequency when utilizing Doppler filter group analysis signal spectrum.
Summary of the invention
The purpose of this invention is to provide a kind of direct sequence signal carrier wave pseudo-code two dimension catching method of anti-text upset, the method, in the acquisition procedure to direct sequence signal, can resist the upset of text.
Realize that technical scheme of the present invention is as follows:
Step 1, required intermediate frequency direct sequence signal of catching is carried out to the digital quadrature down-converted, obtain sine, cosine two paths of signals, then the sine, the cosine two paths of signals that obtain are multiplied each other with described intermediate frequency direct sequence signal respectively, obtain homophase, quadrature two-way baseband signal;
Step 2, homophase, quadrature two-way baseband signal are carried out respectively 1 time, 2 times, 3 times ..., (N-1) inferior delay process, obtain the parallel baseband signal in 2N road; Number of samples K=(the f of each time delay wherein
s/ f
c) * (L/N), f
sRepresent sampling rate, f
cMean pseudo-bit rate, L means the pseudo-code cycle;
Step 3, make the pseudo-code digital controlled oscillator produce the pseudo-code clock of 3.069MHz, pseudo-code generator generates replica code under the driving of pseudo-code clock, and the speed of the replica code generated is 3.069Mcps;
Step 4, utilize 2N parallel correlator to carry out respectively relevant accumulation computing to 2N roadbed band signal and replica code, the cycle that each accumulation computing wherein is set is 2ms, in the time range of 2ms, number of samples on signal is divided into to 512 parts, number of samples on every portion is accumulated, and then obtained 2N road accumulation operation result; Homophase with same time delay, the accumulation operation result of digital orthogonal baseband signal are merged into to a road, are obtained the accumulation result of N road after merging;
Step 5, the accumulation result after the N road is merged adopt respectively formula (1) and (2) to carry out a times angle processing, obtain N road signal group, and wherein each signal group comprises I (n) and Q (n),
I(n)＝r
I(n)×r
I(n)-r
Q(n)×r
Q(n)（1）
Q(n)＝r
I(n)×r
Q(n)+r
Q(n)×r
I(n)（2）
R wherein
I(n) be the accumulation result of in-phase base band signal, r
Q(n) be the accumulation result of digital orthogonal baseband signal, * for multiplying, n is all integers of getting all in 1 to 512;
Step 6, for each road in the signal group of N road, to I (n) rear end zero padding to 1024 accumulation result, to Q (n) rear end zero padding to 1024 accumulation result; Then the real part converted I (n) as Fourier FFT, the imaginary part of conversion using Q (n) as FFT, respectively N road signal is carried out to Fast Fourier Transform (FFT), obtain real part, imaginary part and exponential part after FFT converts, then calculate real part after FFT conversion and the quadratic sum of imaginary part, obtain altogether 1024 * N quadratic sum;
Step 7, relatively 1024 * N the quadratic sum of passing through, select maximal value and default thresholding wherein to compare, when comparative result is preset thresholding for surpassing, think acquisition success, obtain the corresponding retardation of maximum quadratic sum, utilize this retardation to produce a thick synchronous replica code for accurate pseudo-code tracing, and 1024 * N FFT position corresponding to quadratic sum maximal value represented that carrier doppler catches result; When obtaining comparative result when being less than thresholding, judge and catch unsuccessfully, next coherent integration period is come, and controls pseudo-code generator 0.5 chip that slides and generates replica code, returns to step 3.
Beneficial effect
The present invention utilizes in frequency domain FFT acquisition algorithm, before FFT, adopts double angle formula to be processed homophase, quadrature two paths of signals, eliminates the problem that can't detect correct Doppler frequency when Data Modulation causes FFT to carry out doppler frequency spectrum analysis.
The accompanying drawing explanation
The process flow diagram that Fig. 1 is catching method of the present invention.
Embodiment
Below in conjunction with the drawings and specific embodiments, the present invention is described in detail.
This invention be embodied as a measurement and control unit, adopt the hardware such as FPGA and A/D converter to realize.Fpga chip is selected the product XC2V3000 of U.S. Xilinx company, and its dominant frequency reaches as high as 300MHz, and FPGA (Field Programmable Gate Array) can reach 3,000,000.A/D conversion chip is selected the product A D10200 of U.S. Analogic Corp., and its highest sample frequency is 105MHz, and data resolution is 12.The analog if signal of input is converted to the intermediate frequency direct sequence signal after the bandpass sampling of A/D chip, and in FPGA, settling signal catches.
Comprise digital quadrature down conversion module, parallel correlator group, pseudo-code generator, FFT conversion module, magnitude calculation module, catch processing module etc. at FPGA.The scheme adopted based on frequency domain FFT parallel-time domain multidiameter delay code acquisition algorithm, the flow process of processing as shown in Figure 1, below is implemented to be set forth to invention.
FPGA described in the present embodiment adopts the work clock of 38MHz, and 38MHz is also used as the change over clock of A/D simultaneously.Analog if signal, through analog to digital conversion, is exported the intermediate frequency direct sequence signal of the sample value of per second 38M, the input by 12 interfaces as FPGA.
As shown in Figure 1, concrete acquisition procedure is as follows:
Step 1, required intermediate frequency direct sequence signal of catching is carried out to the digital quadrature down-converted, obtain sine, cosine two paths of signals, then the sine, the cosine two paths of signals that obtain are multiplied each other with described intermediate frequency direct sequence signal respectively, obtain homophase, quadrature two-way baseband signal.
Step 2, the mode delay input signal by the RAM resource with first-in first-out, adopt through (N-1) group RAM and carry out delay disposal, and homophase, quadrature two-way baseband signal are become to 2N road parallel signal; For homophase and digital orthogonal baseband signal, the N road is equivalent to differ in time L/N chip with respect to the N-1 road.The N road walks abreast and can realize searching for N pseudo-code phase that is spaced apart the L/N chip simultaneously like this.Concrete process is: homophase, quadrature two-way baseband signal carried out respectively 1 time, and 2 times, 3 times ..., (N-1) inferior delay process, wherein the number of samples K=(f of each time delay
s/ f
c) * (L/N), f
sRepresent sampling rate, f
cMean pseudo-bit rate, L means the pseudo-code cycle, and N means parallel way, and then obtains the parallel baseband signal in 2N road.In this enforcement, preferably make L equal 1023, preferably make N equal 8, following steps all make N equal 8 and describe.
Due to each road signal has all been carried out respectively to 7 kinds of time delays, add that a road that there is no time delay obtains 8 road signals altogether, therefore consider that each road comprises again homophase and quadrature, obtain altogether 16 road signals, in the signal of resulting 2N road, if only there is 1 time delay, amount of delay is K, if there are 2 time delays, amount of delay is 2K, and therefore analogize, obtained 16 road signals.
Differ successively 8 road signals of L/N code phase on generation time, then with the local replica pseudo code correlation, when local copy codes slides into certain phase place, N the phase place that be equivalent to parallel detection.
Step 3, make the pseudo-code digital controlled oscillator produce the pseudo-code clock of 3.069MHz, pseudo-code generator generates replica code under the driving of pseudo-code clock, and the speed of the replica code generated is 3.069Mcps.
Step 4, utilize 16 parallel correlators to carry out respectively relevant accumulation computing to 16 road homophases, digital orthogonal baseband signal to replica code, the cycle that each accumulation computing wherein is set is 2ms, in the time range of 2ms, number of samples on signal is divided into to 512 parts, each increment is counted and accumulated, and then obtain 16 tunnel integral operation results.For the homophase with same time delay, quadrature base band data, homophase, quadrature two-way base band data are merged into to a road to the relevant accumulation results of replica code, obtain the accumulation result of 8 tunnels after merging.
Step 5, the accumulation result after 8 tunnels are merged adopt respectively formula (1) and (2) to carry out times angle and process, and the impact of elimination Data Modulation, obtain N road signal group, and wherein each signal group comprises I (n) and Q (n),
I(n)＝r
I(n)×r
I(n)-r
Q(n)×r
Q(n)（1）
Q(n)＝r
I(n)×r
Q(n)+r
Q(n)×r
I(n)（2）
R wherein
I(n) be the accumulation result of in-phase base band signal, r
Q(n) be the accumulation result of digital orthogonal baseband signal, * for multiplying, n is all integers of getting all in 1 to 512.
The homophase accumulation result I (n) and the quadrature accumulation result Q (n) that computing are obtained, eliminate the impact of Data Modulation are kept in the inside dual port RAM of FPGA.The result produced due to each 2ms time is 512,8 tunnel value, by ping-pong operation, is kept in the internal RAM of FPGA, therefore needs 16 block RAMs that storage depth is 512.
Step 6, sense data from the dual port RAM of FPGA inside successively, for each road in the signal group of N road, to I (n) rear end zero padding to 1024 accumulation result, to Q (n) rear end zero padding to 1024 accumulation result; Then the real part converted I (n) as Fourier FFT, the imaginary part of conversion using Q (n) as FFT, 8 road signals complete respectively Fast Fourier Transform (FFT) and calculate, the FFT computing is used the IP kernel of Xilinx company to realize, real part, imaginary part and exponential part that the exportable FFT computing of this IP kernel obtains, the quadratic sum that calculates real part after FFT conversion and imaginary part is delivered to peak value and is detected, and the quadratic sum wherein calculated has 1024 * 8=8192.
Step 7, relatively 8192 quadratic sums of passing through, select maximal value and default thresholding wherein to compare, when comparative result is preset thresholding for surpassing, think acquisition success, obtain the corresponding retardation of maximum quadratic sum, utilize this retardation to produce a thick synchronous replica code for accurate pseudo-code tracing, and FFT position corresponding to maximal value represented the doppler values of catching; , judge and catch unsuccessfully for being less than thresholding when comparative result, to next coherent integration period, come, code NCO controls the slip of a replica code chip, enters next group code phase search unit.
Use the coherent integration period of 2ms, use the counter cycle count, when reaching 2ms+t
1Constantly, the register of pseudo-code generator is composed as first phase value, the value zero clearing of unison counter.According to t
1Can calculate the number of chips that each replica code slides, every 2ms once slides.Known integration period is 2ms, t
1Be chosen as 1 ~ 9 work clock cycle.
Use the coherent integration period of 2ms, the frequency resolution of FFT is 1/2ms=500Hz, and 2ms sampling point integration is 512 accumulated values, and corresponding capturing carrier scope is 500Hz * 512/2=128kHz ,-64kHz ~+63kHz.Adopt 1024 FFT, the frequency resolution of catching corresponding to each FFT sample value is 128kHz/1024=125Hz.
The present invention can overcome the impact that the text upset is caught carrier doppler, has capturing carrier speed and high reliability fast.And be combined with time-domain parallel multichannel pseudo-code searching method and can realize carrier wave and pseudo-code two dimension fast Acquisition.
In sum, these are only preferred embodiment of the present invention, be not intended to limit protection scope of the present invention.Within the spirit and principles in the present invention all, any modification of doing, be equal to replacement, improvement etc., within all should being included in protection scope of the present invention.
Claims (1)
1. the direct sequence signal carrier wave pseudo-code two dimension catching method of an anti-text upset, is characterized in that,
Step 1, required that catch, intermediate frequency direct sequence signal is carried out to the digital quadrature down-converted, obtain sine, cosine two paths of signals, then the sine, the cosine two paths of signals that obtain are multiplied each other with described intermediate frequency direct sequence signal respectively, obtain homophase, quadrature two-way baseband signal;
Step 2, homophase, quadrature two-way baseband signal are carried out respectively 1 time, 2 times, 3 times ..., N-1 delay process, obtain the parallel baseband signal in 2N road; Number of samples K=(the f of each time delay wherein
s/ f
c) * (L/N), f
sRepresent sampling rate, f
cMean pseudo-bit rate, L means the pseudo-code cycle;
Step 3, make the pseudo-code digital controlled oscillator produce the pseudo-code clock of 3.069MHz, pseudo-code generator generates replica code under the driving of pseudo-code clock, and the speed of the replica code generated is 3.069Mcps;
Step 4, utilize 2N parallel correlator to carry out respectively relevant accumulation computing to 2N roadbed band signal and replica code, the cycle that each accumulation computing wherein is set is 2ms, in the time range of 2ms, number of samples on signal is divided into to 512 parts, number of samples on every portion is accumulated, and then obtained 2N road accumulation operation result; Homophase with same time delay, the accumulation operation result of digital orthogonal baseband signal are merged into to a road, are obtained the accumulation result of N road after merging;
Step 5, the accumulation result after the N road is merged adopt respectively formula (1) and (2) to carry out a times angle processing, obtain N road signal group, and wherein each signal group comprises I (n) and Q (n),
I(n)=r
I(n)×r
I(n)-r
Q(n)×r
Q(n) （1）
Q(n)=r
I(n)×r
Q(n)+r
Q(n)×r
I(n) （2）
R wherein
I(n) be the accumulation result of in-phase base band signal, r
Q(n) be the accumulation result of digital orthogonal baseband signal, * for multiplying, n is all integers of getting all in 1 to 512;
Step 6, for each road in the signal group of N road, to I (n) rear end zero padding to 1024 accumulation result, to Q (n) rear end zero padding to 1024 accumulation result; Then the real part converted I (n) as Fourier FFT, the imaginary part of conversion using Q (n) as FFT, respectively N road signal is carried out to Fast Fourier Transform (FFT), obtain real part, imaginary part and exponential part after FFT converts, then calculate real part after FFT conversion and the quadratic sum of imaginary part, obtain altogether 1024 * N quadratic sum;
Step 7, relatively 1024 * N the quadratic sum of passing through, select maximal value and default thresholding wherein to compare, when comparative result is preset thresholding for surpassing, think acquisition success, obtain the corresponding retardation of maximum quadratic sum, utilize this retardation to produce a thick synchronous replica code for accurate pseudo-code tracing; When obtaining comparative result when being less than thresholding, judge and catch unsuccessfully, next coherent integration period is come, and controls pseudo-code generator 0.5 chip that slides and generates replica code, returns to step 3.
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| CN111262618B (en) * | 2020-01-17 | 2020-09-29 | 北京理工大学 | Solution method for multi-target measurement and control signal parallel access based on same pseudo code |
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