CN102815662A - Method for preparing cavity in semiconductor substrate - Google Patents
Method for preparing cavity in semiconductor substrate Download PDFInfo
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- CN102815662A CN102815662A CN2011101517562A CN201110151756A CN102815662A CN 102815662 A CN102815662 A CN 102815662A CN 2011101517562 A CN2011101517562 A CN 2011101517562A CN 201110151756 A CN201110151756 A CN 201110151756A CN 102815662 A CN102815662 A CN 102815662A
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Abstract
The invention provides a method for preparing a cavity in a semiconductor substrate, and belongs to the field of integrated circuit manufacturing technology. The method comprises the steps of providing a semiconductor substrate, forming a plurality of through holes or grooves via anisotropic etching on the semiconductor substrate; performing isotropic etching on the through holes to make the adjacent through holes or the bottoms of the adjacent grooves communicated mutually to form a cavity slot; epitaxially growing an epitaxial semiconductor substrate layer to seal and form the cavity. The method has the characteristics of low cost, high efficiency and easily controllable thickness of the semiconductor substrate layer on the cavity.
Description
Technical field
Belong to the ic manufacturing technology field, relate to the method that in Semiconductor substrate, prepares cavity.
Background technology
In the manufacturing of integrated circuit, need in Semiconductor substrate, (for example in the silicon substrate) form cavity usually.This Semiconductor substrate that has cavity further is used for preparing other IC-components (for example, MEMS device).Therefore, the preparation cost of cavity and efficient directly influence the preparation cost and the efficient of IC-components.
The structural change sketch map of procedure of preparation cavity in Semiconductor substrate that provides for prior art shown in Figure 1.As shown in Figure 1, be that monocrystalline silicon piece is an example with the Semiconductor substrate, at first; Patterned etch forms cavity 110 on the substrate 100 of silicon chip A, and simultaneously, patterned etch forms cavity 210 on the substrate 200 of silicon chip B; Cavity 210 and cavity 110 etching formation simultaneously, and have essentially identical shape.Further, silicon chip A and silicon chip B are carried out bonding, in this step; After any upset in two silicon chips, make that two cavitys (110 and 210) are basic to be aimed at, then; Adopt conventional bonding technology and bonding apparatus; Make mutual bonding between two silicon chips, silicon substrate 100 and 200 integrators, and formed hermetic cavity body 310 therein.Further, behind two wafer bondings, the substrate thickness of cavity 310 tops is to be determined by silicon wafer thickness; Therefore; Normally need carry out attenuate, promptly be kept to thickness d by the thickness D shown in Fig. 1, this process is normally accomplished by the method for cmp (CMP).
But preparation method shown in Figure 1 has following shortcoming at least:
The first, the bonding technology cost is high, and with respect to the conventional cmos integrated circuit production line, the employed bonding apparatus of bonding technology is not required, therefore, needs to buy in addition the bonding apparatus of high value usually;
The second, in the thinning process, be difficult to control the thickness of the substrate of institute's attenuate, also promptly be difficult to control the substrate thickness (d) of cavity top;
The 3rd, whole technological process is complicated, length consuming time, and production efficiency is low.
In view of this, be necessary to propose a kind of novel cavity preparation method.
Summary of the invention
The objective of the invention is to, reduce the preparation cost of cavity, improve its production efficiency.
For realizing above purpose or other purpose, the present invention provides a kind of method that in Semiconductor substrate, prepares cavity, and it may further comprise the steps:
Semiconductor substrate is provided, and the anisotropy patterned etch forms a plurality of through holes or groove on said Semiconductor substrate;
Said through hole is carried out isotropic etching form the cavity groove so that be interconnected between the bottom of adjacent through-holes or adjacent trenches; And
Epitaxial growth epitaxial semiconductor substrate layer forms said cavity with sealing.
According to an embodiment who prepares the method for cavity provided by the invention, wherein, said a plurality of through holes desire in said Semiconductor substrate forms the zone of said cavity and arranges basically equally spacedly.
Preferably, the scope of said spacing is 1um to 5um basically, and the pore diameter range of said through hole is 0.8um to 3um basically
Preferably, the depth bounds of the hole depth scope of said through hole or said groove can be 1um to 10um basically.
Preferably, said etching is a reactive ion etching.
Preferably, said cavity slot pitch is 1um to 10um from the distance of the upper surface of said Semiconductor substrate basically.
According to the another embodiment of method for preparing cavity provided by the invention, said epitaxial semiconductor substrate layer basically only grows on the upper surface of said Semiconductor substrate.
Preferably, said epitaxially grown temperature is arranged on 1080 ℃ to 1200 ℃.
Preferably, said epitaxially grown growth gasses is SiH
2Cl
2, SiHCl
3Perhaps SiCl
4
In an instantiation, said Semiconductor substrate is a silicon substrate.
Technique effect of the present invention is; The present invention utilizes the characteristics of isotropic etching method, the through hole of anisotropic etching formation or the bottom of groove are communicated with formation cavity groove, and further extension generates the cavity in the formation Semiconductor substrate; Therefore; Only need a slice Semiconductor substrate, preparation method's process is simple, cost is low, and production efficiency is high.Simultaneously,, therefore need not purchase new process equipment, help reducing cost yet for the preparation of cavity because lithographic method used in the present invention and epitaxial growth method are CMOS integrated circuit preparation technology's common methods.Further, through epitaxially grown method, the thickness of the semiconductor substrate layer on the cavity is easy to control.
Description of drawings
From the following detailed description that combines accompanying drawing, will make above and other objects of the present invention and advantage clear more fully, wherein, same or analogous key element adopts identical label to represent.
Fig. 1 is the structural change sketch map that in Semiconductor substrate, prepares the procedure of cavity that prior art provides.
Fig. 2 is the method flow sketch map of the preparation cavity that provides according to one embodiment of the invention.
Fig. 3 to Fig. 6 is the structural change sketch map corresponding to flowchart process shown in Figure 2.
Fig. 7 is the structural representation behind the anisotropic etching formation groove in the another method embodiment of preparation cavity.
The specific embodiment
What introduce below is some among a plurality of possibility embodiment of the present invention, aims to provide basic understanding of the present invention.Be not intended to confirm key of the present invention or conclusive key element or limit claimed scope.Understand easily, according to technical scheme of the present invention, do not changing under the connotation of the present invention, but one of ordinary skill in the art can propose other implementation of mutual alternative.Therefore, the following specific embodiment and accompanying drawing only are the exemplary illustrations to technical scheme of the present invention, and should not be regarded as qualification or the restriction to technical scheme of the present invention that all perhaps be regarded as of the present invention.
In the accompanying drawings, for the sake of clarity, exaggerated the thickness in layer and zone, and, because the mellow and full shape facility that waits that etching causes does not illustrate in the accompanying drawing.
Method flow sketch map for the preparation cavity that provides according to one embodiment of the invention shown in Figure 2.Fig. 3 is extremely shown in Figure 6 to be the structural change sketch map corresponding to flowchart process shown in Figure 2.Below in conjunction with Fig. 2 to Fig. 6 the method for preparing cavity is elaborated.
At first, step S10, the anisotropy patterned etch forms a plurality of through holes of equidistant arrangement on silicon substrate.
As shown in Figure 3, in this embodiment, Semiconductor substrate is normally used silicon substrate 500 (a for example monocrystalline silicon piece).Fig. 3 (a) is depicted as the silicon substrate vertical view behind the formation through hole, and Fig. 3 (b) is depicted as the silicon substrate sectional view behind the formation through hole.A plurality of through holes 510 are formed in the silicon substrate 500, and are arranged in the zone (shown in the figure frame of broken lines) that the silicon substrate desire forms cavity.Can arrange basically equally spacedly between the through hole 510, its spacing range each other is 1um to 5um (for example being 2um), correspondingly; The pore diameter range of through hole 510 is 0.8um to 3um (for example being 1mm); Usually, the aperture is big more, and the spacing between the through hole also can be selected bigger.The hole depth h scope of through hole 510 is 1um to 10um (for example being 5um).In this embodiment; Desire forms on the zone (shown in frame of broken lines among the figure) of cavity; 30 through holes 510 are arranged by two row, 15 row, still, need to prove; The quantity of through hole 510, shape (for example circular or square) and concrete arrangement mode are not restrictive, and the shape size in the zone of the cavity that those skilled in the art can form according to desire, condition of etching or the like are selected.
In this step, through hole 510 is to adopt the anisotropic etching method to form, and preferably, adopts reactive ion etching method, and it is a kind of of dry etching, is easy to like this form that the aperture is less, through hole that up rightness is good, that depth-to-width ratio is bigger.Particularly, in etching process, can adopt SF
6Gas is as etching gas; The range of flow of gas is 30sccm to 250sccm; And can adopt the reactive ion etching method that stringer silicon step and etch silicon step hocket to come etching to form through hole 510 earlier; Also can adopt the method etching that stringer silicon step and etch silicon step carry out simultaneously to form through hole 510, can keep the characteristics of good anisotropic etching like this, the through hole up rightness is good.Because this etching process is anisotropic, therefore, can form the through hole that is basically perpendicular to substrate surface shown in Fig. 3 (b).
Further, step S20 carries out isotropic etching to each through hole and forms the cavity groove so that be interconnected between the bottom of adjacent through-holes.
In this step; The characteristics (this is to be avoided in the common etching process as far as possible) of anisotropic etching conformality difference have been utilized; Silicon between the bottom of adjacent through-holes is etched away under the effect of isotropic etching basically, forms the cavity groove thereby can be communicated with.Particularly, as shown in Figure 4, in this embodiment; Preferably adopt the dry etching method of reactive ion etching, when continuing to the bottom etching, the process conditions of control reactive ion etching; Make it to become isotropic etching (being that master, physical etchings speed are less relatively wherein) with the chemical reaction etching; Therefore, through hole 510 bottoms can be with very fast speed lateral etching, until; Silicon substrate between the via bottoms is etched away, thereby forms the cavity groove 610a that is interconnected and forms in its bottom between each through hole as shown in Figure 5.In this embodiment, can in silicon substrate 500, basically form the cavity groove 610a into rectangular shape, still, concrete shape and the size of cavity groove 610a neither be restrictive.Wherein, Cavity groove 610a apart from the scope of the distance h 1 of the upper surface of silicon substrate 500 (also i.e. the degree of depth of residual flux bore portion 510 among the figure) can for 1um to 10um (for example; 3um), the concrete size of h1 is confirmed by the factors such as process conditions of hole depth h and isotropic etching.
Further, step S30, the epitaxial growth silicon layer forms cavity with sealing.
As shown in Figure 6, through epitaxial growth silicon layer 600, be covered on the silicon substrate 500, thereby seal chamber groove 610a (as shown in Figure 5) forms cavity 610, cavity 610 is appreciated that the enclosure space into cavity groove 610a and partial through holes.In this embodiment, silicon epitaxial layers 600 basically only grows on the upper surface of silicon substrate 500, also promptly, during epitaxial growth, basically can be in cavity 610a growing epitaxial layers; Therefore, the epitaxial surface of silicon epitaxial layers 600 (also being the upper surface of silicon epitaxial layers 600) is more smooth, helps further making in the epitaxial silicon layer 600 other device like this.Reach above-described extension generation requirement through controlling epitaxially grown condition.In a preferred embodiment, select SiH
2Cl
2, SiHCl
3Perhaps SICl
4As epitaxially grown reacting gas, epitaxially grown temperature is arranged on 1080 ℃ to 1200 ℃, (for example 1100 ℃), can selective epitaxy the temperature range of growth be 1120 ℃ to 1150 ℃.Therefore, the flatness of the epitaxial surface of the silicon epitaxial layers 600 of extension generation can reach in 1000 dusts.
In addition, through controlling epitaxially grown speed and epitaxially grown time, can accurately control the thickness h 2 of silicon epitaxial layers 600, this controls the thickness of the substrate on the cavity more easily than method shown in Figure 1.
So far, in silicon substrate, formed described cavity like Fig. 6.
Need to prove; Although be that instance has been explained the method that forms cavity therein with the silicon substrate among the above embodiment; Those skilled in the art are according to above instruction and enlightenment; Can the basic principle of above procedure be applied to form cavity in other Semiconductor substrate, for example, polysilicon substrate, GaN Semiconductor substrate or the like.
In the another method embodiment of preparation cavity, also be mainly according in the method flow shown in Figure 1, main difference is that through hole is substituted by groove.This be because, the structure that forms at anisotropic etching stage institute's composition is not restrictive.In this embodiment, step S10 is a plurality of grooves that anisotropic etching forms equidistant arrangement on silicon substrate.The structural representation that is after anisotropic etching forms groove shown in Figure 7.As shown in Figure 7; In the square arrangement equally spacedly of its width, its spacing range each other is 1um to 5um (for example being 2um), correspondingly between a plurality of grooves 710; The width range of groove 710 is 0.8um to 3um (for example being 1mm); Usually, width is big more, and the spacing between the groove also can be selected bigger.The shape of the cavity that the length of groove 710 can form according to desire is confirmed.The degree of depth h scope of groove 710 also can be 1um to 10um (for example being 5um).Step after groove 710 forms and other step embodiment illustrated in fig. 1 are basic identical, for example, each groove is carried out isotropic etching form the cavity groove so that be interconnected between the bottom of adjacent through-holes, therefore, describe no longer one by one at this.
Above example has mainly been explained cavity preparation method of the present invention.Although only some of them embodiment of the present invention is described, those of ordinary skills should understand, and the present invention can be in not departing from its purport and scope implements with many other forms.Therefore, example of being showed and embodiment are regarded as schematic and nonrestrictive, are not breaking away under the situation of liking defined spirit of the present invention of each claim and scope enclosed, and the present invention possibly contained various modifications and replacement.
Claims (10)
1. a method that in Semiconductor substrate, prepares cavity is characterized in that, may further comprise the steps:
Semiconductor substrate is provided, and the anisotropy patterned etch forms a plurality of through holes or groove on said Semiconductor substrate;
Said through hole is carried out isotropic etching form the cavity groove so that be interconnected between the bottom of adjacent through-holes or adjacent trenches; And
Epitaxial growth epitaxial semiconductor substrate layer forms said cavity with sealing.
2. the method for claim 1 is characterized in that, said a plurality of through holes or groove desire in said Semiconductor substrate forms the zone of said cavity and arranges basically equally spacedly.
3. method as claimed in claim 2 is characterized in that, the scope of said spacing is 1um to 5um basically, and the width range of the pore diameter range of said through hole or said groove is 0.8um to 3um basically.
4. like claim 1 or 2 or 3 described methods, it is characterized in that the depth bounds of the hole depth scope of said through hole or said groove is 1um to 10um basically.
5. the method for claim 1 is characterized in that, said etching is a reactive ion etching.
6. the method for claim 1 is characterized in that, said cavity slot pitch is 1um to 10um from the distance of the upper surface of said Semiconductor substrate basically.
7. the method for claim 1 is characterized in that, said epitaxial semiconductor substrate layer basically only grows on the upper surface of said Semiconductor substrate.
8. the method for claim 1 is characterized in that, said epitaxially grown temperature is arranged on 1080 ℃ to 1200 ℃.
9. the method for claim 1 is characterized in that, said epitaxially grown growth gasses is SiH
2Cl
2, SiHCl
3Perhaps SiH
4
10. the method for claim 1 is characterized in that, said Semiconductor substrate is a silicon substrate.
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| CN2011101517562A CN102815662A (en) | 2011-06-08 | 2011-06-08 | Method for preparing cavity in semiconductor substrate |
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103449358A (en) * | 2013-08-27 | 2013-12-18 | 上海先进半导体制造股份有限公司 | Manufacturing method of closed cavity of micro-electromechanical system (MEMS) |
| WO2019007324A1 (en) * | 2017-07-03 | 2019-01-10 | 无锡华润上华科技有限公司 | Method for manufacturing dual-cavity structure, and dual-cavity structure |
| CN109399553A (en) * | 2017-08-15 | 2019-03-01 | 无锡华润上华科技有限公司 | A kind of preparation method of semiconductor devices |
| CN109399555A (en) * | 2017-08-18 | 2019-03-01 | 无锡华润上华科技有限公司 | A kind of preparation method of semiconductor devices |
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| CN103449358A (en) * | 2013-08-27 | 2013-12-18 | 上海先进半导体制造股份有限公司 | Manufacturing method of closed cavity of micro-electromechanical system (MEMS) |
| WO2019007324A1 (en) * | 2017-07-03 | 2019-01-10 | 无锡华润上华科技有限公司 | Method for manufacturing dual-cavity structure, and dual-cavity structure |
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| CN109399553A (en) * | 2017-08-15 | 2019-03-01 | 无锡华润上华科技有限公司 | A kind of preparation method of semiconductor devices |
| CN109399555A (en) * | 2017-08-18 | 2019-03-01 | 无锡华润上华科技有限公司 | A kind of preparation method of semiconductor devices |
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Effective date of registration: 20140403 Address after: 214028 Wuxi provincial high tech Industrial Development Zone, Hanjiang Road, No. 5, Jiangsu, China Applicant after: Wuxi CSMC Semiconductor Co., Ltd. Address before: 214028 Wuxi provincial high tech Industrial Development Zone, Hanjiang Road, No. 5, Jiangsu, China Applicant before: Wuxi CSMC Semiconductor Co., Ltd. Applicant before: Wuxi Huarun Shanghua Technology Co., Ltd. |
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Application publication date: 20121212 |