CN102800971A - Meta-material preparation method based on semiconductor and meta-material based on semiconductor - Google Patents

Meta-material preparation method based on semiconductor and meta-material based on semiconductor Download PDF

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CN102800971A
CN102800971A CN2011101457608A CN201110145760A CN102800971A CN 102800971 A CN102800971 A CN 102800971A CN 2011101457608 A CN2011101457608 A CN 2011101457608A CN 201110145760 A CN201110145760 A CN 201110145760A CN 102800971 A CN102800971 A CN 102800971A
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semiconductor layer
photoresist
semiconductor
layer
impurity
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CN102800971B (en
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刘若鹏
赵治亚
缪锡根
杨宗荣
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Kuang Chi Institute of Advanced Technology
Kuang Chi Innovative Technology Ltd
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Kuang Chi Institute of Advanced Technology
Kuang Chi Innovative Technology Ltd
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Abstract

The invention provides a meta-material preparation method based on a semiconductor. The meta-material preparation method comprises the following steps of: forming a semiconductor layer on a substrate; coating a layer of photoresist on the semiconductor layer; using a template with a pre-set micro-structure array as a mask plate to photo-etch the photoresist; doping impurities in the semiconductor according to pre-set electromagnetic parameters; and removing the photoresist coated on the semiconductor, so as to obtain a meta-material. The embodiment of the invention further provides the meta-material based on the semiconductor. The meta-material which has higher controllable property of a micro-structure and meets design requirements can be obtained.

Description

The ultra material preparation method of based semiconductor and the ultra material of based semiconductor
[technical field]
The present invention relates to technical field of composite materials, relate in particular to a kind of ultra material preparation method of based semiconductor and the ultra material of based semiconductor.
[background technology]
Along with the fast development of new and high technologies such as radar detection, satellite communication, Aero-Space, and the rise of research field such as anti-electromagnetic interference, stealth technique, microwave dark room, the research of microwave absorbing material more and more receives people's attention.Because very marvellous galvanomagnetic effect can appear in ultra material, can be used for fields such as absorbing material and stealth material, becomes the focus of absorbing material area research.The character of ultra material and function mainly come from its inner structure, how to prepare the key that the three-dimensional fine structure with periodic arrangement becomes ultra material preparation technology.
CMOS (Complementary Metal Oxide Semiconductor, CMOS) technology is to realize the technology of controlled minimum dimension in the current semiconductor technology, and the technology of 32nm is ripe gradually now, and the technology of smaller szie is developed.Therefore, effectively utilize the size Control means in the CMOS technology, can make the micro-structural of very small dimensions, utilize the special micro-structural of materials with different properties just can produce the ultra material that is used for special nature.Semiconductor is to use a kind of very widely material in the CMOS technology, but does not also have the ultra material preparation technology of based semiconductor in the prior art.
[summary of the invention]
Technical problem to be solved by this invention provides a kind of ultra material preparation method of based semiconductor and the ultra material of based semiconductor, can access the ultra material that the electromagnetic parameter controllability is higher, also more adhere to specification.
For solving the problems of the technologies described above, one embodiment of the invention provides a kind of ultra material preparation method of based semiconductor, and this method comprises:
On substrate, form semiconductor layer;
On said semiconductor layer, apply one deck photoresist;
Template to have preset micro structure array is carried out photoetching as mask plate to said photoresist;
According to preset electromagnetic parameter, in semiconductor layer, mix impurity;
Removal is coated in the photoresist on the said semiconductor layer, obtains ultra material.
Another embodiment of the present invention also provides a kind of ultra material that adopts the based semiconductor of technique scheme preparation.
Technique scheme is through forming semiconductor layer on substrate; Photoresist to have micro-structural mixes in semiconductor layer as mask; Can change the electromagnetic parameter of ultra material owing in semiconductor, mix; Therefore in semiconductor layer, mix impurity according to preset electromagnetic parameter, can obtain required ultra material, controllability is high.
[description of drawings]
In order to be illustrated more clearly in the technical scheme in the embodiment of the invention; The accompanying drawing of required use is done to introduce simply in will describing embodiment below; Obviously, the accompanying drawing in describing below only is some embodiments of the present invention, for those of ordinary skills; Under the prerequisite of not paying creative work property, can also obtain other accompanying drawing according to these accompanying drawings.
Fig. 1 is the ultra material preparation method flow chart of a kind of based semiconductor of providing of the embodiment of the invention one;
Fig. 2 is the ultra material preparation method flow chart of a kind of based semiconductor of providing of the embodiment of the invention two;
Fig. 3 is the ultra material preparation method flow chart of a kind of based semiconductor of providing of the embodiment of the invention three;
Fig. 4 is the ultra material preparation method flow chart of a kind of based semiconductor of providing of the embodiment of the invention four;
Fig. 5 is the metamaterial structure sketch map of a kind of based semiconductor of providing of the embodiment of the invention five;
Fig. 6 is the metamaterial structure sketch map of a kind of based semiconductor of providing of the embodiment of the invention six.
[embodiment]
To combine the accompanying drawing in the embodiment of the invention below, the technical scheme in the embodiment of the invention is carried out clear, intactly description, obviously, described embodiment only is the present invention's part embodiment, rather than whole embodiment.Based on the embodiment among the present invention, those of ordinary skills are not making all other embodiment that obtained under the creative work prerequisite, all belong to the scope of the present invention's protection.
Embodiment one,
Referring to Fig. 1, be the ultra material preparation method flow chart that the present invention implements a kind of based semiconductor that provides, this preparation method comprises the steps:
S11: on substrate, form semiconductor layer.
Wherein, substrate is an insulating material, can be made by pottery, macromolecular material, ferroelectric material, ferrite material or ferromagnetic material; Semiconductor layer can be silicon (si) layer, germanium (ge) layer or GaAs (gaas) layer etc.
S12: on semiconductor layer, apply one deck photoresist.
Wherein, the photoresist that on semiconductor layer, applies can be positive photoresist or negative photoresist.
S13: the template to have preset micro structure array is carried out photoetching as mask plate to photoresist.
For example, as mask plate, photoresist is carried out photoetching, finally on photoresist, form the figure of " worker " font array with masterplate with " worker " font array.
S14:, in semiconductor layer, mix impurity according to preset electromagnetic parameter.
Concrete, as mask, adopt the CMOS diffusion technology in semiconductor, to mix P type or N type impurity with photoresist with micro-structural.
S15: remove and be coated in the photoresist on the semiconductor layer, obtain ultra material.
In concrete implementation process, positive photoresist can adopt acetone, and negative photoresist cleans with corresponding cleaning liquid.
In the present embodiment; Through on substrate, forming semiconductor layer, on semiconductor layer, form preset micro structure array then, in semiconductor layer, mix as mask with photoresist with micro structure array; Can change the electromagnetic parameter of ultra material owing in semiconductor, mix; Therefore in semiconductor layer, mix impurity according to preset electromagnetic parameter, can obtain required ultra material, controllability is high.
Embodiment two,
Referring to Fig. 2, the ultra material preparation method flow chart of a kind of based semiconductor that provides for the embodiment of the invention two, this preparation method comprises the steps:
S21: on substrate, form semiconductor layer.
Wherein, substrate is an insulating material, can be made by pottery, macromolecular material, ferroelectric material, ferrite material or ferromagnetic material; Semiconductor layer can be silicon layer, germanium layer or gallium arsenide layer etc.
S22: on semiconductor layer, apply one deck photoresist.
Wherein, the photoresist that on semiconductor layer, applies can be positive photoresist or negative photoresist.
S23: the template to have preset micro structure array is carried out photoetching as mask plate to photoresist.
For example; With masterplate with font array as mask plate; Photoresist is carried out photoetching, finally on photoresist, form the figure of
Figure BDA0000065539060000052
font array.
S24: with the figure transfer that forms after the photoetching on the photoresist to semiconductor layer.
Concrete, the method for employing wet etching is etching the figure that forms after the photoetching on the photoresist on the semiconductor layer; Perhaps, adopt the method for dry etching, etching the figure that forms after the photoetching on the photoresist on the semiconductor layer.
S25:, adopt thermal diffusion technology in semiconductor layer, to mix impurity according to preset electromagnetic parameter.
Concrete; 1) for alms giver or acceptor impurity atom: because the radius of alms giver or acceptor impurity atom is generally all bigger; These foreign atoms will directly get into and go in the gap of semiconductor lattice is difficulty very; Have only after having lattice vacancy in the semiconductor crystal, foreign atom just might enter to occupy these rooms, thereby is diffused in the crystal.To produce a large amount of lattice vacancies in order letting in the crystal, just must to heat, let the warm-up movement aggravation of crystal atoms,, stay the room so that some atom obtains sufficiently high energy and leaves lattice position to crystal.2) for the beavy metal impurity atom: the atomic radius of beavy metal impurity is very little, goes even also can be diffused in the semiconductor through interstitial void at an easy rate at a lower temperature, so the temperature of diffusion is generally lower.
After mixing impurity, can change semi-conductive electromagnetic parameter, in embodiments of the present invention, the concentration of mixing impurity is provided with according to required electromagnetic parameter.
S26: remove and be coated in the photoresist on the semiconductor layer, obtain ultra material.
In concrete implementation process, positive photoresist can adopt acetone, and negative photoresist cleans with corresponding cleaning liquid.
In the present embodiment; Through on substrate, forming semiconductor layer; Adopt the mode of photoetching on semiconductor layer, to form micro-structural, can change the electromagnetic parameter of ultra material, therefore adopt thermal diffusion technology in semiconductor layer, to mix impurity owing in semiconductor, mix; Can obtain required ultra material, controllability is high.
Embodiment three,
Referring to Fig. 3, the ultra material preparation method flow chart of a kind of based semiconductor that provides for the embodiment of the invention three, this preparation method comprises the steps:
S31: on substrate, form semiconductor layer.
Wherein, substrate is an insulating material, can be made by pottery, macromolecular material, ferroelectric material, ferrite material or ferromagnetic material; Semiconductor layer can be silicon layer, germanium layer or gallium arsenide layer etc.
S32: on semiconductor layer, apply one deck photoresist.
Wherein, the photoresist that on semiconductor layer, applies can be positive photoresist or negative photoresist.
S33: the template to have preset micro structure array is carried out photoetching as mask plate to photoresist.
For example, as mask plate, photoresist is carried out photoetching, finally on photoresist, form the figure of " ten " font array with masterplate with " ten " font array.
S34: with the figure transfer that forms after the photoetching on the photoresist to semiconductor layer.
Concrete, the method for employing wet etching is etching the figure that forms after the photoetching on the photoresist on the semiconductor layer; Perhaps, adopt the method for dry etching, etching the figure that forms after the photoetching on the photoresist on the semiconductor layer.
S35:, adopt ion implantation technique in said semiconductor layer, to mix impurity according to preset electromagnetic parameter.
Concrete; Go in order to make alms giver or acceptor impurity atom can enter into semiconductor crystal, need foreign atom be ionized into ion, and quicken, let these ions obtain very high kinetic energy with highfield; And then direct bombarding semiconductor crystal, thereby be injected in the semiconductor crystal.After mixing impurity, can change semi-conductive electromagnetic parameter, in embodiments of the present invention, the concentration of mixing impurity is provided with according to required electromagnetic parameter.
S36: remove and be coated in the photoresist on the semiconductor layer, obtain ultra material.
In concrete implementation process, positive photoresist can adopt acetone, and negative photoresist cleans with corresponding cleaning liquid.
In the present embodiment; Through on substrate, forming semiconductor layer; Adopt the mode of photoetching on semiconductor layer, to form micro-structural, can change the electromagnetic parameter of ultra material, therefore adopt ion implantation technique in semiconductor layer, to mix impurity owing in semiconductor, mix; Can obtain required ultra material, controllability is high.
Embodiment four,
Referring to Fig. 4, the ultra material preparation method flow chart of a kind of based semiconductor that provides for the embodiment of the invention four, this preparation method comprises the steps:
S41: on substrate, form semiconductor layer.
Wherein, substrate is an insulating material, can be made by pottery, macromolecular material, ferroelectric material, ferrite material or ferromagnetic material; Semiconductor layer can be silicon layer, germanium layer or gallium arsenide layer etc.
S42: on semiconductor layer, apply one deck photoresist.
Wherein, the photoresist that on semiconductor layer, applies can be positive photoresist or negative photoresist.
S43: the template to have preset micro structure array is carried out photoetching as mask plate to photoresist.
For example, as mask plate, photoresist is carried out photoetching, finally on photoresist, form the figure of " ten " font array with masterplate with " ten " font array.
S44: with the figure transfer that forms after the photoetching on the photoresist to semiconductor layer.
Concrete, the method for employing wet etching is etching the figure that forms after the photoetching on the photoresist on the semiconductor layer; Perhaps, adopt the method for dry etching, etching the figure that forms after the photoetching on the photoresist on the semiconductor layer.
S45:, adopt ion implantation technique in semiconductor layer, to mix impurity according to preset electromagnetic parameter.
Concrete; Go in order to make alms giver or acceptor impurity atom can enter into semiconductor crystal, need foreign atom be ionized into ion, and quicken, let these ions obtain very high kinetic energy with highfield; And then direct bombarding semiconductor crystal, thereby be injected in the semiconductor crystal.After mixing impurity, can change semi-conductive electromagnetic parameter, in embodiments of the present invention, the concentration of mixing impurity is provided with according to required electromagnetic parameter.
S46: remove and be coated in the photoresist on the semiconductor layer.
In concrete implementation process, positive photoresist can adopt acetone, and negative photoresist cleans with corresponding cleaning liquid.
S47: the semiconductor layer to mixing impurity carries out annealing in process, obtains ultra material.
Concrete, alms giver or acceptor impurity atom are wanted charge carrier can be provided, and just must be on the position of alternative semiconductors atom, valence electron unnecessary or that lack are so just arranged to produce charge carrier.So in semiconductor, even mixed alms giver or acceptor impurity, if but these foreign atoms do not enter into alternative site, and they will not have the effect that charge carrier is provided yet so.Therefore, also need carry out the annealing in process step: elevated temperature make the semiconductor atom bonding in foreign atom and the lattice, thereby the activator impurity atom changes semi-conductive electromagnetic parameter, for example conductivity.
Present embodiment has carried out annealing in process with respect to embodiment three after in semiconductor, mixing, the lattice defect that has produced when having eliminated semiconductor doping, and activated and mixed semi-conductive foreign atom, further change semi-conductive electromagnetic parameter.
The foregoing description has been described the ultra material preparation method of based semiconductor, and the present invention also comprises the ultra material of the based semiconductor that adopts above-mentioned execution mode preparation.
Embodiment five,
Referring to Fig. 5, be the metamaterial structure sketch map of a kind of based semiconductor of providing of the embodiment of the invention five, this ultra material comprises:
Substrate 51; And be positioned at the semiconductor layer 52 on the substrate 51.
Wherein, semiconductor layer 52 comprises doped portion 53 and doped portion 54 not; Doped portion 53 has conductivity.
Wherein, substrate is an insulating material, can be made by pottery, macromolecular material, ferroelectric material, ferrite material or ferromagnetic material.
Concrete preparation process can repeat no more referring to embodiment one here.
Embodiment six,
Referring to Fig. 6, be the metamaterial structure sketch map of a kind of based semiconductor of providing of the embodiment of the invention six, this ultra material comprises:
Substrate 61; And be positioned at the semiconductor layer 62 that has micro structure array on the substrate 61.
Wherein, semiconductor layer 62 comprises doped portion 63 and doped portion 64 not; Doped portion 64 has conductivity.
Wherein, substrate is an insulating material, can be made by pottery, macromolecular material, ferroelectric material, ferrite material or ferromagnetic material.
Concrete preparation process can repeat no more referring to embodiment two to embodiment four here.
More than the embodiment of the invention has been carried out detailed introduction, used concrete example among this paper principle of the present invention and execution mode set forth, the explanation of above embodiment just is used for helping to understand method of the present invention and core concept thereof; Simultaneously, for one of ordinary skill in the art, according to thought of the present invention, the part that on embodiment and range of application, all can change, in sum, this description should not be construed as limitation of the present invention.

Claims (10)

1. the ultra material preparation method of a based semiconductor is characterized in that, said method comprises:
On substrate, form semiconductor layer;
On said semiconductor layer, apply one deck photoresist;
Template to have preset micro structure array is carried out photoetching as mask plate to said photoresist;
According to preset electromagnetic parameter, in semiconductor layer, mix impurity;
Removal is coated in the photoresist on the said semiconductor layer, obtains ultra material.
2. method according to claim 1 is characterized in that, on substrate, forms semiconductor layer, specifically comprises:
Vapor deposition layer of semiconductor on substrate; Perhaps,
On substrate with adhesive pressing layer of semiconductor.
3. method according to claim 1 is characterized in that, according to preset electromagnetic parameter, in semiconductor layer, mixes before the impurity, also comprises:
With the figure transfer that forms after the photoetching on the photoresist to said semiconductor layer.
4. method according to claim 3 is characterized in that, the figure transfer that forms after the photoetching on the photoresist to said semiconductor layer, is specifically comprised:
Adopt the method for wet etching, on said semiconductor layer, etch the figure that forms after the photoetching on the photoresist.
5. method according to claim 3 is characterized in that, the figure transfer that forms after the photoetching on the photoresist to said semiconductor layer, is specifically comprised:
Adopt the method for dry etching, on said semiconductor layer, etch the figure that forms after the photoetching on the photoresist.
6. method according to claim 1 is characterized in that, according to preset electromagnetic parameter, in having the semiconductor layer of micro-structural, mixes impurity, specifically comprises:
According to preset electromagnetic parameter, adopt thermal diffusion technology in said semiconductor layer, to mix impurity.
7. method according to claim 1 is characterized in that, according to preset electromagnetic parameter, in having the semiconductor layer of micro-structural, mixes impurity, specifically comprises:
According to preset electromagnetic parameter, adopt ion implantation technique in said semiconductor layer, to mix impurity.
8. method according to claim 7 is characterized in that, said removal is coated in after the photoresist on the said semiconductor layer, also comprises:
Semiconductor layer to mixing impurity carries out annealing in process.
9. method according to claim 1 is characterized in that, said substrate is an insulating material; Said semiconductor layer is silicon layer, germanium layer or gallium arsenide layer.
10. the ultra material of a based semiconductor is characterized in that, comprises the ultra material of any described method preparation of claim 1 to 9.
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110133761A (en) * 2019-05-20 2019-08-16 湖南理工学院 A kind of Meta Materials reflectance coating and preparation method thereof

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1505842A (en) * 2001-05-02 2004-06-16 Ħ��������˾ An opto-coupling device structure and method therefor
CN1324710C (en) * 2002-07-03 2007-07-04 旺宏电子股份有限公司 Embedded bit line structure and mfg. method thereof
WO2008121159A2 (en) * 2006-10-19 2008-10-09 Los Alamos National Security Llc Active terahertz metamaterial devices
CN100524661C (en) * 2006-02-16 2009-08-05 南亚科技股份有限公司 Semiconductor device with slot type grid and producing method thereof
US20100124160A1 (en) * 2008-11-19 2010-05-20 Kabushiki Kaisha Toshiba Optical recording system to record information with light

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1505842A (en) * 2001-05-02 2004-06-16 Ħ��������˾ An opto-coupling device structure and method therefor
CN1324710C (en) * 2002-07-03 2007-07-04 旺宏电子股份有限公司 Embedded bit line structure and mfg. method thereof
CN100524661C (en) * 2006-02-16 2009-08-05 南亚科技股份有限公司 Semiconductor device with slot type grid and producing method thereof
WO2008121159A2 (en) * 2006-10-19 2008-10-09 Los Alamos National Security Llc Active terahertz metamaterial devices
US20100124160A1 (en) * 2008-11-19 2010-05-20 Kabushiki Kaisha Toshiba Optical recording system to record information with light

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110133761A (en) * 2019-05-20 2019-08-16 湖南理工学院 A kind of Meta Materials reflectance coating and preparation method thereof

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