CN102780472B - FPGA is utilized to realize the method for the brand-new lock-out pulse measurement of vector network analyzer - Google Patents
FPGA is utilized to realize the method for the brand-new lock-out pulse measurement of vector network analyzer Download PDFInfo
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- CN102780472B CN102780472B CN201210230887.4A CN201210230887A CN102780472B CN 102780472 B CN102780472 B CN 102780472B CN 201210230887 A CN201210230887 A CN 201210230887A CN 102780472 B CN102780472 B CN 102780472B
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Abstract
The invention belongs to technical field of measurement and test, it is a kind of data processor utilizing fpga chip to control vector network analyzer, thus analyzer data acquisition moment and external pulse signal or inner synchronousing signal are synchronously got up, reach a kind of method of data processing and pulses generation Complete Synchronization under pulse condition.The present invention utilizes the programmable features of programmable logic array, under the triggering of same clock, arrange according to user, detect the pulse synchronous signal of designated port input or the synchronizing signal of detection system inside generation, when synchronizing signal is effective, unbalanced pulse exports and data processor, thus the data acquisition ensureing vector network analyzer is the moment of specifying user, reaches a kind of method of the synchro measure under pulse condition.
Description
Technical field
The invention belongs to technical field of measurement and test, relate to a kind of method that FPGA of utilization realizes the brand-new lock-out pulse measurement of vector network analyzer.
Background technology
Traditional Pulse vector network analyzer only provides lock-out pulse metering system, it utilizes the counter of the ADC transducer of internal system to produce inner synchronousing signal, cannot the synchronizing signal of external user input, only can ensure that data processing is modulated synchronous with clock.The program capability utilizing fpga chip of novelty of the present invention, write synchronous source to judge and detection module, synchronously trigger impulse generation module, pulse generating module and data acquisition module, base when these modules adopt same height steady, ensure the correlation of the signal that several module produces, thus the Complete Synchronization of data acquisition under achieving pulse condition and pulse signal, meet the signal that user specifies according to oneself and carry out the moment that synchronous vector network analyzer exports clock signal, the instrument of control analysis simultaneously gathers the requirement that user specifies the spectrum information in moment.
Traditional Pulse vector network analyzer, fixing synchronous triggering signal can only be produced according to internal system mechanism, this synchronizing signal only can ensure the Wideband synchronization measurement function realizing pulse, neither allow to utilize external signal synchronous, can not be independently set by user the synchronous data collection moment.The present invention then utilizes the programmable features of fpga chip, make pulse network analyzer both independently can produce pulse synchronous signal, the synchronizing signal of user's input can also be detected, user's control and analysis instrument data sampling and processing Complete Synchronization is got up, when height is steady in base resolution, synchronizing relay, sampling instant etc. can be set flexibly.
Summary of the invention
The present invention is directed to above-mentioned technical problem provides a kind of FPGA of utilization to realize the method for the brand-new lock-out pulse measurement of vector network analyzer.
For solving the problems of the technologies described above, the technical scheme that the present invention adopts is: provide a kind of FPGA of utilization to realize the method for the brand-new lock-out pulse measurement of vector network analyzer, a synchronously source judgement and detection module is utilized to analyze synchronizing signal source, if external sync mode, the state of designated port is then detected according to the polar requirement of user input signal, when detecting that signal input polarity requires consistent with user, then produce a synchronous enabled signal; If it is enabled state that internal synchronization mode then arranges synchronous enabled signal, synchronous enabled signal finally sends into synchronous trigger impulse generation module; During internal synchronization mode, the pulse repetition period that synchronous trigger impulse generation module is arranged according to user, produce the synchronization pulse that a pulsewidth is 1 clock; During external sync mode, the pulsewidth of synchronous start pulse signal that system exports is the maximum that in the system pulse 1 ~ N that will produce, time delay adds pulsewidth, if edging trigger mode, the cycle of start pulse signal is consistent with the external synchronization signal cycle; If level triggering mode, after having exported a string start pulse signal, if synchronizing signal maintains effectively, then continue to export lower a string trigger impulse; The triggering signal that last synchronous trigger impulse generation module produces enters pulse generating module and data acquisition module, pulse generating module produces the N road pulse signal of specifying, described N is not more than 4, time delay, the width of pulse signal are specified by user, cycle is then equal with the cycle of synchronous start pulse signal, and pulse output time is the rising edge of trigger impulse; Whether data acquisition module can be arranged synchronous with synchronous start pulse signal by user, time synchronous, after receiving lock-out pulse triggering signal, after the time that time delay is specified, start digital filter program, if the data sampling asynchronous moment by Pulse vector network analyzer from master control.
Described edging trigger mode is rising edge or trailing edge, and described level triggering mode is high level or low level.
The invention has the beneficial effects as follows:
The invention provides inside, outside two kinds of synchronous triggering modes; Time delay and sampling instant can be arranged flexibly; multiple triggering mode (edging trigger, level triggers) is supported outward time synchronously; control impuls time of origin that can be convenient when making user utilize Pulse vector network analyzer to measure and data acquisition time; ensure the controllability of analyser output signal, thus protection unit under test.
Accompanying drawing explanation
Fig. 1 is principle of the invention figure;
Fig. 2: each signal relation figure during the inner method of synchronization;
Each signal relation figure when Fig. 3 is external sync mode.
Embodiment
Below preferred embodiment of the present invention is described in detail, can be easier to make advantages and features of the invention be readily appreciated by one skilled in the art, thus more explicit defining is made to protection scope of the present invention.
The embodiment of the present invention comprises:
First a synchronously source judgement and detection module is utilized to analyze synchronizing signal source, if external sync mode, then detect the state of designated port according to the polar requirement of user input signal, when detecting that signal input polarity requires consistent with user, then produce a synchronous enabled signal; If it is enabled state that internal synchronization mode then arranges synchronous enabled signal, synchronous enabled signal finally sends into synchronous trigger impulse generation module.During internal synchronization mode, the pulse repetition period that synchronous trigger impulse generation module is arranged according to user, produce the synchronization pulse that a pulsewidth is 1 clock; During external sync mode, the pulsewidth of synchronous start pulse signal that system exports is the maximum that in the system pulse 1 ~ N that will produce, time delay adds pulsewidth, if edging trigger mode (rising edge, trailing edge), the cycle of start pulse signal is consistent with the external synchronization signal cycle; If level triggering mode (high level, low level), after having exported a string start pulse signal, if synchronizing signal maintains effectively, then continue to export lower a string trigger impulse.The triggering signal that last synchronous trigger impulse generation module produces enters pulse generating module and data acquisition module, pulse generating module produces the N road pulse signal (N is not more than 4) of specifying, time delay, the width of pulse signal are specified by user, cycle is then equal with the cycle of synchronous start pulse signal, and pulse output time is the rising edge of trigger impulse; Whether data acquisition module can be arranged synchronous with synchronous start pulse signal by user, time synchronous, after receiving lock-out pulse triggering signal, after the time that time delay is specified, start digital filter program, if the data sampling asynchronous moment by Pulse vector network analyzer from master control.
Here is each signal relation schematic diagram under two kinds of synchronous modes, and wherein D1 and Dn represents pulse delay, the pulse output signals of not going the same way, and time delay and width can be arranged respectively, and the cycle then must be consistent.
Can find out in Fig. 2, during the inner method of synchronization, synchronous start pulse signal is produced automatically by system, and its cycle equals the cycle that user is arranged, and note time delay and the width of every road signal and can not be greater than the pulse period.Illustrate in upper figure be data acquisition module synchronous with inter-sync signal time state, now sample time delay be set by the user, if data acquisition module does not adopt the method for synchronization, so sampling instant is independently determined by analyzer.Base when whole signals in addition in Fig. 2 are all steady based on the same height in Fig. 1, that is the resolution of signal is all consistent, and the benefit done like this is the completely relevant and stringent synchronization that can ensure between each signal.
Each signal relation schematic diagram that lower Fig. 3 is synchronisation source when being external sync mode, suppose the time delay on pulse n road and pulsewidth and maximum in figure, the width of start pulse signal equals this maximum; The cycle of each road signal is identical with the cycle of external synchronization signal.Outer synchronous triggering mode is rising edge synch mode.In figure, the resolution of whole signal is the same with Fig. 2 when being also steady based on the same height in Fig. 1 base.
The foregoing is only embodiments of the invention; not thereby the scope of the claims of the present invention is limited; every utilize description of the present invention to do equivalent structure or equivalent flow process conversion; or be directly or indirectly used in other relevant technical fields, be all in like manner included in scope of patent protection of the present invention.
Claims (2)
1. the method utilizing FPGA to realize the brand-new lock-out pulse measurement of vector network analyzer, it is characterized in that, a synchronously source judgement and detection module is utilized to analyze synchronizing signal source, if external sync mode, the state of designated port is then detected according to the polar requirement of user input signal, when detecting that signal input polarity requires consistent with user, then produce a synchronous enabled signal; If it is enabled state that internal synchronization mode then arranges synchronous enabled signal, synchronous enabled signal finally sends into synchronous trigger impulse generation module; During internal synchronization mode, the pulse repetition period that synchronous trigger impulse generation module is arranged according to user, produce the synchronous start pulse signal that a pulsewidth is 1 clock; During external sync mode, the pulsewidth of synchronous start pulse signal that system exports is the maximum that in the system pulse 1 ~ N that will produce, time delay adds pulsewidth, if edging trigger mode, the cycle of synchronous start pulse signal is consistent with the external synchronization signal cycle; If level triggering mode, after having exported a string synchronous start pulse signal, if synchronizing signal maintains effectively, then continue to export lower a string trigger impulse; The triggering signal that last synchronous trigger impulse generation module produces enters pulse generating module and data acquisition module, pulse generating module produces the N road pulse signal of specifying, described N is not more than 4, time delay, the width of pulse signal are specified by user, cycle is then equal with the cycle of synchronous start pulse signal, and pulse output time is the rising edge of trigger impulse; Whether data acquisition module can be arranged synchronous with synchronous start pulse signal by user, time synchronous, after receiving lock-out pulse triggering signal, after the time that time delay is specified, start digital filter program, if asynchronous, sampling instant by Pulse vector network analyzer from master control.
2. the method for claim 1, described edging trigger mode is rising edge or trailing edge, and described level triggering mode is high level or low level.
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| CN103592637B (en) * | 2013-11-07 | 2015-07-15 | 中国电子科技集团公司第四十一研究所 | Method and device for testing digital array module transmitting channel phase congruency |
| CN106771651B (en) * | 2016-11-15 | 2019-07-05 | 中国电子科技集团公司第四十一研究所 | The synchronous method of data acquisition in a kind of pulse network analyzer pulse |
| CN117348949B (en) * | 2023-12-05 | 2024-03-12 | 成都玖锦科技有限公司 | Multi-channel measurement method and system based on vector network analyzer |
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