CN102768988B - Method for effectively judging blocking capability of copper diffusion blocking layer - Google Patents
Method for effectively judging blocking capability of copper diffusion blocking layer Download PDFInfo
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- CN102768988B CN102768988B CN201210259216.0A CN201210259216A CN102768988B CN 102768988 B CN102768988 B CN 102768988B CN 201210259216 A CN201210259216 A CN 201210259216A CN 102768988 B CN102768988 B CN 102768988B
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Abstract
The invention provides a method for effectively judging blocking capability of a copper diffusion blocking layer. The method comprises the following steps: forming a groove structure required by a contact hole and a metal layer on a medium layer of a semiconductor device; depositing a blocking layer and depositing copper in the groove structure to form a metal-oxide half field effect transistor; and step 6, measuring whether the electric properties of the device meets the predetermined standards, if so, judging that the blocking layer has blocking capability; and if not, re-performing the steps 4 to 6. Compared with the existing method, with the adoption of the method, the blocking capability of the copper diffusion blocking layer can be more effectively monitored, judged and evaluated, and the quality and thickness of the diffusion blocking layer can be accurately and effectively evaluated, so that accurate data for equal proportion reduction of a Cu process can be provided.
Description
Technical field
The present invention relates to a kind of method of judging barrier layer blocking capability, relate in particular to a kind of method of effective judgement copper diffusion barrier layer blocking capability.
Background technology
The level of energy of metal impurities copper in silicon in silicon generally, away from the bottom of conduction band or top of valence band, is therefore called as deep-level impurity.It spreads soon in silicon, and plays complex centre effect, has a strong impact on minority carrier life time.And itself can produce defect, and easy and defect complexing, the performance of deterioration materials and devices.In conventional process monitoring, the diffusion property of Cu interconnect architecture cannot be accomplished to monitor effectively intuitively, can only confirm that the method for the filling coverage rate on barrier layer carries out by section.Even at the initial stage of exploitation, also can only the distribution in medium be used as benchmark by secondary electron collection of illustrative plates (SIMS) measurement Cu for the monitoring of the diffusion property of Cu.Also have in document and adopt mos capacitance structure to study, but the method need to be made new device architecture.And because copper is more limited by the amount of the diffusion of diffusion impervious layer, and this is not one method intuitively.Cause thus the thickness of diffusion impervious layer in process exploitation owing to cannot obtain first hand barrier properties information, and the diffusion barrier property of the thickening of selecting safety to ensure that it is good.Cause thus making its thickness other techniques of cannot following in the scaled down process of technique to be dwindled according to same ratio.
From diffusion impervious layer monitoring specification and the actual monitored result of current industry main flow, can see, in industry, the main material of tungsten as contact hole that adopt in traditional technique, still uses the mode of this physical pattern of stratum's coverage rate (step coverage) to carry out for the monitoring of diffusion impervious layer.
Therefore, those skilled in the art be devoted to develop a kind of more intuitively, effectively judge more accurately the method for copper diffusion barrier layer blocking capability.
Summary of the invention
In view of above-mentioned the problems of the prior art, technical problem to be solved by this invention is existing.
The method of a kind of effective judgement copper diffusion barrier layer blocking capability provided by the invention, comprises the following steps:
Step 1 forms silicide on semiconductor device;
Step 2 forms dielectric layer on semiconductor device and silicide;
Step 3 forms the required groove structure of contact hole and metal level on dielectric layer;
Step 4, precipitation barrier layer cement copper in groove structure;
Step 5, by grinding moulding contact hole and metal level level, forms metal-oxide half field effect transistor;
Whether step 6, meet preassigned by the electrology characteristic of measuring element, and in this way, barrier layer has blocking capability; As no, barrier layer does not have blocking capability.
In a preferred embodiments of the present invention, in described step 1, form silicide by sputter.
In another preferred embodiments of the present invention, in described step 2, form dielectric layer by chemical deposition.
In another preferred embodiments of the present invention, in described step 3, form required groove structure by Damascus method.
In another preferred embodiments of the present invention, in described step 4, adopt electroless plating method cement copper.
In another preferred embodiments of the present invention, in described step 5, pass through chemistry or mechanical lapping moulding contact hole and metal level.
In another preferred embodiments of the present invention, the electrology characteristic in described step 6 comprises the electrology characteristic numerical value of device node.
In another preferred embodiments of the present invention, the electrology characteristic numerical value of described node comprises HCl, VTS, NBTI.
In another preferred embodiments of the present invention, the electrology characteristic in described step 6 comprises device capacitor numerical value.
In another preferred embodiments of the present invention, described device capacitor numerical value comprises CV, GOI, TDDB.
Method of the present invention is more effectively monitored and assesses than existing method.And can accurately effectively assess the quality of diffusion impervious layer and thickness, thereby provide data accurately for the scaled down of Cu technique.
Brief description of the drawings
Fig. 1 is the schematic diagram that embodiments of the invention form silicide;
Fig. 2 is the schematic diagram that embodiments of the invention form dielectric layer;
Fig. 3 is the schematic diagram that embodiments of the invention form groove structure;
Fig. 4 is the schematic diagram that embodiments of the invention form precipitation;
Fig. 5 is the schematic diagram after embodiments of the invention grind;
Fig. 6 is the schematic flow sheet of embodiments of the invention;
Fig. 7 a measures the MOSFET schematic diagram that embodiments of the invention are measured;
Fig. 7 b is the cutaway view of Fig. 7 a;
Fig. 8 a is the schematic diagram of measuring the knot of embodiments of the invention measurement;
Fig. 8 b is the cutaway view of Fig. 8 a;
Fig. 8 c is the schematic diagram of measuring another knot of embodiments of the invention measurement;
Fig. 8 d is the cutaway view of Fig. 8 c;
Fig. 8 e is the schematic diagram of measuring another knot of embodiments of the invention measurement;
Fig. 8 f is the cutaway view of Fig. 8 e;
Fig. 9 a measures the device schematic diagram that embodiments of the invention are measured;
Fig. 9 b is the cutaway view of Fig. 9 a;
Fig. 9 c measures another device schematic diagram that embodiments of the invention are measured;
Fig. 9 d is the cutaway view of Fig. 9 c;
Fig. 9 e measures another device schematic diagram that embodiments of the invention are measured;
Fig. 9 f is the cutaway view of Fig. 9 e;
Fig. 9 g measures another device schematic diagram that embodiments of the invention are measured;
Fig. 9 h is the cutaway view of Fig. 9 g.
Embodiment
Below with reference to accompanying drawing, the present invention is done to concrete explaination.The method of a kind of effective judgement copper diffusion barrier layer blocking capability of embodiments of the invention, comprises the following steps:
Step 1 as shown in fig. 1, forms silicide 2 on semiconductor device 1; Step 2 as shown in Figure 2, forms dielectric layer 3 on semiconductor device and silicide; Step 3 as shown in Figure 3, forms the required groove structure 4 of contact hole 41 and metal level 42 on dielectric layer 3;
Step 4, as shown in Figure 4, precipitation barrier layer 5 cement copper in groove structure 4;
Step 5, as shown in Figure 5, by grinding moulding contact hole and metal level level, forms metal-oxide half field effect transistor MOSFET.
Whether step 6, meet preassigned by the electrology characteristic of measuring element, and in this way, barrier layer has blocking capability; As no, barrier layer does not have blocking capability.
The blocking capability characteristic on the barrier layer described in the present invention is as long as be material behavior and the thickness on barrier layer.The present invention both can be used for the daily monitoring for diffusion barrier material, can be used for again the characteristic in scaled down process for new material or current material and assessed inspection.
When material is assessed, the flow chart of embodiments of the invention as shown in Figure 6, wherein, in the time meeting reliability testing standard by the electrology characteristic of measuring element, material evaluation completes.In the time not meeting reliability testing standard by the electrology characteristic of measuring element, re-start step 4 to 6, until while meeting reliability testing standard, material evaluation completes.
The present invention is by one-shot forming contact hole and metal level level, and to utilize Cu be the characteristic of the deep energy level of Si semiconductor, coordinate conventional grid oxygen and device reliability structure, the electrology characteristic by MOS device and reliability measure and further monitor the blocking capability on barrier layer for the extreme sensitivity of Cu deep energy level.This patent a kind of for monitoring and assess the method for process for copper diffusion impervious layer diffusion barrier property, more effectively monitors and assesses than existing method.And can accurately effectively assess the quality of diffusion impervious layer and thickness, thereby provide data accurately for the scaled down of Cu technique.
In an embodiment of the present invention, in step 1, can form silicide by sputter.In step 2, can form dielectric layer by chemical deposition.
In addition,, in the experimental technique of the effective monitoring copper diffusion barrier layer blocking capability of embodiments of the invention, in step 3, can form required groove structure by Damascus method.
Meanwhile, preferably in step 4, adopt electroless plating method to fill cement copper, in step 5, pass through chemistry or mechanical lapping moulding contact hole and metal level.
In addition, in the method for effective judgement copper diffusion barrier layer blocking capability of embodiments of the invention, the electrology characteristic in step 6 mainly comprises following three kinds:
One) be MOSFET, its basic structure is as shown in Fig. 7 a and 7b, wherein 6,7,8,9 active area, P trap, polysilicon, the P+ that are respectively this structure, because Cu is the deep-level impurity in semiconductor medium, so, its existence can cause hot carrier to inject (Hot Carrier Injection, HCl), Negative Bias Temperature Instability effect (negative bias temperature instability, and the generation of the integrity problem such as threshold voltage unsteadiness (Vth stability, VTS) NBTI).Can confirm the existence of Cu impurity in silicon by building these parameters of control, and then confirm the quality of Cu diffusion impervious layer;
Two) the electrology characteristic numerical value that knot (junction) measures.As shown in Fig. 8 a, 8b, 8c, 8d, 8e, 8f, wherein, 10,11,13,12 are respectively active area, P trap, polysilicon, the P+ of this structure, and the electrology characteristic of the node of test comprises leakage current characteristic and the breakdown characteristics of knot.Whether the measurement of the electrology characteristic numerical value by above-mentioned knot, have blocking capability thereby judge barrier layer;
Three) be the measurement of device capacitor characteristic, its basic structure is as Fig. 9 a, 9b, 9c, 9d, 9e, 9f, 9g, 9h, wherein, 14, 15, 16, 17 are respectively the active area of this structure, P trap, polysilicon, P+, this patent is by the intrinsic numeric to device capacitor, for example capacitance voltage curves (Conductance-Voltage, CV), gate oxide integrity (gate oxide integrity, and grid oxygen time breakdown (Tims Dependent Dielectic Breakdown GOI), electricity and the reliability measurement such as TDDB), whether meet preassigned scope, thereby judge barrier layer and whether there is blocking capability, and the size of blocking capability.
Above specific embodiments of the invention be have been described in detail, but it is just as example, the present invention is not restricted to specific embodiment described above.To those skilled in the art, any equivalent modifications that the present invention is carried out and alternative also all among category of the present invention.Therefore, equalization conversion and the amendment done without departing from the spirit and scope of the invention, all should contain within the scope of the invention.
Claims (10)
1. a method of effectively judging copper diffusion barrier layer blocking capability, is characterized in that, comprises the following steps:
Step 1 forms silicide on semiconductor device;
Step 2 forms dielectric layer on semiconductor device and silicide;
Step 3 forms the required groove structure of contact hole and metal level on dielectric layer;
Step 4 precipitates barrier layer and cement copper in groove structure in groove structure;
Step 5, by grinding moulding contact hole and metal level level, forms metal-oxide half field effect transistor;
Whether step 6, meet preassigned by the electrology characteristic of measuring element, and in this way, barrier layer has blocking capability; As no, barrier layer does not have blocking capability, re-starts step 4 to 6, until described device electrology characteristic meets preassigned.
2. the method for effective judgement copper diffusion barrier layer blocking capability as claimed in claim 1, is characterized in that, in described step 1, forms silicide by sputter.
3. the method for effective judgement copper diffusion barrier layer blocking capability as claimed in claim 1, is characterized in that, in described step 2, forms dielectric layer by chemical deposition.
4. the method for effective judgement copper diffusion barrier layer blocking capability as claimed in claim 1, is characterized in that, in described step 3, forms required groove structure by Damascus method.
5. the method for effective judgement copper diffusion barrier layer blocking capability as claimed in claim 1, is characterized in that, adopts electroless plating method cement copper in described step 4.
6. the method for effective judgement copper diffusion barrier layer blocking capability as claimed in claim 1, is characterized in that, passes through chemistry or mechanical lapping moulding contact hole and metal level in described step 5.
7. the method for effective judgement copper diffusion barrier layer blocking capability as claimed in claim 1, is characterized in that, the electrology characteristic in described step 6 comprises the electrology characteristic numerical value of device node.
8. the method for effective judgement copper diffusion barrier layer blocking capability as claimed in claim 7, is characterized in that, the electrology characteristic numerical value of described node comprises HCI, VTS, NBTI.
9. the method for effective judgement copper diffusion barrier layer blocking capability as claimed in claim 1, is characterized in that, the electrology characteristic in described step 6 comprises device capacitor numerical value.
10. the method for effective judgement copper diffusion barrier layer blocking capability as claimed in claim 9, is characterized in that, described device capacitor numerical value comprises CV, GOI, TDDB.
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| CN110676213B (en) * | 2019-09-18 | 2021-12-14 | 天津大学 | Silicon through hole interconnection copper wire barrier layer optimization method aiming at small line width requirement |
| CN111584383A (en) * | 2020-05-14 | 2020-08-25 | 深圳市华星光电半导体显示技术有限公司 | Method for judging blocking capability of copper diffusion blocking layer and structure thereof |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN102132398A (en) * | 2008-03-21 | 2011-07-20 | 哈佛学院院长等 | Self-aligned barrier layers for interconnects |
| CN102142428A (en) * | 2011-03-01 | 2011-08-03 | 复旦大学 | Ruthenium/wolfram hafnium nitride (Ru/WHfN) blocking layer against copper diffusion applied to copper interconnection and preparation method thereof |
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| US7847344B2 (en) * | 2002-07-08 | 2010-12-07 | Micron Technology, Inc. | Memory utilizing oxide-nitride nanolaminates |
| US7393702B2 (en) * | 2004-10-20 | 2008-07-01 | Board Of Regents, The University Of Texas System | Characterizing the integrity of interconnects |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN102132398A (en) * | 2008-03-21 | 2011-07-20 | 哈佛学院院长等 | Self-aligned barrier layers for interconnects |
| CN102142428A (en) * | 2011-03-01 | 2011-08-03 | 复旦大学 | Ruthenium/wolfram hafnium nitride (Ru/WHfN) blocking layer against copper diffusion applied to copper interconnection and preparation method thereof |
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