CN102760102B - Flash memory device and data protection method thereof - Google Patents
Flash memory device and data protection method thereof Download PDFInfo
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- CN102760102B CN102760102B CN201110118864.XA CN201110118864A CN102760102B CN 102760102 B CN102760102 B CN 102760102B CN 201110118864 A CN201110118864 A CN 201110118864A CN 102760102 B CN102760102 B CN 102760102B
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Abstract
The invention provides a data protection method of a flash memory device. In an embodiment, the flash memory device comprises a flash memory to store protected data. The data protection method comprises the following steps: recording a plurality of current read addresses contained in a plurality of read commands transmitted by a host computer to the flash memory device after the flash memory device is coupled to the host computer; comparing the current read addresses with a plurality of preset read addresses; leading the flash memory device to enter a data protection mode when the current read addresses are not in accordance with the preset read addresses; and processing a data access command according to a protective mode set parameter if the flash memory device receives a plurality of data access commands from the host computer when the flash memory device enters a data protection mode so as to prevent the protected data from being accessed by the host computer.
Description
[technical field]
The present invention has about flash memory, relates to the data protection of flash memory especially.
[background technology]
Flash memory devices comprises a flash memory, with thinking a main frame storage data.Common flash memory devices is as Portable disk.Software programs many at present or archives are all to pay and just can obtain, the song that such as needing pays downloads or video archive and the pay games or application program downloaded.When this supervisor or archives are after main frame is downloaded and is stored to flash memory devices, non-paying person can be coupled to other main frame by being changed by flash memory devices, and reaches the object of program or the archives using the need paying stored in flash memory devices to download.In addition, the program stored in flash memory devices or archives even can be downloaded to the storage device of local side by non-paying person, and reach distribution and not pay the effect of archives.These behaviors all can cause the heavy losses of software developer or archives creator.
Therefore, need a kind of flash memory devices, effectively can protect wherein stored data, avoid user via the main frame changing flash memory devices reach usage behavior of not paying, and prevent the behavior of the pirate software of not paying of user.
[summary of the invention]
In view of this, the object of the present invention is to provide a kind of data guard method of flash memory devices, to solve known techniques Problems existing.In an embodiment, a flash memory devices comprises a flash memory for storage one protected data.First, after this flash memory devices is coupled to a main frame, record the multiple current reading address that this main frame comprises to multiple reading orders that this flash memory devices sends.Then, more described current reading address and multiple predetermined reading address.When described current reading address and described predetermined reading mail returned on ground of incorrect address close, this flash memory devices is made to enter a data protection mode.When this flash memory devices enters this data protection mode, if this flash memory devices receives multiple data access order from this main frame, according to a protected mode setup parameter processing said data access command, with prevent this protected data access by this main frame.
The invention provides a kind of flash memory devices.In an embodiment, this flash memory devices comprises a flash memory and a controller.This flash memory stores a protected data, multiple predetermined reading address and a protected mode setup parameter.After this flash memory devices is coupled to a main frame, the multiple current reading address that this this main frame of controller record comprises to multiple reading orders that this flash memory devices sends, more described current reading address and described predetermined reading address.When described current reading address and described predetermined reading mail returned on ground of incorrect address close, this controller makes this flash memory devices enter a data protection mode.When this flash memory devices enters this data protection mode; if this flash memory devices receives multiple data access order from this main frame; this controller according to this protected mode setup parameter processing said data access command, with prevent this protected data access by this main frame.
In order to above and other objects of the present invention, feature and advantage can be become apparent, several preferred embodiment cited below particularly, and coordinate appended diagram, be described in detail below:
[accompanying drawing explanation]
Fig. 1 is the block diagram according to flash memory devices of the present invention;
Fig. 2 is the schematic diagram according to data protection mode parameter of the present invention;
Fig. 3 A is the schematic diagram according to reading address of the present invention record;
Fig. 3 B figure is the schematic diagram according to presumptive address table of the present invention;
Fig. 4 A and Fig. 4 B is the process flow diagram of the data guard method according to flash memory devices of the present invention; And
Fig. 5 is the process flow diagram of the method 500 of the access command that foundation the present invention processing host under data protection mode sends.
[primary clustering symbol description]
102 ~ main frame;
104 ~ flash memory devices;
112 ~ controller;
114 ~ flash memory;
150 ~ memory storage;
152 ~ read address record;
120 ~ protected data;
130 ~ data protection mode parameter value;
140 ~ read address record;
145 ~ presumptive address table.
[embodiment]
Fig. 1 is the block diagram according to flash memory devices 104 of the present invention.Flash memory devices 104 is coupled to a main frame 102, is main frame 102 storage data.In an embodiment, flash memory devices 104 comprises controller 112 and a flash memory 114.A protected data 120 is stored in flash memory 114.In an embodiment, main frame 102 obtains protected data 120 by paying, is then stored in the flash memory 114 of flash memory devices 104 by protected data 120.In an embodiment, main frame 102 comprises a memory storage.When main frame 102 sends reading order to flash memory devices 104, the reading address that sent reading order can comprise by main frame 102 is recorded in memory storage 150 and becomes reading address record 152.Meanwhile, when flash memory devices 104 from host 102 receives reading order, the reading address that received reading order can comprise by controller 112 is recorded to flash memory 114 and becomes reading address record 140.
Except main frame 102, flash memory devices 104 also can be coupled to other main frame, and is other main frame storage data.In order to avoid other main frame to make developer's sustain damage of protected data 120 to the access of protected data 120, whether the main frame that flash memory devices 104 identifiable design couples on it is main frame 102 or other main frame.In a data protection mode, if the main frame being coupled to flash memory devices 104 is main frame 102, then controller 112 allows protected data 120 stored in main frame 102 free access flash memory 114.If be coupled to the main frame non-host 102 of flash memory devices 104 and be other main frame, then controller 112 does not allow protected data 120 stored in other host accessing flash memory 114.
When main frame 102 and flash memory devices 104 couple disconnection after, stores portion in main frame 102 and flash memory 114 separately and reads address and record 152 and 140.Then, flash memory devices 104 is used again, and is coupled to a current main frame.Now, controller 112 must distinguish whether at present main frame is main frame 102, to determine that current main frame could access the protected data 120 stored in flash memory 114.If main frame is main frame 102 at present, then main frame 102 can sequentially send multiple reading order to flash memory devices, and wherein said reading order comprises multiple reading addresses of reading in address record 152 respectively.In an embodiment, the number of described reading order determines according to a reading times parameter.After flash memory devices 104 receives described reading order, the reading address that controller 112 store in multiple reading address that described reading order can be comprised and flash memory 114 is recorded the reading address of recording in 140 and is compared.If main frame sends at present reading order the reading address comprised and the reading address stored in flash memory 114 are recorded the reading address of recording in 140 and be consistent, then controller 112 determines that current main frame is main frame 102.If the reading address stored in the reading address that the reading order that at present main frame sends comprises and flash memory 114 is recorded the reading mail returned on ground of incorrect address recorded in 140 and closed, then controller 112 determines that current main frame is not main frame 102.
When controller 112 determines that current main frame is main frame 102, controller 112 allows the protected data 120 stored in main frame 102 arbitrary access flash memory 114.When controller 112 determines current main frame for main frame 102, controller 112 does not allow the protected data 120 stored in main frame 102 arbitrary access flash memory 114, to reach the object of data protection.In an embodiment; when controller 112 determines that current main frame is not main frame 102; and when being other main frame, if flash memory devices is done 104 and still received multiple data access order from current main frame, then controller 112 is according to a protected mode setup parameter processing said data access command.The processing mode of controller 112 to the described data access order that other main frames send can have multiple pattern.In an embodiment, when controller 112 receives the data access order of other main frame, then the protected data 120 stored in flash memory 114 is deleted by controller 112.In another embodiment, when controller 112 receives the data read command of other main frame, then controller 112 is to other main frame passback mess code (random code).In another embodiment, when controller 112 receives the data access order of other main frame, then controller 112 normally performs the reading order comprised in data access command, but does not perform the write order comprised in data access command.
Because the execution of data protection mode need according to multiple parameter, therefore flash memory devices 104 concentrates storage one group of data protection mode parameter 130 in a presumptive address of flash memory 114.In an embodiment, this data protection mode parameter 130 is stored in logical block addresses (logical block address, LBA) 0 part of flash memory 114.Fig. 2 is the schematic diagram according to data protection mode parameter 200 of the present invention.In an embodiment, data protection mode parameter 200 comprises 8 bytes.The first character joint of data protection mode parameter 200 is protected mode startup variable, and in order to record, whether flash memory devices 104 starts data protection mode.When flash memory devices 104 does not start data protection mode, the controller 112 of flash memory devices 104 can not carry out identification to the status of main frame, and the data access order that normal process from host receives.
Second byte of data protection mode parameter 200 is protected mode setup parameter, be used to controller 112 pick out current main frame for other main frame time, the processing mode of the data access order that setting controller 112 sends for other main frame.3rd byte of data protection mode parameter 200, for reading address setup parameter, is used for the source of the presumptive address compared with the reading address that sends with main frame in order to setting.In an embodiment, store a presumptive address table 140 in flash memory 114, comprise multiple presumptive address.Controller 112, except the reading address that can send according to addresses and the main frame reading address record 140 record compares, also can choose one group of presumptive address so that the reading address sent with main frame compares according to reading address setup parameter from presumptive address table 145.4th byte of data protection mode parameter 200 is reading times parameter, needs from host to receive for the reading order compared and the number reading address in order to setting.5th, six, seven bytes of data protection mode parameter 200 retain in the future, and Eight characters joint is check code (checksum).
Fig. 3 A is the schematic diagram according to reading address of the present invention record 300.Whenever flash memory devices 104 from host 102 receives a reading order, controller 112 just records reading address that reading order comprises in reading address record 300.The reading times parameter of tentation data protected mode parameter is 10, therefore reads in address record 300 and only comprises 10 reading addresses, be sequentially respectively address A
1~ address A
10.Fig. 3 B is the schematic diagram according to presumptive address table 350 of the present invention.Presumptive address table 350 comprises many groups predetermined reading address, and each group is predetermined reads the value that address corresponds to reading address setup parameter.Such as, suppose that the scope of the value reading address setup parameter is from 0x00 ~ 0xFF, its intermediate value 0x00 corresponds to and reads address record 140.Therefore, presumptive address table 350 comprises the many groups of predetermined reading addresses corresponding to the value 0x01 ~ 0xFF reading address setup parameter.Such as, the predetermined reading address corresponding to the value 0x01 reading address setup parameter is sequentially A
11, A
12, A
13..., A
19, A
10, and the predetermined reading address corresponding to the value 0x03 reading address setup parameter is sequentially A
31, A
32, A
33..., A
39, A
30.
4th figure is the process flow diagram of the data guard method 400 according to flash memory devices 104 of the present invention.After the power supply of flash memory devices 104 connects, first controller 112 reads a data protection mode parameter 130 (step 402) from a presumptive address of flash memory 114.Then, the protected mode that controller 112 can comprise according to data protection mode parameter 130 starts variable and determines whether data protection mode starts (step 404).If not, then the data access order that receives of controller 112 normal process.If the data protection mode of flash memory devices 104 starts, then after main frame 102 is coupled to flash memory devices 104, controller 112 records the multiple current reading address (step 406) of multiple reading orders that main frame 102 sends.For example, if the reading times parameter that data protection mode parameter 130 comprises is 10, then controller 112 sequentially records 10 of 10 reading orders that main frame 102 sends and reads address at present.
Then, controller 112 reads reading address setup parameter (step 408) that data protection mode parameter 130 comprises.If the value of reading address setup parameter is 0x00, then controller 112 compares according to reading the multiple in the past multiple current reading addresses that reading address and main frame 102 send stored in address record 140, with the status of identification main frame 102.If the value reading address setup parameter is 0x00, then controller 112 compares (step 410) according to reading the multiple in the past multiple current reading addresses that reading address and main frame 102 send stored in address record 140, with the status of identification main frame 102.If the value reading address setup parameter is not 0x00, then controller 112 chooses one group of predetermined reading address according to the value reading address setup parameter from presumptive address table 145, so that the multiple current reading address sent with main frame 102 compares (step 412), and the status of identification main frame 102.
Then, if the comparison result of step 410 and step 412 conforms to, then controller 112 judges that main frame 102 is the main frame having data access qualification, and therefore flash memory devices 104 enters normal access mode (step 414).When flash memory devices 112 from host 102 receives data access order, controller 112 is by the data access order received by normal process.In addition, when main frame 102 sends reading order, the reading address appended by reading order is recorded in 140, for the use of comparison in future host identity stored in reading address by controller 112.If the comparison result of step 410 and step 412 does not conform to, then controller 112 judges that main frame 102 not has the main frame of data access qualification, and therefore flash memory devices 104 enters data protection mode (step 418).In data protection mode; when main frame 102 sends money access command to flash memory devices 104; controller 112 first reads the protected mode setup parameter of data protection mode parameter 130, then according to the data access order (step 420) that protected mode setup parameter processing host 102 sends.The processing mode of the data access order sent in data protection mode middle controller 112 pairs of main frames 102 will be described in detail with Fig. 5.Finally, if main frame 102 sends a reading order to require that flash memory devices 104 reads the presumptive address in order to storage data protected mode parameter 130, then controller 112 is got back to step 402 and is re-executed method 400.
Fig. 5 is the process flow diagram of the method 500 according to the present invention's access command that processing host 102 sends under data protection mode.The reading address that controller 112 sends because of comparison main frame 102 and presumptive address are not inconsistent, and make flash memory devices 104 enter data protection mode.First, controller 112 reads the protected mode setup parameter (step 502) in data protection mode parameter 130.Then; if the value of protected mode setup parameter is 0x01 (step 504); then when controller 112 receives the access command that main frame 102 sends; data stored by flash memory 114 are all deleted (step 506) by controller 112, access protected data 120 to prevent main frame 102.If the value of protected mode setup parameter is 0x02 (step 508); then when controller 112 receives the reading order that main frame 102 sends; controller 112 sends mess code (step 510) to main frame 102, reads protected data 120 to prevent main frame 102.If the value of protected mode setup parameter is not 0x01 or 0x02 (step 508); the then reading order that sends of controller 112 normal process main frame 102; but the write order that main frame 102 sends is not responded (step 512), changes protected data to avoid main frame 102.
Although the present invention discloses as above with preferred embodiment; so itself and be not used to limit the present invention; any those who familiarize themselves with the technology; without departing from the spirit and scope of the present invention; when doing a little change and retouching, therefore protection scope of the present invention is when being as the criterion depending on the accompanying claim person of defining.
Claims (12)
1. a data guard method for flash memory devices, wherein a flash memory devices comprises a flash memory for storage one protected data, and the method comprises the following steps:
After this flash memory devices is coupled to a main frame, record the multiple current reading address that this main frame comprises to multiple reading orders that this flash memory devices sends;
More described current reading address and multiple predetermined reading address;
When described current reading address and described predetermined reading mail returned on ground of incorrect address close, this flash memory devices is made to enter a data protection mode; And
When this flash memory devices enters this data protection mode, if this flash memory devices receives multiple data access order from this main frame, according to a protected mode setup parameter processing said data access command, with prevent this protected data access by this main frame; Wherein, a presumptive address of this flash memory stores multiple data protection mode parameter, and described data protection mode parameter comprises this protected mode setup parameter, and reads address setup parameter and a reading times parameter; Wherein predetermined reading address described in this reading address setup parameter record, and the predetermined number reading address described in this reading times reference record.
2. the data guard method of flash memory devices according to claim 1; it is characterized in that; when this reading address setup parameter is 0x00, multiple past that described predetermined reading address comprises for the multiple past reading orders finally received before the previous power-off of this flash memory devices read address.
3. the data guard method of flash memory devices according to claim 1; it is characterized in that; value according to this reading address setup parameter in one presumptive address table stores multiple sets of address respectively; and when this reading address setup parameter is not 0x00, described predetermined reading address system is according to selected by described address in this presumptive address table of the value of this reading address setup parameter.
4. the data guard method of flash memory devices according to claim 1, is characterized in that, the treatment step of described data access order comprises:
If when the value of this protected mode setup parameter is 0x01, when this flash memory devices receives described data access order from this main frame, this protected data is deleted from this flash memory; And
If when the value of this protected mode setup parameter is 0x02, when this flash memory devices receives multiple reading order from this main frame, this flash memory devices is made to transmit random code (random code) to this main frame.
5. the data guard method of flash memory devices according to claim 4, is characterized in that, the treatment step of described data access order more comprises:
If when the value of this protected mode setup parameter is 0x03, do not perform the write order in described data access order, and the normal reading order performed in described data access order.
6. the data guard method of flash memory devices according to claim 1, is characterized in that, the method more comprises:
Make this flash memory devices before connecing with this main frame decoupling, sequentially store the multiple decouplings received from this main frame and connect front reading order, during to be coupled to this main frame as next time, supply the described predetermined reading address of carrying out data protection; And
Make this main frame and this flash memory devices before decoupling connects, sequentially store the described decoupling being sent to this flash memory devices and connect front reading order, during to be coupled to this flash memory devices as next time, be sent to the described current reading address of this flash memory devices.
7. a flash memory devices, comprising:
One flash memory, stores a protected data, multiple predetermined reading address and a protected mode setup parameter; And
One controller, the multiple current reading address that this main frame comprises to multiple reading orders that this flash memory devices sends is recorded after this flash memory devices is coupled to a main frame, more described current reading address and described predetermined reading address, this flash memory devices is made to enter a data protection mode when described current reading address and described predetermined reading mail returned on ground of incorrect address close, and when this flash memory devices enters this data protection mode, if this flash memory devices receives multiple data access order from this main frame, according to this protected mode setup parameter processing said data access command, with prevent this protected data access by this main frame, wherein, a presumptive address of this flash memory stores described data protection mode parameter, and described data protection mode parameter comprises this protected mode setup parameter, and reads address setup parameter and a reading times parameter, wherein predetermined reading address described in this reading address setup parameter record, and the predetermined number reading address described in this reading times reference record.
8. flash memory devices according to claim 7, it is characterized in that, when this reading address setup parameter is 0x00, multiple past that described predetermined reading address comprises for the multiple past reading orders finally received before the previous power-off of this flash memory devices read address.
9. flash memory devices according to claim 7, it is characterized in that, value according to this reading address setup parameter in one presumptive address table stores multiple sets of address respectively, and when this reading address setup parameter is not 0x00, described predetermined reading address system is according to selected by described address in this presumptive address table of the value of this reading address setup parameter.
10. flash memory devices according to claim 7, it is characterized in that, when this controller is according to this protected mode setup parameter processing said data access command, if when the value of this protected mode setup parameter is 0x01, this protected data is deleted from this flash memory by this controller; If when the value of this protected mode setup parameter is 0x02, when this flash memory devices receives multiple reading order from this main frame, this controller makes this flash memory devices transmit random code (random code) to this main frame.
11. flash memory devices according to claim 7; it is characterized in that; when this controller is according to this protected mode setup parameter processing said data access command; if when the value of this protected mode setup parameter is 0x03; this controller does not perform the write order in described data access order, and the normal reading order performed in described data access order.
12. flash memory devices according to claim 7; it is characterized in that; when this flash memory devices is before connecing with this main frame decoupling; this controller sequentially stores the described predetermined reading address supplying to carry out data protection when the multiple decouplings received from this main frame connect front reading order to be coupled to this main frame as next time, and this main frame sequentially stores the described current reading address being sent to this flash memory devices when the described decoupling being sent to this flash memory devices connects front reading order to be coupled to this flash memory devices as next time.
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| CN201110118864.XA CN102760102B (en) | 2011-04-26 | 2011-04-26 | Flash memory device and data protection method thereof |
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|---|---|---|---|
| CN201110118864.XA CN102760102B (en) | 2011-04-26 | 2011-04-26 | Flash memory device and data protection method thereof |
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Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6009495A (en) * | 1989-12-29 | 1999-12-28 | Packard Bell Nec | Protected address range in an electrically erasable programmable read only memory |
| CN101211319A (en) * | 2006-12-31 | 2008-07-02 | 深圳市朗科科技有限公司 | Program file protection method for memory and protection device |
| CN101546297A (en) * | 2008-03-27 | 2009-09-30 | 创惟科技股份有限公司 | System and method thereof for protecting access of flash memory |
-
2011
- 2011-04-26 CN CN201110118864.XA patent/CN102760102B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6009495A (en) * | 1989-12-29 | 1999-12-28 | Packard Bell Nec | Protected address range in an electrically erasable programmable read only memory |
| CN101211319A (en) * | 2006-12-31 | 2008-07-02 | 深圳市朗科科技有限公司 | Program file protection method for memory and protection device |
| CN101546297A (en) * | 2008-03-27 | 2009-09-30 | 创惟科技股份有限公司 | System and method thereof for protecting access of flash memory |
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