CN102750245A - Message receiving method, module and system as well as device - Google Patents
Message receiving method, module and system as well as device Download PDFInfo
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- CN102750245A CN102750245A CN2012101718867A CN201210171886A CN102750245A CN 102750245 A CN102750245 A CN 102750245A CN 2012101718867 A CN2012101718867 A CN 2012101718867A CN 201210171886 A CN201210171886 A CN 201210171886A CN 102750245 A CN102750245 A CN 102750245A
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Abstract
The invention provides a message receiving method, module and system as well as a device. The message receiving method comprises the following steps of: constructing a message with a physical address and a virtual address in a first descriptor of a first descriptor queue, and a virtual address in a second descriptor in the first descriptor queue to be a bus message after receiving the message; sending the bus message to an internal memory and a current message buffering area corresponding to the physical address in the first descriptor, so that a central processor reads the message in the current message buffering area according to a virtual address corresponding to the current message buffering area; and after clearing the physical address and the virtual address in the first descriptor, shifting a descriptor sequence in the first descriptor queue. With the message receiving method provided by the invention, the central processor can sequentially read content in the message buffering area in a polling manner, so that the processing efficiency of the system is effectively improved, and the system cost is reduced.
Description
Technical field
The present invention relates to computer communication technology, relate in particular to a kind of message method of reseptance, message receiver module, Apparatus and system.
Background technology
Direct access memory (Direct Memory Access, DMA) technology is the method for high speed transmission data between a kind of peripheral hardware and the internal memory, the external apparatus interface card can directly be visited the data in the mainframe memory with dma mode.
The DMA transmission technology adopts two kinds of gordian techniquies, and promptly the message buffer descriptor is safeguarded and interrupt handling program.The message buffer descriptor is safeguarded and is mainly used in application and the management to the message buffer of descriptor and descriptor indication; Interrupt handling program relates generally to the release of interior message processing of buffer zone and buffer zone.
But; The software-hardware synergism that needs synchronously that receives and send descriptor is safeguarded, multiple register need be set, for example; Descriptor base register, interrupt register, outage threshold register, descriptor quantity register and overtime register etc.; Dealing with complicated not only, and taken a large amount of central processing units (Central Processing Unit, expense CPU) and hardware logic resource.Down trigger mechanism need produce to CPU according to preset threshold interrupts, if interruption times is too frequent, can cause a large amount of process switching expenses, influences the work efficiency of CPU.Therefore, there is the lower problem of system handles efficient in DMA transmission technology of the prior art.
Summary of the invention
The present invention provides a kind of treatment effeciency that is used to improve the DMA transmission technology, and reduces message method of reseptance, message receiver module, the Apparatus and system of system overhead.
First aspect of the present invention provides a kind of message method of reseptance, comprising:
Receive after the message, with physical address and the virtual address in first descriptor in the said message and first descriptor queue, and the virtual address in second descriptor in said first descriptor queue is configured to bus message;
Wherein, said first descriptor comprises the physical address and the virtual address of current message buffer zone in the internal memory; The said second descriptor series arrangement comprises the physical address and the virtual address of the next message buffer behind the current message buffer zone described in the said internal memory after said first descriptor;
With said bus message be sent in the said internal memory with said first descriptor in the corresponding said current message buffer zone of physical address; According to said current message buffer zone corresponding virtual address, read the message in the said current message buffer zone for central processing unit;
Remove after the physical address and virtual address in said first descriptor; Descriptor in said first descriptor queue is shifted in proper order, so that physical address in said second descriptor and virtual address become physical address and virtual address in first descriptor after the renewal.
Another aspect of the present invention provides a kind of message receiver module, comprising:
First receiving element; Be used for after receiving message; With physical address and the virtual address in first descriptor in the said message and first descriptor queue, and the virtual address in second descriptor in said first descriptor queue is configured to bus message;
Wherein, said first descriptor comprises the physical address and the virtual address of current message buffer zone in the internal memory; The said second descriptor series arrangement comprises the physical address and the virtual address of the next message buffer behind the current message buffer zone described in the said internal memory after said first descriptor;
First transmitting element; Be used for said bus message is sent to said internal memory and the corresponding said current message buffer zone of physical address in said first descriptor; According to said current message buffer zone corresponding virtual address, read the message in the said current message buffer zone for central processing unit;
First processing unit; Be used for after the physical address and virtual address of removing said first descriptor; Descriptor in said first descriptor queue is shifted in proper order, so that physical address in said second descriptor and virtual address become physical address and virtual address in first descriptor after the renewal.
Another aspect of the present invention provides a kind of NIC, comprises above-mentioned message receiver module.
The present invention also provides a kind of message receiving system, comprises above-mentioned NIC, internal memory and central processing unit.
Message method of reseptance provided by the invention, message receiver module, Apparatus and system; The bus message of the descriptor through the message that receives being configured to comprise current message buffer zone in the internal memory and the descriptor of next message buffer; Make the virtual address that to know next message buffer when CPU reads the message of current message buffer zone from internal memory; Thereby can read the content in the message buffer in proper order through the mode of poll, need not use multiple register to cooperate, also need not produce and interrupt to CPU; Improve the treatment effeciency of system effectively, reduced system overhead.
Description of drawings
Fig. 1 is the process flow diagram of message method of reseptance one embodiment of the present invention;
Fig. 2 is the synoptic diagram of message buffer form in the embodiment of the invention internal memory;
Fig. 3 is the process flow diagram of another embodiment of message method of reseptance of the present invention;
Fig. 4 is the process flow diagram that embodiment of the invention message receiver module receives message;
Fig. 5 receives the process flow diagram of message for embodiment of the invention central processing unit;
Fig. 6 is the structural representation of message receiver module embodiment of the present invention;
Fig. 7 is the structural representation of message receiving system embodiment of the present invention;
Fig. 8 is a kind of system architecture of embodiment of the invention message receiving system.
Embodiment
Technical scheme in the various embodiments of the present invention is that host memory is received the improvement that method of message is carried out from dma controller.Dma controller adopts the packet sending and receiving between realization of DMA technology and the host memory, and wherein, dma controller comprises that DMA sends engine and DMA receives engine.DMA sends engine and is used for the message of host memory is sent to the external device or the network equipment etc.; DMA receives engine and is used for the message that receives from external device or the network equipment is sent to host memory.
Message receiver module in the various embodiments of the present invention comprises that DMA receives engine and relevant functional module, and promptly the message receiver module in following each embodiment has the function of DMA reception engine and relevant control and processing capacity; Host memory also is called internal memory for short in following each embodiment; Central processing unit also is called CPU for short in following each embodiment.
Fig. 1 is the process flow diagram of message method of reseptance one embodiment of the present invention, and as shown in Figure 1, this method comprises:
Wherein, said first descriptor comprises the physical address and the virtual address of current message buffer zone in the internal memory; The said second descriptor series arrangement comprises the physical address and the virtual address of the next message buffer behind the current message buffer zone described in the said internal memory after said first descriptor.
The message receiver module need be configured to bus message with the message that receives after external device or the network equipment receive message, this bus message comprises descriptor field and message territory.
Concrete building method does; Read first descriptor and second descriptor in first descriptor queue that from this message receiver module, stores; With physical address in first descriptor and virtual address; Virtual address in second descriptor, and control information and the message that receives are configured to bus message.Wherein, physical address in first descriptor and virtual address, virtual address in second descriptor and control information are stored in the descriptor field of bus message, and the message that receives is stored in the message territory of bus message.Comprise sequence of information in the bus message and control, construct according to the agreement of communicating pair and get final product by message receiver module and the software program that is stored in advance among the CPU.
Wherein, First descriptor queue that stores in the message receiver module; Comprise at least two tactic descriptors, each descriptor includes a physical address and a virtual address, and in the same descriptor physical address and virtual address corresponding the same storage space in the internal memory.
Difference is; Physical address is the actual address of the storage space of stored messages in the internal memory; Be used for supplying other devices or module according to this physical address with in the message write memory corresponding memory space; When CPU need read the message of this storage space in the internal memory, then need visit this storage space according to virtual address, what physical address and virtual address were pointed to is the same storage space in the internal memory.
Because the descriptor in first descriptor queue is tactic, the descriptor definition that therefore will wherein be positioned at the formation reference position is first descriptor, is second descriptor with the descriptor definition of series arrangement after first describes.First and second only are used for the location order of flag descriptor in formation.
At structure during bus message, the storage space in the internal memory that the physical address in first descriptor and virtual address is pointed is as the destination of this bus message; Except comprising destination-address; Also in bus message, carry the virtual address in second descriptor; Storage space in virtual address in this second descriptor internal memory pointed is the storage space of series arrangement after bus message sends the destination, i.e. next message buffer.
The transmitting state information that comprises this bus message in the control information comprises that in addition the length of message in the message territory of this bus message and the port information of message transmission etc. guarantee the information of message normal transmission.
With the virtual address in the physical address in first descriptor and virtual address, second descriptor; And control information is stored in the descriptor field of bus message; The message that receives is stored in the message territory, is bus message with descriptor field and message domain construction.
What the message buffer of the reception bus message in the internal memory adopted is the chain sheet form, concrete, and the virtual address in second descriptor of preserving in the current message buffer zone is the pointer that points to next message buffer.
It is understandable that, can normally receive the bus message that the message receiver module is sent in order to guarantee internal memory, the form that receives the message buffer of bus message in the form of bus message and the internal memory is consistent.
Fig. 2 is the synoptic diagram of message buffer form in the embodiment of the invention internal memory, and is as shown in Figure 2, and the form of message buffer is illustrated.
Message buffer is made up of descriptor field and message territory, and the size of wherein establishing message buffer is 2KB, is divided into 64 unit, and the size of each unit is 256.Wherein, The 1st unit is the descriptor field of message buffer; 64 physical address Phy_Addr that comprise the current message buffer zone, 64 virtual address Virt_Addr, 64 virtual address Next_Virt_Addr of next message buffer after 64 control information Ctrl_Status and the current message buffer zone; Wherein comprise 1 hardware transmission completion flag HWCpl in the control information, all the other positions keep; 64 unit, the 2nd unit to the are message territory Packet.
Wherein, Phy_Addr is the physical address of current message buffer zone, and the message receiver module can write this current message buffer with message according to this physical address.
Virt_Addr is the virtual address of current message buffer zone, and CPU can be according to the message in this this current message buffer of virtual address visit.
Ctrl_Status is the control information of this bus message, mainly comprises transmission completion flag HWCpl.When if message buffer does not receive bus message; This flag is 0 in the descriptor field of this message buffer; This flag is 1 in the bus message that the message receiver module is constructed, and after message buffer received bus message, this flag promptly was updated to 1 so; Thereby explain that message buffer has received bus message, the message transmissions of message receiver module and internal memory is accomplished; If with control information in the message receiver module be made as 0 with message buffer in control information be made as 1, have the renewal receive control information after the bus message in can realizing equally, and the form of control information is not limited in this.
Next_Virt_Addr is the virtual address of next message buffer after this current message buffer; Be used to supply CPU when visit current message buffer zone, to know the virtual address of next message buffer; Thereby when next message buffer of needs visit, utilize this virtual address can realize visit.
The message territory is used to store the message content that receives.Because the form of the bus message that the message receiver module is sent is consistent with the form of message buffer; Message buffer is not when receiving bus message; Comprise the address information and the control information of current message buffer zone, next message buffer in its descriptor field, and the message territory is empty; The current message buffer zone receives after the bus message, and the content of bus message covers the content of current message buffer zone, thereby makes the control information in the current message buffer zone obtain upgrading, and has write message content in the message territory.
It is understandable that, more than illustrational content be merely a kind of implementation in the embodiment of the invention, optional implementation is not limited in this.
Step 102, with said bus message be sent in the said internal memory with said first descriptor in the corresponding said current message buffer zone of physical address; According to said current message buffer zone corresponding virtual address, read the message in the said current message buffer zone for central processing unit.
The message receiver module is after having constructed bus message; The entrained physical address that from first descriptor, reads in the descriptor field according to this bus message; Bus message is sent to the corresponding message buffer of this physical address, and this message buffer is the current message buffer zone.
The message receiver module is sent to bus message after the internal memory, and CPU can be according to the virtual address of the message buffer of correspondence, from internal memory, reads the message content in the message territory of this message buffer.
CPU judges the control information in the descriptor field of current message buffer zone; Received message if judge the current message buffer zone; Then read message in the message territory of current message buffer zone, do not receive message, then be in waiting status if judge in the current message buffer zone.
After the physical address and virtual address in step 103, said first descriptor of removing; Descriptor in said first descriptor queue is shifted in proper order, so that physical address in said second descriptor and virtual address become physical address and virtual address in first descriptor after the renewal.
The message receiver module is after the bus message with structure is sent to internal memory, and the content that first descriptor in first descriptor queue is corresponding is removed, that is, physical address in first descriptor and virtual address are removed.And, because series arrangement has two or more descriptors in first descriptor queue, if the descriptor in first descriptor queue is three or when above; Descriptor in this first descriptor queue is shifted in proper order, that is to say, after the content in first descriptor is eliminated; First descriptor is empty; Descriptor integral body is shifted forward, make the physical address and the virtual address that are arranged in second descriptor be displaced to first descriptor, the descriptor that in former first descriptor queue, is arranged in the 3rd position is displaced in second descriptor; By that analogy; Descriptor is all to one of reach, and correspondingly, the memory location of the descriptor at end is empty in first descriptor queue.Physical address and virtual address in first descriptor and second descriptor have obtained renewal respectively.
In practical application; The message receiver module is when the structure bus message; From first descriptor queue, read first descriptor and second descriptor mode can also for; Deposit first descriptor that reads in register Cur_Des, deposit second descriptor that reads in register Next_Des, utilize the descriptor construction bus message in these two registers; And after preceding two descriptors in first descriptor queue were read, removing for two descriptors, the descriptor integral body in the formation shifted forward, and made the position of the initial memory descriptor of the descriptor queue that wins not be sky; Thereby after the message receiver module sends this bus message; When next bus message of structure; Physical address of storing among the former register Cur_Des and virtual address are removed, and physical address and virtual address among the former register Next_Des deposit register Cur_Des in, and the initial position that continues from first descriptor queue reads new descriptor; Deposit register Next_Des in, and by that analogy.
Message method of reseptance in the embodiment of the invention; The bus message of the descriptor through the message that receives being configured to comprise current message buffer zone in the internal memory and the descriptor of next message buffer; Make the virtual address that to know next message buffer when CPU reads the message of current message buffer zone from internal memory; Thereby can read the content in the message buffer in proper order through the mode of poll, need not use multiple register to cooperate, also need not produce and interrupt to CPU; Improve the treatment effeciency of system effectively, reduced system overhead.
Further, on the basis of the foregoing description, after the execution in step 103, this method also comprises:
Step 104, receive and to be sent after the message of said central processing unit in reading said current message buffer zone, the recovery command that the physical address and the virtual address of said current message buffer zone reclaimed.
Step 105, the physical address that carries in the said recovery command and virtual address deposited in the end of said first descriptor queue.
CPU is after reading message from the current message buffer zone; The message that reads is sent to network protocol stack; And send recovery command to the message receiver module; Carry the physical address and the virtual address of current message buffer zone in this recovery command, that is to say, this message buffer can continue to be used for receiving the bus message that the message receiver module is sent.
At this moment; Control information in the descriptor field in this current message buffer is updated to the state that does not receive bus message; And the content in the message territory keeps; Wait for when this message buffer receives follow-up bus message that the content in this message territory will be covered by the content in the message territory of new bus message.
The message receiver module is stored in the physical address that carries in this recovery command and virtual address on the room at end of first descriptor queue after receiving the recovery command that CPU sends.
Message method of reseptance in the embodiment of the invention; After having read the message of current message buffer zone in the internal memory at CPU; Indication message receiver module reclaims the descriptor of current message buffer zone, deposits the end of first descriptor queue in, so that message receiver module order is when reading the descriptor construction bus message from first descriptor queue; Can get access to available descriptor continuously; Thereby avoided the message receiver module after available descriptor all is used, to initiate the action of interrupting, improved the treatment effeciency of system effectively, reduced system overhead.
Fig. 3 is the process flow diagram of another embodiment of message method of reseptance of the present invention, and as shown in Figure 3 before the execution in step 101 on the basis of above-mentioned each embodiment, this method also comprises:
Wherein, said second descriptor queue stores at least two message buffers descriptor separately in the said internal memory, and said descriptor comprises physical address and the virtual address of said message buffer in said internal memory.
The descriptor of step 201, the said quantity that will from said internal memory, read according to said base address is as said first descriptor queue.
Before the message receiver module receives message, need obtain first descriptor queue that is used to construct bus message earlier.
Concrete grammar does, CPU can be stored in the descriptor of initialized two message buffers in the internal memory in the formation when internally depositing into capable initialization at least, and this formation is second descriptor queue.Preserved these at least two message buffers descriptor separately in second descriptor queue, the descriptor of each message buffer comprise this message buffer physical address and with this physical address corresponding virtual address; CPU sends to the message receiver module with the quantity of the descriptor of storing in the base address of second descriptor queue and second descriptor queue, and wherein this base address is the initial physical address of storage second descriptor queue; The message receiver module is according to this base address and quantity, and this base address corresponding memory space from internal memory reads the descriptor of this quantity, and the descriptor that reads is formed first descriptor queue in proper order, is used to construct bus message.
Message method of reseptance in the embodiment of the invention when depositing into capable initialization, obtains the descriptor of the message buffer in the internal memory to interior through CPU; CPU is used to construct bus message, owing to after the descriptor of the message buffer that has read, can inform that the message receiver module reclaims this descriptor; The descriptor that makes the message receiver module when internal memory initialization, obtain can be recycled; Need not to produce interruption, improved the treatment effeciency of system effectively, reduced system overhead to CPU.
Further, on the basis of above-mentioned each embodiment, when CPU read the message in the current message buffer zone from internal memory, it knew that the method for the virtual address of current message buffer zone has following two kinds.
First kind of situation do, if said bus message be to the first bus message of said internal memory transmission, that is to say, CPU after internally depositing into capable initialization, the situation of first message buffer in the access memory.
CPU deposits into after the capable initialization interior; Virtual address in the first descriptor in second descriptor queue that stores in the internal memory is the virtual address of first message buffer; CPU reads the virtual address of first descriptor from second descriptor queue; Get final product message buffer corresponding in the access memory, the message content in the message territory of acquisition current message buffer zone.
Second kind of situation does; If said bus message is not the first bus message that sends to said internal memory; That is to say; CPU has read the message in the message buffer from internal memory, then CPU can be known the virtual address of the message buffer that preparation is read from the descriptor field of this message buffer that has read.CPU gets final product the current message buffer zone in the access memory according to this virtual address, reads the message content in the message territory in the current message buffer zone.The rest may be inferred; Can know according to the structure of bus message and the form of message buffer; CPU can be known the virtual address of next message buffer from the descriptor field of current message buffer zone, thereby can be according to this next message buffer of virtual address visit that learns.
Message method of reseptance in the embodiment of the invention, CPU read after the message according to the virtual address of first message buffer after to internal memory initialization; Can visit next message buffer according to the virtual address of next message buffer in the descriptor field of current message buffer zone, and utilize the message buffer in the method poll internal memory; Do not need to safeguard separately the descriptor tabulation; Need not produce yet and interrupt, improve the treatment effeciency of system effectively, reduce system overhead to CPU.
Fig. 4 is the process flow diagram that embodiment of the invention message receiver module receives message, and is as shown in Figure 4, and the flow process that the message receiver module receives message comprises:
Physical address and virtual address that step 404, the utilization of message receiver module are extracted from register Cur_Des and register Next_Des, and message that receives and the needed control information of message transmission, structure comprises the bus message of above-mentioned each data;
Fig. 5 is for the process flow diagram of embodiment of the invention central processing unit reception message, and is as shown in Figure 5, and the flow process that central processing unit receives message comprises:
Step 500, CPU are extracted the thread parameter, when internally depositing into capable initialization, and the virtual address of first message buffer in second descriptor queue that stores in the internal memory, the corresponding message buffer in this virtual address is read in visit;
Step 501, CPU accomplish flag HWCpl according to transmission, judge whether message is arranged in the current message buffer zone, and when not receiving bus message owing to this message buffer, its HWCpl is 0, and after receiving bus message, HWCpl is 1; Thereby do not receive bus message, the execution in step 501 that then circulates, wait reception bus message if judge in the current message buffer zone according to HWCpl; If judge and received bus message in the current message buffer zone, then execution in step 502;
Step 502, CPU are after receiving bus message; The summary info of message in the message territory of extraction bus message; And execution in step 503 with summary info store into the summary formation in, for system quantity, byte length, the quantity of data stream and the information such as duration of data stream of received message are carried out record; Continue execution in step 504 simultaneously;
Need to prove that the implementation in the step 502 is identical with mode used in the prior art;
Step 504, CPU are sent to network protocol stack with the message that receives, and wherein network protocol stack is a upper layer application;
Step 505, CPU receive and handle after the message, the HWCpl in the descriptor field of this message buffer are reverted to original state, i.e. zero clearing;
The message buffer that step 506, CPU will read reclaims; The physical address and the virtual address of this message buffer are carried in the recovery command; Send to the message receiver module, indication message receiver module reclaims this message buffer, that is to say; This message buffer is in upstate, can be used for receiving new bus message;
The virtual address of next entrained message buffer in step 507, the descriptor field of CPU according to the message buffer that has read, promptly addressable next message buffer, thus realize the poll of CPU to the message buffer in the internal memory.
The embodiment of the invention is through being configured to the message that receives; The bus message of the descriptor that comprises current message buffer zone in the internal memory and the descriptor of next message buffer; Make the virtual address that to know next message buffer when CPU reads the message of current message buffer zone from internal memory; Thereby can read the content in the message buffer in proper order through the mode of poll, need not use multiple register to cooperate, also need not produce and interrupt to CPU; Improve the treatment effeciency of system effectively, reduced system overhead.
One of ordinary skill in the art will appreciate that: all or part of step that realizes above-mentioned each method embodiment can be accomplished through the relevant hardware of programmed instruction.Aforesaid program can be stored in the computer read/write memory medium.This program the step that comprises above-mentioned each method embodiment when carrying out; And aforesaid storage medium comprises: various media that can be program code stored such as ROM, RAM, magnetic disc or CD.
Fig. 6 is the structural representation of message receiver module embodiment of the present invention, and as shown in Figure 6, this message receiver module comprises:
First receiving element 11; Be used for after receiving message; With physical address and the virtual address in first descriptor in the said message and first descriptor queue, and the virtual address in second descriptor in said first descriptor queue is configured to bus message;
Wherein, said first descriptor comprises the physical address and the virtual address of current message buffer zone in the internal memory; The said second descriptor series arrangement comprises the physical address and the virtual address of the next message buffer behind the current message buffer zone described in the said internal memory after said first descriptor;
First transmitting element 12; Be used for said bus message is sent to said internal memory and the corresponding said current message buffer zone of physical address in said first descriptor; According to said current message buffer zone corresponding virtual address, read the message in the said current message buffer zone for central processing unit;
First processing unit 13; Be used for after the physical address and virtual address of removing said first descriptor; Descriptor in said first descriptor queue is shifted in proper order, so that physical address in said second descriptor and virtual address become physical address and virtual address in first descriptor after the renewal.
Further, on the basis of the foregoing description, this message receiver module also comprises:
Second receiving element 14; Be used for after said first processing unit 13 is shifted the descriptor of said first descriptor queue in proper order; Receive and sent after the message of said central processing unit in reading said current message buffer zone, the recovery command that the physical address and the virtual address of said current message buffer zone reclaimed;
Further, on the basis of above-mentioned each embodiment, this message receiver module also comprises:
The 3rd receiving element 16; Be used for before said first receiving element 11 receives message; Receive said central processing unit after said internal memory is carried out initialization, the base address of second descriptor queue in the said internal memory of transmission, and the quantity of descriptor in said second descriptor queue;
Wherein, said second descriptor queue stores at least two message buffers descriptor separately in the said internal memory, and said descriptor comprises physical address and the virtual address of said message buffer in said internal memory;
The 3rd processing unit 17 is used for the descriptor with the said quantity that reads from said internal memory according to said base address, as said first descriptor queue.
Further, on the basis of above-mentioned each embodiment, if said first transmitting element 12 is first bus message to the bus message that said internal memory sends;
Correspondingly; Said first transmitting element 12 also is used for; With said bus message be sent in the said internal memory with said first descriptor in the corresponding said current message buffer zone of physical address; According to the virtual address in the first descriptor in said second descriptor queue, read the message in the said current message buffer zone for said central processing unit;
If said first transmitting element 12 is not first bus message to the bus message that said internal memory sends;
Correspondingly; Said first transmitting element 12 also is used for; With said bus message be sent in the said internal memory with said first descriptor in the corresponding said current message buffer zone of physical address; The virtual address of the said current message buffer zone that reads according to the last message buffer before said current message buffer zone for said central processing unit reads the message in the said current message buffer zone.
Need to prove that first, second that is adopted during to the name of each functional module and C grade content only are used to distinguish each functional module, do not represent the order between each functional module.
Concrete, the message receiver module in the embodiment of the invention carries out the method that message receives, and can repeat no more referring to the method embodiment of above-mentioned correspondence here.
Message receiver module in the embodiment of the invention; The bus message of the descriptor through the message that receives being configured to comprise current message buffer zone in the internal memory and the descriptor of next message buffer; Make the virtual address that to know next message buffer when CPU reads the message of current message buffer zone from internal memory; Thereby can read the content in the message buffer in proper order through the mode of poll, need not use multiple register to cooperate, also need not produce and interrupt to CPU; Improve the treatment effeciency of system effectively, reduced system overhead.
Fig. 7 is the structural representation of message receiving system embodiment of the present invention; Fig. 8 is a kind of system architecture of embodiment of the invention message receiving system.As shown in Figure 7, this message receiving system comprises NIC 1, internal memory 2 and central processing unit 3, wherein comprises message receiver module 4 in the NIC 1.
Concrete, the message receiving system is carried out the method that message receives in the embodiment of the invention, can repeat no more referring to the method embodiment of above-mentioned correspondence here.
Message receiving system in the embodiment of the invention; The bus message of the descriptor through the message that receives being configured to comprise current message buffer zone in the internal memory and the descriptor of next message buffer; Make the virtual address that to know next message buffer when CPU reads the message of current message buffer zone from internal memory; Thereby can read the content in the message buffer in proper order through the mode of poll, need not use multiple register to cooperate, also need not produce and interrupt to CPU; Improve the treatment effeciency of system effectively, reduced system overhead.
What should explain at last is: above each embodiment is only in order to explaining technical scheme of the present invention, but not to its restriction; Although the present invention has been carried out detailed explanation with reference to aforementioned each embodiment; Those of ordinary skill in the art is to be understood that: it still can be made amendment to the technical scheme that aforementioned each embodiment put down in writing, perhaps to wherein part or all technical characteristic are equal to replacement; And these are revised or replacement, do not make the scope of the essence disengaging various embodiments of the present invention technical scheme of relevant art scheme.
Claims (10)
1. a message method of reseptance is characterized in that, comprising:
Receive after the message, with physical address and the virtual address in first descriptor in the said message and first descriptor queue, and the virtual address in second descriptor in said first descriptor queue is configured to bus message;
Wherein, said first descriptor comprises the physical address and the virtual address of current message buffer zone in the internal memory; The said second descriptor series arrangement comprises the physical address and the virtual address of the next message buffer behind the current message buffer zone described in the said internal memory after said first descriptor;
With said bus message be sent in the said internal memory with said first descriptor in the corresponding said current message buffer zone of physical address; According to said current message buffer zone corresponding virtual address, read the message in the said current message buffer zone for central processing unit;
Remove after the physical address and virtual address in said first descriptor; Descriptor in said first descriptor queue is shifted in proper order, so that physical address in said second descriptor and virtual address become physical address and virtual address in first descriptor after the renewal.
2. message method of reseptance according to claim 1 is characterized in that, said descriptor in said first descriptor queue is shifted in proper order after, said method also comprises:
Receive and sent after the message of said central processing unit in reading said current message buffer zone, the recovery command that the physical address and the virtual address of said current message buffer zone reclaimed;
The physical address that carries in the said recovery command and virtual address are deposited in the end of said first descriptor queue.
3. message method of reseptance according to claim 1 and 2 is characterized in that, said receiving before the message, and said method also comprises:
Receive said central processing unit after said internal memory is carried out initialization, the base address of second descriptor queue in the said internal memory of transmission, and the quantity of descriptor in said second descriptor queue;
Wherein, said second descriptor queue stores at least two message buffers descriptor separately in the said internal memory, and said descriptor comprises physical address and the virtual address of said message buffer in said internal memory;
The descriptor of the said quantity that will from said internal memory, read according to said base address is as said first descriptor queue.
4. message method of reseptance according to claim 3 is characterized in that, if said bus message is the first bus message that sends to said internal memory;
Correspondingly; Said with said bus message be sent in the said internal memory with said first descriptor in the corresponding said current message buffer zone of physical address; According to said current message buffer zone corresponding virtual address, the message that reads in the said current message buffer zone comprises for central processing unit:
With said bus message be sent in the said internal memory with said first descriptor in the corresponding said current message buffer zone of physical address; According to the virtual address in the first descriptor in said second descriptor queue, read the message in the said current message buffer zone for said central processing unit;
If said bus message is not the first bus message that sends to said internal memory;
Correspondingly; Said with said bus message be sent in the said internal memory with said first descriptor in the corresponding said current message buffer zone of physical address; According to said current message buffer zone corresponding virtual address, the message that reads in the said current message buffer zone comprises for central processing unit:
With said bus message be sent in the said internal memory with said first descriptor in the corresponding said current message buffer zone of physical address; The virtual address of the said current message buffer zone that reads according to the last message buffer before said current message buffer zone for said central processing unit reads the message in the said current message buffer zone.
5. a message receiver module is characterized in that, comprising:
First receiving element; Be used for after receiving message; With physical address and the virtual address in first descriptor in the said message and first descriptor queue, and the virtual address in second descriptor in said first descriptor queue is configured to bus message;
Wherein, said first descriptor comprises the physical address and the virtual address of current message buffer zone in the internal memory; The said second descriptor series arrangement comprises the physical address and the virtual address of the next message buffer behind the current message buffer zone described in the said internal memory after said first descriptor;
First transmitting element; Be used for said bus message is sent to said internal memory and the corresponding said current message buffer zone of physical address in said first descriptor; According to said current message buffer zone corresponding virtual address, read the message in the said current message buffer zone for central processing unit;
First processing unit; Be used for after the physical address and virtual address of removing said first descriptor; Descriptor in said first descriptor queue is shifted in proper order, so that physical address in said second descriptor and virtual address become physical address and virtual address in first descriptor after the renewal.
6. message receiver module according to claim 5 is characterized in that, said message receiver module also comprises:
Second receiving element; Be used for after said first processing unit is shifted the descriptor of said first descriptor queue in proper order; Receive and sent after the message of said central processing unit in reading said current message buffer zone, the recovery command that the physical address and the virtual address of said current message buffer zone reclaimed;
Second processing unit, the end that physical address that is used for said recovery command is carried and virtual address deposit said first descriptor queue in.
7. according to claim 5 or 6 described message receiver modules, it is characterized in that said message receiver module also comprises:
The 3rd receiving element; Be used for before said first receiving element receives message; Receive said central processing unit after said internal memory is carried out initialization, the base address of second descriptor queue in the said internal memory of transmission, and the quantity of descriptor in said second descriptor queue;
Wherein, said second descriptor queue stores at least two message buffers descriptor separately in the said internal memory, and said descriptor comprises physical address and the virtual address of said message buffer in said internal memory;
The 3rd processing unit is used for the descriptor with the said quantity that reads from said internal memory according to said base address, as said first descriptor queue.
8. message receiver module according to claim 7 is characterized in that, if said first transmitting element is first bus message to the bus message that said internal memory sends;
Correspondingly; Said first transmitting element also is used for; With said bus message be sent in the said internal memory with said first descriptor in the corresponding said current message buffer zone of physical address; According to the virtual address in the first descriptor in said second descriptor queue, read the message in the said current message buffer zone for said central processing unit;
If said first transmitting element is not first bus message to the bus message that said internal memory sends;
Correspondingly; Said first transmitting element also is used for; With said bus message be sent in the said internal memory with said first descriptor in the corresponding said current message buffer zone of physical address; The virtual address of the said current message buffer zone that reads according to the last message buffer before said current message buffer zone for said central processing unit reads the message in the said current message buffer zone.
9. a NIC is characterized in that, comprises arbitrary described message receiver module like claim 5-8.
10. a message receiving system is characterized in that, comprises NIC as claimed in claim 9, internal memory and central processing unit.
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