CN102739262B - Satellite communication gateway station signal demodulation processing board based on a CPCI (Compact Peripheral Component Interconnect) interface - Google Patents
Satellite communication gateway station signal demodulation processing board based on a CPCI (Compact Peripheral Component Interconnect) interface Download PDFInfo
- Publication number
- CN102739262B CN102739262B CN201210192191.7A CN201210192191A CN102739262B CN 102739262 B CN102739262 B CN 102739262B CN 201210192191 A CN201210192191 A CN 201210192191A CN 102739262 B CN102739262 B CN 102739262B
- Authority
- CN
- China
- Prior art keywords
- module
- signal
- fpga
- down converter
- digital down
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Landscapes
- Radio Relay Systems (AREA)
Abstract
The invention discloses a satellite communication gateway station signal demodulation processing board based on a CPCI (Compact Peripheral Component Interconnect) interface. The signal demodulation processing board comprises a single-path intermediate frequency signal receiving module, wherein the single-path intermediate frequency signal receiving module is connected with an A/D (Analog/Digital) conversion module; the A/D conversion module is connected with a DDC (Digital Down Converter) module; the DDC module is connected with an FPGA (Field Programmable Gate Array) module; and the FPGA module is connected with a DSP (Digital Signal Processing) module and a CPCI interface module. According to the satellite communication gateway station signal demodulation processing board based on the CPCI interface provided by the invention, the analog signal receiving and digital signal transmission are integrated, the independent A/D conversion module and the digital down converter are adopted, the intermediate frequency signal in the single-path satellite mobile communication can be processed, and the practicality is stronger.
Description
Technical field
The present invention relates to signal process field, particularly a kind of satellite communication gateway station signal demodulation process plate based on CPCI interface.
Background technology
In means of communication more and more abundanter today, satellite mobile communication remain a kind of effectively, communication mode reliably.Satellite mobile communication be exactly between the radio communication station (comprising in ground and lower atmosphere layer) on the earth, utilize satellite as in the communication then carried out.Satellite communication has advantages of that at aspects such as constructing communication network, network securitys it is special: (1) communication range is large, distance, as long as in the scope that the electric wave of satellite launch covers, between any 2, can communicate, user can move freely in the coverage of satellite beams; (2) reliability is high, is not subject to the impact of Land disaster; (3) open circuit speed fast, as long as earth gateway station circuit is set, can open; (4) can receive in many places, realize broadcast, multiple access communication simultaneously; (5) satellite mobile communication system can provide speech, telegram, data, has wide range of applications, and is applicable to commercial communication, is also applicable to military communication; Be applicable to home communications, also can be used for international communication.Based on These characteristics, satellite mobile communication has become an important development direction of communication service, is also become to an important trend of communication service development a very long time.
Satellite communication gateway station signal demodulation process plate is the important component part of satellite mobile communication system, and satellite communication gateway station signal demodulation process plate carries out demodulation, processing to the intermediate-freuqncy signal of satellite launch, then output.Development along with satellite communication, the signal demodulation process information of gateway station improves constantly, image, voice-and-data information constantly improve, need image, voice-and-data information that gateway station signal demodulation process plate is processed also constantly to increase, developing station, high performance pass signal demodulation process plate has become problem demanding prompt solution.
Summary of the invention
The object of the present invention is to provide a kind of satellite communication gateway station signal demodulation process plate based on CPCI interface, this signal demodulation process plate adopts independently A/D modular converter and DDC digital down converter module, can process the intermediate-freuqncy signal of single channel satellite mobile communication.
In order to realize foregoing invention object, the invention provides following technical scheme:
Satellite communication gateway station signal demodulation process plate based on CPCI interface, this signal demodulation process plate comprises single channel intermediate-freuqncy signal receiver module, for receiving single channel analog intermediate frequency signal;
With the A/D modular converter that described single channel intermediate-freuqncy signal receiver module is connected, described A/D modular converter has been used for the digital translation of analog intermediate frequency signal;
The DDC digital down converter module being connected with described A/D modular converter, described DDC digital down converter module is for filtering, signal adjustment and down-converted;
With the FPGA module that described DDC digital down converter module is connected, described FPGA module has been used for format conversion, semi-band filtering, demodulation, the decoding function of digital signal;
The DSP module and the CPCI interface module that are connected with described FPGA module respectively, described DSP module has been used for computing, the analysis of digital signal, and signal is configured to computing, digital demodulation processing, and CPCI interface module is for output information;
Described A/D modular converter is connected with DDC digital down converter module in direct-current coupling mode, described DDC digital down converter module is connected by input control, output signal, control signal with FPGA module, and described FPGA module is connected with DSP module with multi-channel synchronous serial port form by direct-current coupling mode.
Further, the input clock of described A/D modular converter is provided by connector by external clock.
Further, described FPGA module is also connected with FIFO, and described FIFO is for data cached.
compared with prior art, beneficial effect of the present invention:
1, the satellite communication gateway station signal demodulation process plate based on CPCI interface of the present invention, that an integrated simulation signal receives the integrated treatment plate that is sent as one with digital signal, this signal demodulation process plate has adopted independently A/D modular converter and DDC digital down converter module, can process the intermediate-freuqncy signal of single channel satellite mobile communication.
2, CPCI(Compact Peripheral Component Interconnect) there is high opening, high reliability, modularization, easy use, easy care, have higher bandwidth, there is good compatibility.The satellite communication gateway station signal demodulation process plate that the present invention is based on CPCI interface adopts CPCI interface, and each functional module is extracted or inserted to signal demodulation process plate, the in the situation that of not power-off,, and signal demodulation process plate will continue normal work.
Accompanying drawing explanation:
The transmission of Fig. 1 satellite communication system signal, process flow block diagram;
Fig. 2 signal demodulation process of the present invention sheet frame figure;
Fig. 3 single channel intermediate-freuqncy signal receiver module theory diagram;
Fig. 4 DDC digital down converter module and FPGA module catenation principle block diagram;
Fig. 5 FPGA module and DSP module catenation principle block diagram;
Fig. 6 A/D modular converter and FPGA module catenation principle block diagram;
Fig. 7 FPGA module and CPCI interface catenation principle block diagram.
Embodiment
Below in conjunction with test example and embodiment, the present invention is described in further detail.But this should be interpreted as to the scope of the above-mentioned theme of the present invention only limits to following embodiment, all technology realizing based on content of the present invention all belong to scope of the present invention.
As shown in Figure 1, satellite sends signal, ground-plane antenna by this signal through downlink transmission to earth station; Earth station transfers to low noise amplifier module by this small-signal receiving, to guarantee to receive the quality of signal; This signal through amplifying carries out frequency translation through low-converter again, signal is amplified again to the intermediate-freuqncy signal of output 70MHz; This intermediate-freuqncy signal of further amplifying obtains corresponding information after demodulator signal-processing board carries out demodulation, coding, and exports this information.
As shown in Figure 2, the satellite communication gateway station signal demodulation process plate based on CPCI interface that the present embodiment is enumerated comprises single channel intermediate-freuqncy signal receiver module, A/D modular converter, DDC digital down converter module, FPGA module, DSP module and CPCI interface module.Wherein, described A/D modular converter is connected with DDC digital down converter module in direct-current coupling mode, described DDC digital down converter module is connected with FPGA module by signal, described FPGA module is connected with DSP module with multi-channel synchronous serial port form by direct-current coupling mode, and FPGA module is connected with CPCI interface module by interface circuit.
In the present embodiment, A/D modular converter adopts the A/D6645 of ADI company as analog sampling chip, DDC digital down converter adopts the ISL5416 of InterSil company, FPGA module adopts the integrated programmable logic chip XC5VLX330T of XILINX company, DSP module is selected the TMS320C6455 of TI company, switching network by FPGA module and DSP module makes data-signal and global network carry out synchronous exchange, and CPCI interface adopts the PCI9054 device that uses programmable logic device.
The workflow that the present invention is based on the satellite communication gateway station signal demodulation process plate of CPCI interface is: single channel intermediate-freuqncy signal receiver module transfers to A/D modular converter by the analog intermediate frequency signal of reception, A/D modular converter transfers to DDC digital down converter module after this analog intermediate frequency signal is converted to digital signal, DDC digital down converter module is carried out filtering to this digital signal, signal is adjusted and down-converted, then transfer to FPGA module, FPGA module is carried out format conversion to the digital signal through down-converted, semi-band filtering, demodulation, decoding, then transfer to DSP module, DSP module completes the computing of this digital signal, analyze, be configured computing, digital demodulation is processed, signal after processing is back to FPGA module again, signal after this processing is exported by CPCI interface after FPGA module filtered, CPCI interface is connected to computer and disk array, this information exchange is crossed RAID RAID card and is stored in computer disk array, facilitate researcher's research.
Respectively form module and each module annexation that the present invention is based on the satellite communication gateway station signal demodulation process plate of CPCI interface specifically describe as follows:
With reference to figure 3, single channel intermediate-freuqncy signal receiver module comprises tuner, and analog intermediate frequency signal is received by tuner, then after impedance transformation, transfers to A/D modular converter.The input clock of A/D modular converter is provided by connector by outside 10MHz clock, and A/D modular converter sampling clock requires quality high, and phase noise is low, if clock signal shake is larger, signal to noise ratio easily worsens, and is difficult to guarantee the precision of effective sampling resolution.For Optimal performance, the input of the clock of A/D modular converter adopts the clock input of difference low jitter, and input clock is treated to PECL(Positive Emitter Coupled Logic) signal, by being ac-coupled to A/D modular converter.
The output level of A/D modular converter, DDC digital down converter module is 3.3V, adopts direct-current coupling mode to connect.A/D modular converter outputs data bits width is 14, and DDC digital down converter module data input bit width is 17.A/D modular converter is output as TWOS complement code form, and due to data bit width misalignment, so A/D modular converter is alignd according to highest order with the data of DDC digital down converter module, the unnecessary low level of DDC digital down converter module is drop-down.
With reference to figure 4, the interconnection of DDC digital down converter module and FPGA module comprises input control interconnection, output signal interconnection, the control signal interconnection of DDC digital down converter module.
DDC digital down converter module comprises that four inputs enable pin and FPGA modules carry out input control interconnection, and every DDC digital down converter module takies 4 3.3V I/O pins of FPGA module altogether.
In the present embodiment, the output signal of DDC digital down converter module comprises A, B, C, tetra-output data channel of D, and each output data channel divided data enables, frame synchronization enables, output enable three classes.The output signal of DDC digital down converter module also provides a road VGA/ decay to control output channel and two output clock pins, and the signal that DDC digital down converter module is connected in FPGA module comprises A, B, C, tetra-output data channel of D and two output clock pins.
The control signal interconnection of DDC digital down converter module and FPGA module comprises that hardware controls and Microprocessor Interface control two classes.Hardware controls has synchronous input, synchronous output, the three kinds of signals that reset, and takies altogether 4 3.3V I/O pins of FPGA module.Microprocessor Interface is controlled 23 3.3V I/O pins that take altogether FPGA module.
With reference to figure 5, DSP module externally has 2 EMIF bus interface, is respectively the EMIFA of 64 bit and the EMIFB of 16 bit.EMIFA interface possesses the function with 8 bit, 16 bit, 32 bit, 64 bit system interfaces, and in the present embodiment, the EMIFA of the data channel of FPGA module and DSP module by DSP module interconnects in the mode of direct-current coupling, realizes seamless link.
DSP module controls and status signal have reset (RESET) signal, non-maskable interrupts (NMI) signal, reset mode output (RESETSTAT) signal, electrification reset (POR) signal, GPIO[3:0] signal, TIMER1 signal, TIMER2 signal, IIC signal.The AECLKIN signal pins of DSP module and AECLKOUT signal pins are connected to the clock pin of FPGA module.
The two-way McBSP of DSP module is with form and the FPGA module interconnects of multi-channel synchronous serial ports.
With reference to figure 6, the interconnection between A/D modular converter and FPGA module need to be passed backboard connector, and A/D modular converter is connected by two pins of OVR and RDY with condition line with the control between FPGA module.
With reference to figure 7, PCI9054 interface chip completes communicating by letter of FPGA module and host computer, and local bus is transformed on cpci bus fast, and supports DMA transmission mode.For meeting the Real-time Collection requirement of great amount of images, FPGA is connected with FIFO(first in first out data buffer), jumbo FIFO realizes data buffering, realize the continuous acquisition transmission of high flow capacity, high-speed view data, also for different picture formats and different transmission meanss, data acquisition is adjusted, application VerilogHDL hardware program language is realized the programming conversion of picture format.FPGA has realized the logic coupling of bus clock and external timing signal, and the sequential logic of FIFO operation is controlled.
Satellite communication gateway station signal demodulation process plate based on CPCI interface, integrated simulation signal receives with digital signal and is sent as one, adopt independently A/D modular converter and digital down converter passage, can process the intermediate-freuqncy signal of single channel satellite mobile communication, realize Viterbi code decoding process, met higher demand.
Claims (1)
1. the satellite communication gateway station signal demodulation process plate based on CPCI interface, is characterized in that, this signal demodulation process plate comprises:
Single channel intermediate-freuqncy signal receiver module, for receiving single channel analog intermediate frequency signal;
With the A/D modular converter that described single channel intermediate-freuqncy signal receiver module is connected, described A/D modular converter has been used for the digital translation of analog intermediate frequency signal;
The DDC digital down converter module being connected with described A/D modular converter, described DDC digital down converter module is for filtering, signal adjustment and down-converted;
With the FPGA module that described DDC digital down converter module is connected, described FPGA module has been used for format conversion, semi-band filtering, demodulation, the decoding function of digital signal;
The DSP module and the CPCI interface module that are connected with described FPGA module respectively, described DSP module has been used for computing, the analysis of digital signal, and signal is configured to computing, digital demodulation processing, and CPCI interface module is for output information;
Described A/D modular converter is connected with DDC digital down converter module in direct-current coupling mode, described DDC digital down converter module is connected by input control, output signal, control signal with FPGA module, and described FPGA module is connected with DSP module with multi-channel synchronous serial port form by direct-current coupling mode;
The input clock of described A/D modular converter is provided by connector by external clock;
Described FPGA module is also connected with FIFO, and described FIFO is for data cached;
Described A/D modular converter adopts the A/D6645 of ADI company as analog sampling chip, described DDC digital down converter adopts the ISL5416 of InterSil company, described FPGA module adopts the integrated programmable logic chip XC5VLX330T of XILINX company, described DSP module adopts the TMS320C6455 of TI company, switching network by FPGA module and DSP module makes data-signal and global network carry out synchronous exchange, and described CPCI interface module adopts programmable logic device PCI9054;
Single channel intermediate-freuqncy signal receiver module comprises tuner, analog intermediate frequency signal is received by tuner, after impedance transformation, transfer to again A/D modular converter, the input clock of A/D modular converter is provided by connector by outside 10MHz clock, the clock input of A/D modular converter adopts the clock input of difference low jitter, input clock is treated to PECL signal, by being ac-coupled to A/D modular converter;
The output level of A/D modular converter, DDC digital down converter module is 3.3V, adopt direct-current coupling mode to connect, A/D modular converter outputs data bits width is 14, DDC digital down converter module data input bit width is 17, A/D modular converter is output as TWOS complement code form, A/D modular converter is alignd according to highest order with the data of DDC digital down converter module, and the unnecessary low level of DDC digital down converter module is drop-down;
The interconnection of DDC digital down converter module and FPGA module comprises input control interconnection, output signal interconnection, the control signal interconnection of DDC digital down converter module;
DDC digital down converter module comprises that four inputs enable pin and FPGA modules carry out input control interconnection, and every DDC digital down converter module takies 4 3.3V I/O pins of FPGA module altogether;
The output signal of DDC digital down converter module comprises A, B, C, tetra-output data channel of D, each output data channel divided data enables, frame synchronization enables, output enable three classes, the output signal of DDC digital down converter module also provides a road VGA/ decay to control output channel and two output clock pins, and the signal that DDC digital down converter module is connected in FPGA module comprises A, B, C, tetra-output data channel of D and two output clock pins;
The control signal interconnection of DDC digital down converter module and FPGA module comprises that hardware controls and Microprocessor Interface control two classes, hardware controls has synchronous input, synchronous output, three kinds of signals reset, take altogether 4 3.3V I/O pins of FPGA module, Microprocessor Interface is controlled 23 3.3V I/O pins that take altogether FPGA module;
DSP module externally has 2 EMIF bus interface, respectively the EMIFA of 64bit and the EMIFB of 16bit, EMIFA interface possesses the function with 8bit, 16bit, 32bit, 64bit system interface, the EMIFA of the data channel of FPGA module and DSP module by DSP module interconnects in the mode of direct-current coupling, realizes seamless link;
DSP module controls and status signal have reset RESET signal, non-maskable interrupts NMI signal, reset mode output RESETSTAT signal, electrification reset por signal, GPIO[3:0] signal, TIMER1 signal, TIMER2 signal, IIC signal, the AECLKIN signal pins of DSP module and AECLKOUT signal pins are connected to the clock pin of FPGA module;
The two-way McBSP of DSP module is with form and the FPGA module interconnects of multi-channel synchronous serial ports;
Interconnection between A/D modular converter and FPGA module is through backboard connector, and A/D modular converter is connected by two pins of OVR and RDY with condition line with the control between FPGA module;
PCI9054 interface chip completes communicating by letter of FPGA module and host computer, make local bus be transformed into fast on cpci bus, and support DMA transmission mode, FPGA is connected with FIFO, jumbo FIFO realizes data buffering, realize high flow capacity, the continuous acquisition transmission of high-speed view data, for different picture formats, and different transmission meanss is adjusted data acquisition, application VerilogHDL hardware program language is realized the programming conversion of picture format, FPGA realizes the logic coupling of bus clock and external timing signal, and the sequential logic of FIFO operation is controlled,
The workflow of the satellite communication gateway station signal demodulation process plate of described CPCI interface is: single channel intermediate-freuqncy signal receiver module transfers to A/D modular converter by the analog intermediate frequency signal of reception, A/D modular converter transfers to DDC digital down converter module after this analog intermediate frequency signal is converted to digital signal, DDC digital down converter module is carried out filtering to this digital signal, signal is adjusted and down-converted, then transfer to FPGA module, FPGA module is carried out format conversion to the digital signal through down-converted, semi-band filtering, demodulation, decoding, then transfer to DSP module, DSP module completes the computing of this digital signal, analyze, be configured computing, digital demodulation is processed, signal after processing is back to FPGA module again, signal after this processing is exported by CPCI interface module after FPGA module filtered, CPCI interface module is connected to computer and disk array, the information exchange of this output is crossed RAID RAID card and is stored in disk array.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201210192191.7A CN102739262B (en) | 2012-06-12 | 2012-06-12 | Satellite communication gateway station signal demodulation processing board based on a CPCI (Compact Peripheral Component Interconnect) interface |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201210192191.7A CN102739262B (en) | 2012-06-12 | 2012-06-12 | Satellite communication gateway station signal demodulation processing board based on a CPCI (Compact Peripheral Component Interconnect) interface |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN102739262A CN102739262A (en) | 2012-10-17 |
| CN102739262B true CN102739262B (en) | 2014-09-03 |
Family
ID=46994139
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201210192191.7A Expired - Fee Related CN102739262B (en) | 2012-06-12 | 2012-06-12 | Satellite communication gateway station signal demodulation processing board based on a CPCI (Compact Peripheral Component Interconnect) interface |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN102739262B (en) |
Families Citing this family (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106209148B (en) * | 2016-07-01 | 2018-08-31 | 中国电子科技集团公司第十研究所 | Multifunctional radio-frequency module common port system |
| CN108123684B (en) * | 2017-12-19 | 2021-05-25 | 中国科学院深圳先进技术研究院 | Digital down-conversion processing method and device |
| CN111342884B (en) * | 2020-02-24 | 2022-04-22 | 北京华力创通科技股份有限公司 | Method, device and system for analyzing demodulation performance of gateway station and storage medium |
| CN112986927A (en) * | 2021-02-06 | 2021-06-18 | 江苏信息职业技术学院 | Direct sampling module and direct sampling method for broadband radio frequency signals |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN201204577Y (en) * | 2008-06-03 | 2009-03-04 | 中国电子科技集团公司第三十研究所 | Universal board for processing wideband high speed digital signal base on multiple DSPs |
| CN101820699A (en) * | 2009-02-27 | 2010-09-01 | 京信通信系统（中国）有限公司 | Wideband signal digital frequency selecting system with self-adaptive bandwidth adjustment and signal processing method |
| CN102170302A (en) * | 2011-03-23 | 2011-08-31 | 西安电子科技大学 | Anti-interference system-on-chip and method of intelligent antenna based on FPGA (Field Programmable Gate Array) |
| CN201966896U (en) * | 2011-03-25 | 2011-09-07 | 兰州众仕通电子科技有限公司 | Wireless wideband multi-channel signal processing board |
| CN102223325A (en) * | 2011-06-17 | 2011-10-19 | 奥维通信股份有限公司 | System and method for locking wideband code division multiple access (WCDMA) base station based on Altera |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH11331125A (en) * | 1997-12-04 | 1999-11-30 | Sanyo Electric Co Ltd | Radio receiving system |
-
2012
- 2012-06-12 CN CN201210192191.7A patent/CN102739262B/en not_active Expired - Fee Related
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN201204577Y (en) * | 2008-06-03 | 2009-03-04 | 中国电子科技集团公司第三十研究所 | Universal board for processing wideband high speed digital signal base on multiple DSPs |
| CN101820699A (en) * | 2009-02-27 | 2010-09-01 | 京信通信系统（中国）有限公司 | Wideband signal digital frequency selecting system with self-adaptive bandwidth adjustment and signal processing method |
| CN102170302A (en) * | 2011-03-23 | 2011-08-31 | 西安电子科技大学 | Anti-interference system-on-chip and method of intelligent antenna based on FPGA (Field Programmable Gate Array) |
| CN201966896U (en) * | 2011-03-25 | 2011-09-07 | 兰州众仕通电子科技有限公司 | Wireless wideband multi-channel signal processing board |
| CN102223325A (en) * | 2011-06-17 | 2011-10-19 | 奥维通信股份有限公司 | System and method for locking wideband code division multiple access (WCDMA) base station based on Altera |
Also Published As
| Publication number | Publication date |
|---|---|
| CN102739262A (en) | 2012-10-17 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN102694557A (en) | Multi-channel demodulation signal processing platform based on CPCI (compact programmable communication interface) | |
| CN102739262B (en) | Satellite communication gateway station signal demodulation processing board based on a CPCI (Compact Peripheral Component Interconnect) interface | |
| CN102624439B (en) | Integrated detection equipment for pico-satellite | |
| CN103353725A (en) | PCI interface protocol based array expandable data collection system realized by adopting FPGA (field programmable gate array) | |
| CN107864023B (en) | Short-wave ultrashort-wave channel simulation device and simulation method | |
| CN103678212A (en) | Universal interface detection device based on VPX framework | |
| CN106790897A (en) | For the verification experimental verification platform of millimeter wave radio communication | |
| CN202083795U (en) | Radar data acquisition card based on CPCI (compact peripheral component interconnect) | |
| CN103856257A (en) | Satellite communication gateway station signal demodulation processing board | |
| CN202931321U (en) | Satellite communication gateway station signal demodulation processing plate based on PCI-E interface | |
| CN112416831A (en) | High-speed signal acquisition, storage and processing system | |
| CN201966896U (en) | Wireless wideband multi-channel signal processing board | |
| CN117353758A (en) | High-performance SDR platform based on domestic ware component | |
| CN114897171B (en) | Superconducting quantum bit low-delay feedback control circuit and superconducting quantum feedback control method | |
| CN102739263B (en) | Satellite communication demodulator signal processing platform based on 32-bit PCI (Peripheral Component Interconnect) interface | |
| CN216490493U (en) | Satellite measurement and control satellite affair integrated system | |
| CN203014851U (en) | Multi-interface self-adapting radar video digitization processing device | |
| CN115509970A (en) | FPGA multichannel high-speed signal acquisition and processing module | |
| CN114896194A (en) | Multi-channel signal acquisition processing board based on FPGA and DSP | |
| CN202957821U (en) | Demodulated signal processing platform based on compact peripheral component interconnect (PCI) interface | |
| CN202940800U (en) | High-orbit remote-sensing satellite-demodulation signal processing platform | |
| CN212211006U (en) | Satellite electronic system of micro/nano satellite | |
| CN106533533A (en) | Signal demodulation processing plate for satellite communication gateway station | |
| CN202940926U (en) | VPX interface-based mobile-communication gateway-station video-signal processing platform | |
| CN202750076U (en) | Software radio front-end system apparatus |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CF01 | Termination of patent right due to non-payment of annual fee | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20140903 Termination date: 20160612 |