CN102710289A - Multi-user time hopping-pulse position modulation ultra-wideband receiver demodulator - Google Patents
Multi-user time hopping-pulse position modulation ultra-wideband receiver demodulator Download PDFInfo
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Abstract
The invention discloses a multi-user time hopping-pulse position modulation ultra-wideband receiver demodulator. A local encryption module generates encryption signals required in the demodulator. A multi-user module receives the signals of the local encryption module and provides local template signals of a multi-user output. A clock tree receives system clock signals from a clock and data recovery circuit and distributes the signals to a clock end of each sub-module of the demodulator. A template generates pulse position modulation (PPM) signals which are received by a comparison module and come from a radio-frequency front end, and the PPM signals are compared with the local template signals. A synchronous counting and out-of-step reset module receives a comparison result which is produced by the template and acquired in the comparison module, carries out synchronization judgment of the signals and finishes out-of-step reset operation. A judgment output module receives data which are produced by the template and acquired in the comparison module and enabling signals from the synchronous counting and out-of-step reset module, and transmits decoded data signals. According to the demodulator, the area of a whole chip is reduced and a time hopping-ultra-wideband (TH-UWB) multi-user decoding function is realized at the same time by simple template comparison and synchronization control.
Description
Technical field
The present invention relates to wireless communication technology field, be specifically related to a kind of multi-user pulse position modulation ultra wideband receiver demodulator when jumping.
Background technology
Ultra broadband (UWB) is a kind of extremely competitive communication mode in the high-speed radiocommunication, and it can realize carrier wave or carrierfree communication, and it is a kind of superfast short-distance wireless access technology simultaneously.Ultra broadband can be on the frequency spectrum of broad the lower powered signal of carry electrode; Realize the data transmission rate of the hundreds of megabits of per second in can the scope about 10m, many advantages such as have strong anti-interference performance, transmission rate is high, very bandwidth is wide, consumed power is little, good confidentiality, transmitted power are little.Because the frequency spectrum of ultra-broadband signal is by the waveform decision of modulation system and signal; Therefore extremely important in the design that is chosen in radio ultra wide band system of ultra-wideband waveform and modulation technique.In practical application, need take all factors into consideration the use occasion and the specification requirement of system and choose suitable waveform and modulation system.In multi-user's system; The modulation system of ultra broadband is the combination of multiple access modulation and information modulation; As can be through different users is distributed different time-hopping sequences, pulse position modulation ultra broadband when avoiding the jumping of the interference between the different user in time (the TH-pulse position modulation-UWB).
The ultra-broadband signal transmission is owing to receive the influence of factors such as large scale path loss, shadow effect, small scale multipath fading; Therefore there is serious distortion in the signal that arrives receiver, and synchronous signal also possibly receive the influence of multiple access interference, narrow band interference and background noise.Generally speaking, ultra wideband receiver mainly is made up of demodulator and detector.The function of demodulator is to become N dimensional vector r with accepting waveform transformation, and N is for sending the dimension of waveform.The function of detector is to judge it is the transmission of which waveform according to r.Demodulator often adopts following two kinds of implementation methods at present as the critical component of ultra wideband receiver, and one is based on the application of signal correction, and is based on the application of matched filter.Yet all there are the complicated characteristics of circuit structure in above-mentioned two kinds of demodulators that method realized.
Summary of the invention
Technical problem to be solved by this invention provides a kind of multi-user pulse position modulation ultra wideband receiver demodulator when jumping; This demodulator can adopt standard digital CMOS technology to realize; Circuit structure is succinct, can under the prerequisite that does not increase circuit power consumption and complexity, realize multi-user's function simultaneously.
For addressing the above problem, the present invention realizes through following scheme:
Pulse position modulation ultra wideband receiver demodulator when the multi-user jumps is characterized in that: mainly by clock trees module, multi-user's module, local encryption module, 2 template generations and comparison modules, count the step-out reseting module synchronously and the judgement output module is formed.The system clock input of clock trees module is accepted the system clock that receiver clock and data recovery circuit are sent here, and it is decomposed into this multichannel output of first clock, second clock, the 3rd clock and the 4th clock; First output terminal of clock of clock trees module is connected to first and second templates and produces with first input end of clock of first input end of clock of comparison module, judgement output module, counts first input end of clock of step-out reseting module and first input end of clock of local encryption module synchronously; The second clock output of clock trees module is connected to the second clock input of generation of first and second templates and comparison module; The 3rd output terminal of clock of clock trees module is connected to the 3rd input end of clock of judgement output module; The 4th output terminal of clock of clock trees module is connected to the 4th input end of clock of judgement output template.The first input end of multi-user's module is connected outside next selecting side, numerical control multipurpose family respectively with second input; The local pseudo noise code input of multi-user's module receives the encryption output signal from local encryption module; Multi-user's output of multi-user's module is connected to multi-user's input of generation of first and second templates and comparison module.Data input pin after the comparison of local encryption module is connected to the data output end after the comparison of synchronous counting step-out reseting module.First template produces the pulse position modulation input signal that receives the outside with system's pulse position modulation input of comparison module; First template produces and the pattern control input end of comparison module is connected to power supply; First template produces this signal input part of Q that is connected to the judgement output module with this signal output part of Q that compares template; First template produces the Q external signal input that is connected to the judgement output module with the Q external signal output that compares template; First template produces the second pulse position modulation output after the comparison with template relatively and is connected to the second pulse position modulation input after the comparison of synchronous counting step-out reseting module.Second template produces the pulse position modulation input signal that receives the outside with system's pulse position modulation input of comparison module; Second template produces and the pattern control input end of comparison module is connected to ground; Second template produces the first pulse position modulation output after the comparison with template relatively and is connected to the first pulse position modulation input after the comparison of synchronous counting step-out reseting module.Count the input that enables that enables input and judgement output module that output is connected to generation of first and second templates and comparison module that enables of step-out reseting module synchronously; External reset signal is connected to the RESET input of synchronous counting step-out reseting module.The data output end of judgement output template is the later data output end of demodulator conclusive judgement; The data clock output of judgement output template is the later data clock output of demodulator conclusive judgement.
In the present invention, said multi-user's module comprises first AND circuit and first OR circuit; First AND circuit is sent in the local pseudo noise code and the first multi-user selecting side from local encryption module, and the output of first AND circuit and the second multi-user selecting side are sent into first OR circuit together, and the output of first OR circuit is multi-user's output.
In the present invention, said local encryption module comprises second AND circuit, 8 frequency dividing circuits and local pseudo noise code generation circuit; First clock signal from data-signal after the comparison of synchronous counting step-out reseting module and the output of clock trees module is sent into second AND circuit; The output of second AND circuit is through 8 frequency dividing circuits; Deliver to local pseudo noise code again and produce circuit, the output that last local pseudo noise code produces circuit is to encrypt output.
In the present invention, said first template generation and comparison module and second template produce with each self-contained half adder circuit of comparison module, pulse position modulation and produce circuit, the first d type flip flop circuit, 2 serial-parallel conversion circuits, first buffer circuits and comparator circuits; Multi-user's input signal is sent into half adder circuit with mode control signal, and half adder circuit output is delivered to pulse position modulation and produced circuit; Pulse position modulation produces first clock of the clock of circuit from the output of clock trees module; Pulse position modulation produces the signal of circuit output and delivers to the first d type flip flop circuit, and the clock of the first d type flip flop circuit is from the second clock of clock trees module output; First serial-parallel conversion circuit is sent in the output of the first d type flip flop circuit, and the clock of first serial-parallel conversion circuit is from first clock of clock trees module output; System's pulse position modulation input signal is sent into second serial-parallel conversion circuit, and the clock of second serial-parallel conversion circuit is from output first clock of clock trees module; First buffer circuits is all delivered in 4 tunnel outputs separately of first and second serial-parallel conversion circuits, and the enable signal of first buffer circuits is from the Enable Pin of synchronous counting step-out reseting module; Comparator circuit is delivered in 24 tunnel outputs of first buffer circuits, and the clock of comparator circuit is from first clock of clock trees module output; Comparator circuit is output as the first or second pulse position modulation output after the comparison, and a road in 4 tunnel outputs of first serial-parallel conversion circuit are this output of Q, and a road in 4 tunnel outputs of second serial-parallel conversion circuit are the outer output of Q.
In the present invention, said synchronous counting step-out reseting module comprises second OR circuit, counter circuit and the 3rd AND circuit; First and second pulse position modulation signals were sent into second OR circuit after first and second templates produced the comparison of exporting with comparison module; Data-signal after the comparison of second OR circuit output offers local encryption module, and sends into counter circuit simultaneously; The clock of counter circuit is from first clock of clock trees module output, and the input of the 3rd AND circuit is delivered in the output of counter circuit, has reset terminal on the 3rd AND circuit, and the 3rd AND circuit is output as and enables output.
In the present invention, said judgement output template comprises 3 d type flip flop circuit, same OR circuit, the 4th AND circuit, integrating circuit and second buffer circuits; Second and the clock of 3d flip-flop circuit all from the 3rd clock signal of clock trees module output; The data of the second d type flip flop circuit are from the Q external signal of first template generation with comparison module, and the data of 3d flip-flop circuit are from first template generation this signal of Q with comparison module; Second and the output of 3d flip-flop circuit send into same OR circuit together, with the clock of OR circuit first clock signal, send into the 4th AND circuit with the output of OR circuit from the output of clock trees module; Another signal of the 4th AND circuit is from the enabling of synchronous counting step-out reseting module, and the output of the 4th AND circuit is sent into the four d flip-flop circuit after through the integrator circuit integration; All from the 4th clock of clock trees module output, the four d flip-flop circuit is output as data output end to the clock of the four d flip-flop circuit and second buffer circuits, and second buffer circuits is output as the data clock output.
Compared with prior art, the present invention has following characteristics:
Pulse position modulation ultra broadband (TH-PPM-UWB) digital receiver demodulator circuit structure when 1, having proposed a kind of new multi-user and jump; This circuit can adopt standard digital CMOS technology to realize; Circuit structure is succinct, under the prerequisite that does not increase circuit power consumption and complexity, has realized multi-user's function;
2, realize the data decode function of multi-user UWB system, and system is simple, saves the area of entire circuit;
3, have synchronous searching and loss of synchronism protection function, improved the stability of demodulator and the reliability of decoded data;
4, can separate the signal of the UWB system of code encryption;
5, be applicable to the short-distance wireless high speed data transmission system.
Description of drawings
Fig. 1 is the structural representation of TH-PPM-UWB receiver demodulator.
Fig. 2 is that the multi-user of demodulator selects module diagram.
Fig. 3 is the local encryption module sketch map of demodulator.
Fig. 4 is that the template of demodulator produces and the comparison module sketch map.
Fig. 5 is the synchronous counting and the step-out reseting module sketch map of demodulator.
Fig. 6 is the judgement output module sketch map of demodulator.
Fig. 7 is the input/output signal sequential sketch map of demodulator.
Embodiment
Referring to Fig. 1; Pulse position modulation ultra wideband receiver demodulator when a kind of multi-user jumps, mainly by clock trees module, multi-user's module, local encryption module, 2 template generations and comparison modules, count the step-out reseting module synchronously and the judgement output module is formed.Local encryption module is used for producing the required coded signal of TH-PPM-UWB receiver demodulator, and multi-user's module receives the signal from local encryption module, the local template signal that provides the multi-user to export.Clock trees receives the clock signal of system of self-clock and data recovery circuit, and is assigned to the clock end of each sub-module of demodulator.Template produces with comparison module and receives the PPM signal from radio-frequency front-end, and compares with local template signal.Counting step-out reseting module receives the comparative result of template generation and comparison module and carries out the synchronous judgement of signal synchronously, and accomplishes the step-out reset operation.The judgement output module receives self-template to produce and the data of comparison module and the enable signal that resets from synchronous counting step-out, sees decoded data-signal off.The present invention has realized the function of TH-UWB multi-user's decoding through simple template comparison and Synchronization Control when saving the entire chip area.
The system clock input sysclk of clock trees module accepts the system clock that receiver clock and data recovery circuit are sent here, and it is decomposed into this multichannel output of the first clock clk0, second clock clk1, the 3rd clock clk2 and the 4th clock clk500; The first output terminal of clock clk0 of clock trees module is connected to first and second templates and produces with the first input end of clock clk0 of the first input end of clock clk0 of comparison module, judgement output module, counts first input end of clock clk0 of step-out reseting module and the first input end of clock clk0 of local encryption module synchronously; The second clock output clk1 of clock trees module is connected to the second clock input clk1 of generation of first and second templates and comparison module; The 3rd output terminal of clock clk2 of clock trees module is connected to the 3rd input end of clock clk2 of judgement output module; The 4th output terminal of clock clk500 of clock trees module is connected to the 4th input end of clock clk500 of judgement output template.The first input end A of multi-user's module is connected outside next selecting side, numerical control multipurpose family respectively with the second input B; The local PN sign indicating number of the local pseudo noise code input of multi-user's module receives the encryption output signal from local encryption module; Multi-user's output of multi-user's module is connected to multi-user's input of generation of first and second templates and comparison module.Data input pin Dcomp after the comparison of local encryption module is connected to the data output end Dcomp after the comparison of synchronous counting step-out reseting module.First template produces the pulse position modulation input signal that receives the outside with the pulse position modulation input PPMin of system of comparison module; First template produces and the pattern control input end modctrl of comparison module is connected to power supply Vdd; First template produces this signal input part of Q that is connected to the judgement output module with this signal output part of Q that compares template; First template produces the Q external signal input that is connected to the judgement output module with the Q external signal output that compares template; First template produce the second pulse position modulation output after the comparison with template relatively relatively back PPM1 be connected to after the comparison of synchronous counting step-out reseting module relatively back PPM1 of the second pulse position modulation input.Second template produces the pulse position modulation input signal that receives the outside with the pulse position modulation input PPMin of system of comparison module; Second template produces and the pattern control input end modctrl of comparison module is connected to ground Vss; Second template produce the first pulse position modulation output after the comparison with template relatively relatively back PPM0 be connected to after the comparison of synchronous counting step-out reseting module relatively back PPM0 of the first pulse position modulation input.Synchronously counting step-out reseting module enable output en be connected to first and second templates produce with comparison module enable input en and judgement output module enable input en; External reset signal Reset is connected to the RESET input Reset of synchronous counting step-out reseting module.The data output end Dataout of judgement output template is the later data output end of demodulator conclusive judgement; The data clock output clkout of judgement output template is the later data clock output of demodulator conclusive judgement.
In order to adopt standard digital CMOS technology to realize the present invention, the physical circuit of each module of the present invention is constructed as follows:
In the present invention, said multi-user's module comprises first AND circuit and first OR circuit; First AND circuit is sent in the local pseudo noise code and the first multi-user selecting side from local encryption module, and the output of first AND circuit and the second multi-user selecting side are sent into first OR circuit together, and the output of first OR circuit is multi-user's output.
In the present invention, said local encryption module comprises second AND circuit, 8 frequency dividing circuits and local pseudo noise code generation circuit; First clock signal from data-signal after the comparison of synchronous counting step-out reseting module and the output of clock trees module is sent into second AND circuit; The output of second AND circuit is through 8 frequency dividing circuits; Deliver to local pseudo noise code again and produce circuit, the output that last local pseudo noise code produces circuit is to encrypt output.
In the present invention, said first template generation and comparison module and second template produce with each self-contained half adder circuit of comparison module, pulse position modulation and produce circuit, the first d type flip flop circuit, 2 serial-parallel conversion circuits, first buffer circuits and comparator circuits; Multi-user's input signal is sent into half adder circuit with mode control signal, and half adder circuit output is delivered to pulse position modulation and produced circuit; Pulse position modulation produces first clock of the clock of circuit from the output of clock trees module; Pulse position modulation produces the signal of circuit output and delivers to the first d type flip flop circuit, and the clock of the first d type flip flop circuit is from the second clock of clock trees module output; First serial-parallel conversion circuit is sent in the output of the first d type flip flop circuit, and the clock of first serial-parallel conversion circuit is from first clock of clock trees module output; System's pulse position modulation input signal is sent into second serial-parallel conversion circuit, and the clock of second serial-parallel conversion circuit is from output first clock of clock trees module; First buffer circuits is all delivered in 4 tunnel outputs separately of first and second serial-parallel conversion circuits, and the enable signal of first buffer circuits is from the Enable Pin of synchronous counting step-out reseting module; Comparator circuit is delivered in 24 tunnel outputs of first buffer circuits, and the clock of comparator circuit is from first clock of clock trees module output; Comparator circuit is output as the first or second pulse position modulation output after the comparison, and a road in 4 tunnel outputs of first serial-parallel conversion circuit are this output of Q, and a road in 4 tunnel outputs of second serial-parallel conversion circuit are the outer output of Q.
In the present invention, said synchronous counting step-out reseting module comprises second OR circuit, counter circuit and the 3rd AND circuit; First and second pulse position modulation signals were sent into second OR circuit after first and second templates produced the comparison of exporting with comparison module; Data-signal after the comparison of second OR circuit output offers local encryption module, and sends into counter circuit simultaneously; The clock of counter circuit is from first clock of clock trees module output, and the input of the 3rd AND circuit is delivered in the output of counter circuit, has reset terminal on the 3rd AND circuit, and the 3rd AND circuit is output as and enables output.
In the present invention, said judgement output template comprises 3 d type flip flop circuit, same OR circuit, the 4th AND circuit, integrating circuit and second buffer circuits; Second and the clock of 3d flip-flop circuit all from the 3rd clock signal of clock trees module output; The data of the second d type flip flop circuit are from the Q external signal of first template generation with comparison module, and the data of 3d flip-flop circuit are from first template generation this signal of Q with comparison module; Second and the output of 3d flip-flop circuit send into same OR circuit together, with the clock of OR circuit first clock signal, send into the 4th AND circuit with the output of OR circuit from the output of clock trees module; Another signal of the 4th AND circuit is from the enabling of synchronous counting step-out reseting module, and the output of the 4th AND circuit is sent into the four d flip-flop circuit after through the integrator circuit integration; All from the 4th clock of clock trees module output, the four d flip-flop circuit is output as data output end to the clock of the four d flip-flop circuit and second buffer circuits, and second buffer circuits is output as the data clock output.
Multi-user's input is the P-pulse modulation signal of sending into; Sending into first and second modules respectively produces and comparison module; First and second modules produce with comparison module and are respectively local PPM template signal; First module produces the pattern control termination power (high level Vdd) with comparison module; Second module produces the pattern control end ground connection (low level Vss) with comparison module, like this can be so that one the tunnel be used to produce the PPM signal of template for " 1 ", and another road is used to produce the PPM signal of template for " 0 ".When information data was " 0 " sign indicating number, what PPM template signal circuit was exported was the TH-PPM baseband signal that contains information code " 0 "; When information data was " 1 " sign indicating number, what PPM template signal circuit was exported was the TH-PPM baseband signal that contains information code " 1 ".Multi-user's module is passed through A, B termination high level, low level, and the various combination of PN pseudo random sequence is realized multi-user's selection function.First and second modules produce with the output of comparison module and all send into synchronous counting step-out reseting module.The function that synchronous counting step-out reseting module is mainly accomplished is for receiver synchronous searching and loss of synchronism protection function to be provided; Locked in order to prevent the long-time step-out of locking system; Counting step-out reseting module provides reset terminal specially synchronously; Make circuit under this extreme case, realize the synchronous searching once more and the loss of synchronism protection function of system through it.Template produce with comparison module with the comparison that is shifted of the PPM template signal of the TH-PPM signal that receives and the sign indicating number " 0 " or " 1 " that hides Info, the comparative result that will walk abreast then is sent to synchronous counting step-out reseting module.When the output signal voltage value of two templates generations and comparison module all is low level; Or the output signal of door is a low level; The control counter circuit begins counting; Set numerical value hour counter circuit output high level when count value reaches, the Enable Pin of control correlation detector circuit is opened, and two templates produce with comparison module restarts work.After the system synchronization, adjudicate, recover information signal through the judgement output module.The clock trees module is that each module of receiver provides system clock.The output signal of judgement output module is a high level, expression recovering information sign indicating number " 1 "; When integrator was output as low level, the output signal of decision device was a low level, expression recovering information sign indicating number " 0 ".The effect of d type flip flop circuit is that integrator output signal is carried out shaping.
Owing to be to have certain requirements to settling time and retention time in the digital circuit, so the present invention passes through the application to d type flip flop and inverter, realizes settling time and retention time requirement.If there is signal just might form instability in the edge variation of clock, this moment clock is carried out anti-phase and make the edge of clock move to the centre of the level of signal, can improve the stability of circuit thus, the shake of clock also there is good vulnerability to jamming.After the oversampling clock anti-phase, we not must be noted that the variation of the signal of wanting in order to avoid produce mistake.The effect of d type flip flop is to signal shaping to be prolonged the retention time of signal.Because d type flip flop is sequence circuit, the signal through its shaping has synchronous character, transmits according to clock fully.Inverter and d type flip flop combine and make circuit more stable.
What should explain at last is, technical scheme of the present invention is made amendment or replacement on an equal basis, and do not break away from the spirit and the scope of technical scheme of the present invention, and it all should be encompassed in the claim scope of the present invention.
Claims (6)
1. pulse position modulation ultra wideband receiver demodulator when the multi-user jumps is characterized in that: mainly by clock trees module, multi-user's module, local encryption module, 2 template generations and comparison modules, count the step-out reseting module synchronously and the judgement output module is formed;
The system clock input (sysclk) of clock trees module is accepted the system clock that receiver clock and data recovery circuit are sent here, and it is decomposed into first clock (clk0), second clock (clk1), this multichannel output of the 3rd clock (clk2) and the 4th clock (clk500); First output terminal of clock (clk0) of clock trees module is connected to first and second templates and produces with first input end of clock (clk0) of first input end of clock (clk0) of comparison module, judgement output module, counts first input end of clock (clk0) of step-out reseting module and first input end of clock (clk0) of local encryption module synchronously; The second clock output (clk1) of clock trees module is connected to the second clock input (clk1) of generation of first and second templates and comparison module; The 3rd output terminal of clock (clk2) of clock trees module is connected to the 3rd input end of clock (clk2) of judgement output module; The 4th output terminal of clock (clk500) of clock trees module is connected to the 4th input end of clock (clk500) of judgement output template;
The first input end of multi-user's module (A) is connected outside next selecting side, numerical control multipurpose family respectively with second input (B); The local pseudo noise code of multi-user's module (local PN sign indicating number) input receives the encryption output signal from local encryption module; Multi-user's output of multi-user's module is connected to multi-user's input of generation of first and second templates and comparison module;
Data input pin after the comparison of local encryption module (Dcomp) is connected to the data output end (Dcomp) after the comparison of synchronous counting step-out reseting module;
First template produces the pulse position modulation input signal that receives the outside with system's pulse position modulation input (PPMin) of comparison module; First template produces and the pattern control input end (modctrl) of comparison module is connected to power supply (Vdd); First template produces this signal input part of Q that is connected to the judgement output module with this signal output part of Q that compares template; First template produces the Q external signal input that is connected to the judgement output module with the Q external signal output that compares template; First template produces the second pulse position modulation output (relatively back PPM1) after the comparison with template relatively and is connected to the second pulse position modulation input (relatively back PPM1) after the comparison of synchronous counting step-out reseting module;
Second template produces the pulse position modulation input signal that receives the outside with system's pulse position modulation input (PPMin) of comparison module; Second template produces and the pattern control input end (modctrl) of comparison module is connected to ground (Vss); Second template produces the first pulse position modulation output (relatively back PPM0) after the comparison with template relatively and is connected to the first pulse position modulation input (relatively back PPM0) after the comparison of synchronous counting step-out reseting module;
Synchronously counting step-out reseting module enable output (en) be connected to first and second templates produce with comparison module enable input (en) and judgement output module enable input (en); External reset signal (Reset) is connected to the RESET input (Reset) of synchronous counting step-out reseting module;
The data output end (Dataout) of judgement output template is the later data output end of demodulator conclusive judgement; The data clock output (clkout) of judgement output template is the later data clock output of demodulator conclusive judgement.
2. pulse position modulation ultra wideband receiver demodulator when multi-user according to claim 1 jumps, it is characterized in that: said multi-user's module comprises first AND circuit and first OR circuit;
First AND circuit is sent in the local pseudo noise code and the first multi-user selecting side from local encryption module, and the output of first AND circuit and the second multi-user selecting side are sent into first OR circuit together, and the output of first OR circuit is multi-user's output.
3. pulse position modulation ultra wideband receiver demodulator when multi-user according to claim 1 jumps is characterized in that: said local encryption module comprises second AND circuit, 8 frequency dividing circuits and local pseudo noise code and produces circuit;
First clock signal from data-signal after the comparison of synchronous counting step-out reseting module and the output of clock trees module is sent into second AND circuit; The output of second AND circuit is through 8 frequency dividing circuits; Deliver to local pseudo noise code again and produce circuit, the output that last local pseudo noise code produces circuit is to encrypt output.
4. pulse position modulation ultra wideband receiver demodulator when multi-user according to claim 1 jumps is characterized in that: said first template generation and comparison module and second template produce with each self-contained half adder circuit of comparison module, pulse position modulation and produce circuit, the first d type flip flop circuit, 2 serial-parallel conversion circuits, first buffer circuits and comparator circuits;
Multi-user's input signal is sent into half adder circuit with mode control signal, and half adder circuit output is delivered to pulse position modulation and produced circuit; Pulse position modulation produces first clock of the clock of circuit from the output of clock trees module; Pulse position modulation produces the signal of circuit output and delivers to the first d type flip flop circuit, and the clock of the first d type flip flop circuit is from the second clock of clock trees module output; First serial-parallel conversion circuit is sent in the output of the first d type flip flop circuit, and the clock of first serial-parallel conversion circuit is from first clock of clock trees module output; System's pulse position modulation input signal is sent into second serial-parallel conversion circuit, and the clock of second serial-parallel conversion circuit is from output first clock of clock trees module; First buffer circuits is all delivered in 4 tunnel outputs separately of first and second serial-parallel conversion circuits, and the enable signal of first buffer circuits is from the Enable Pin of synchronous counting step-out reseting module; Comparator circuit is delivered in 24 tunnel outputs of first buffer circuits, and the clock of comparator circuit is from first clock of clock trees module output; Comparator circuit is output as the first or second pulse position modulation output after the comparison, and a road in 4 tunnel outputs of first serial-parallel conversion circuit are this output of Q, and a road in 4 tunnel outputs of second serial-parallel conversion circuit are the outer output of Q.
5. pulse position modulation ultra wideband receiver demodulator when multi-user according to claim 1 jumps is characterized in that: said synchronous counting step-out reseting module comprises second OR circuit, counter circuit and the 3rd AND circuit; First and second pulse position modulation signals were sent into second OR circuit after first and second templates produced the comparison of exporting with comparison module; Data-signal after the comparison of second OR circuit output offers local encryption module, and sends into counter circuit simultaneously; The clock of counter circuit is from first clock of clock trees module output, and the input of the 3rd AND circuit is delivered in the output of counter circuit, has reset terminal on the 3rd AND circuit, and the 3rd AND circuit is output as and enables output.
6. pulse position modulation ultra wideband receiver demodulator when multi-user according to claim 1 jumps, it is characterized in that: said judgement output template comprises 3 d type flip flop circuit, same OR circuit, the 4th AND circuit, integrating circuit and second buffer circuits;
Second and the clock of 3d flip-flop circuit all from the 3rd clock signal of clock trees module output; The data of the second d type flip flop circuit are from the Q external signal of first template generation with comparison module, and the data of 3d flip-flop circuit are from first template generation this signal of Q with comparison module; Second and the output of 3d flip-flop circuit send into same OR circuit together, with the clock of OR circuit first clock signal, send into the 4th AND circuit with the output of OR circuit from the output of clock trees module; Another signal of the 4th AND circuit is from the enabling of synchronous counting step-out reseting module, and the output of the 4th AND circuit is sent into the four d flip-flop circuit after through the integrator circuit integration; All from the 4th clock of clock trees module output, the four d flip-flop circuit is output as data output end to the clock of the four d flip-flop circuit and second buffer circuits, and second buffer circuits is output as the data clock output.
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| CN108768517A (en) * | 2018-04-19 | 2018-11-06 | 华南师范大学 | A kind of transmitting terminal, receiving terminal and visible light communication system based on PPM |
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| US20010053175A1 (en) * | 2000-01-04 | 2001-12-20 | Hoctor Ralph Thomas | Ultra-wideband communications system |
| CN1295902C (en) * | 2003-07-08 | 2007-01-17 | 上海大学 | High speed outburst type clock and data restoring apparatus |
| CN202634424U (en) * | 2012-06-16 | 2012-12-26 | 桂林电子科技大学 | Multi-user time hopping pulse position modulation ultra wide band (UWB) receiver demodulator |
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| US20010053175A1 (en) * | 2000-01-04 | 2001-12-20 | Hoctor Ralph Thomas | Ultra-wideband communications system |
| CN1295902C (en) * | 2003-07-08 | 2007-01-17 | 上海大学 | High speed outburst type clock and data restoring apparatus |
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| CN108768517A (en) * | 2018-04-19 | 2018-11-06 | 华南师范大学 | A kind of transmitting terminal, receiving terminal and visible light communication system based on PPM |
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