CN102709235B - Array base board as well as manufacturing method and display device thereof - Google Patents
Array base board as well as manufacturing method and display device thereof Download PDFInfo
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- CN102709235B CN102709235B CN201110329601.3A CN201110329601A CN102709235B CN 102709235 B CN102709235 B CN 102709235B CN 201110329601 A CN201110329601 A CN 201110329601A CN 102709235 B CN102709235 B CN 102709235B
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Abstract
The invention provides an array base board as well as a manufacturing method and a display device thereof, the manufacturing method comprises that transparent conductive film and grid metal film are formed on the base board, and a first pattern layer of a pixel electrode, a grid wire and a grid electrode is formed through a composition process; a grid insulation layer and an active layer are formed, and patterns of the active layer are formed through the composition process; an insulation layer is formed, patterns of a protective layer and a stop layer are formed through the composition process, and the stop layer is arranged on a channel zone of the active layer; and the transparent conductive film and source-drain metal film is formed, and a second pattern layer of the pixel electrode, a source-drain electrode and a data wire is formed through the composition process. By the adoption of four composition processes provide by the invention, the manufacture of the array base board is realized, the manufacture time can be shortened, the production efficiency is increased, and the production cost is lowered.
Description
Technical field
The present invention relates to Display Technique field, particularly relate to a kind of array base palte and manufacture method, display unit.
Background technology
Flat-panel monitor is the display of current main flow, and it comprises active matrix organic light emitting diode display (AMOLED), Thin Film Transistor-LCD (TFT-LCD) etc.TFT-LCD has the features such as volume is little, low in energy consumption, radiationless, in current flat panel display market, occupy leading position.According to the direction of an electric field driving liquid crystal, TFT-LCD is divided into vertical electric field type and horizontal electric field type.And vertical electric field type comprises twisted nematic (TN) TFT-LCD, horizontal electric field type comprises fringing field effect (FFS) TFT-LCD, copline field effect (IPS) TFT-LCD.FFS type TFT-LCD has the advantage such as wide viewing angle, high aperture, is widely used in field of liquid crystal display.
In the manufacture craft of thin-film transistor, in some cases, in order to prevent carving crossing of active layer when forming source-drain electrode, need on active layer, deposit one deck etching barrier layer, this needs once extra photoetching process to form etching barrier layer, such as, for bottom gate type TFT, general needs five patterning processes complete manufacture, complex process, manufacturing time is longer, and manufacturing cost is also higher.
In addition, the size of liquid crystal display is in continuous increase, and the frequency of drive circuit is improving constantly, because the mobility of amorphous silicon film transistor is generally at 0.5cm
2about/VS, and display size more than 80in time, driving frequency, more than 120Hz, needs 1cm
2the mobility of/more than VS, existing amorphous silicon film transistor mobility is difficult to satisfy the demands.The mobility of metal oxide thin-film transistor is high, homogeneity good, transparent, the demand of large scale liquid crystal display and active organic electroluminescent can be met better, therefore high performance metal-oxide thin-film transistor enjoys the concern of people, has become nearest study hotspot.
Summary of the invention
The object of this invention is to provide a kind of array base palte and manufacture method, display unit, adopt the manufacture that four times patterning processes realizes array base palte, thus shorten the production time, enhance productivity, reduce production cost.
To achieve these goals, the invention provides a kind of manufacture method of array base palte, comprising:
The figure of step 1, formation ground floor pixel electrode, grid line and gate electrode;
Step 2, be formed with the figure of active layer;
Step 3, form the figure on protective layer and barrier layer;
The figure of step 4, formation second layer pixel electrode, source-drain electrode and data wire
Above-mentioned manufacture method, wherein:
Described step 1 comprises: on substrate, form transparent conductive film and grid metallic film, is formed the figure of ground floor pixel electrode, grid line and gate electrode by patterning processes;
Described step 2 comprises: form gate insulation layer and active layer, be formed with the figure of active layer by patterning processes;
Described step 3 comprises: form insulating barrier, and formed the figure on protective layer and barrier layer by patterning processes, described barrier layer is positioned at above the channel region of described active layer;
Described step 4 comprises: form transparent conductive film and source and drain metallic film, is formed the figure of second layer pixel electrode, source-drain electrode and data wire by patterning processes.
Above-mentioned manufacture method, wherein, the material of described active layer is metal oxide.
To achieve these goals, the present invention also provides a kind of array base palte, comprising:
Be formed in ground floor pixel electrode, grid line and the gate electrode on substrate;
Be formed in the gate insulation layer on ground floor pixel electrode, grid line and gate electrode;
Be formed in the active layer on gate insulation layer and protective layer, and the barrier layer above the channel region being formed in active layer;
Be formed in the source-drain electrode above active layer and data wire, and form second layer pixel electrode on the protection layer.
Above-mentioned array base palte, wherein, the material of described active layer is metal oxide.
To achieve these goals, the present invention also provides a kind of display unit, wherein, comprises above-mentioned array base palte.
As can be seen from the above; technique scheme provided by the invention; in the process manufacturing FFS type TFT; a patterning processes etching barrier layer and protective layer is utilized to complete; the manufacture of array base palte just can be realized like this by four patterning processes; thus shorten the production time, improve production efficiency, reduce production cost.
Accompanying drawing explanation
Fig. 1 is the sectional view of the array base palte of the embodiment of the present invention;
Fig. 2 is the manufacture method flow chart of the array base palte of the embodiment of the present invention;
Fig. 3 is the sectional view of the embodiment of the present invention after deposit transparent conductive film and grid metallic film;
The sectional view that Fig. 4 is the embodiment of the present invention in first time patterning processes after gray tone or half-tone mask plate exposure imaging;
Fig. 5 is the sectional view of the embodiment of the present invention after completing first time patterning processes;
Fig. 6 is the sectional view of the embodiment of the present invention after completing second time patterning processes;
Fig. 7 is the sectional view of the embodiment of the present invention after completing third time patterning processes;
Fig. 8 is the sectional view of the embodiment of the present invention after deposit transparent conductive film and source and drain metallic film;
Fig. 9 is the sectional view of the embodiment of the present invention in the 4th patterning processes after gray tone or half-tone mask plate exposure imaging.
Embodiment
For making the object, technical solutions and advantages of the present invention clearly, describe the present invention below in conjunction with the accompanying drawings and the specific embodiments.
Fig. 1 is the sectional view of the array base palte of the embodiment of the present invention, and with reference to Fig. 1, this array base palte comprises:
Form ground floor pixel electrode 2, grid line (not shown) and gate electrode 3 and on substrate 1;
Be formed in the gate insulation layer 4 on ground floor pixel electrode 2, grid line and gate electrode 3;
Be formed in the active layer 5 on gate insulation layer 4 and protective layer 6, and the barrier layer 7 above the channel region being formed in active layer 5;
Be formed in the source-drain electrode 9 above active layer 5 and data wire (not shown), and be formed in the second layer pixel electrode 8 on protective layer 6.
The method forming each layer pattern of above-mentioned array base palte can be the deposition of advanced row metal, then adopt the patterning processes comprising mask, etching etc. to realize, directly can also carry out the conventional patterning processes such as silk screen printing, printing and realize for not carrying out the deposition of metal.Those skilled in the art can select according to concrete demand.
The mobility of metal oxide thin-film transistor is high, homogeneity good, transparent, the demand of large scale liquid crystal display and active organic electroluminescent can be met better.Therefore, as a preferred version, the material of the described active layer 5 in the above-mentioned array base palte of the embodiment of the present invention is metal oxide, such as, and IGZO, IZO, ZnO etc.By the high mobility of metal oxide and FFS molded breadth visual angle are combined, this array base palte can be widely used in large size TFT-LCD, and possess the advantages such as high aperture, high mobility and wide viewing angle simultaneously.
In addition, for the array base palte of this kind of structure, protective layer 6 and barrier layer 7 can be combined into a mask plate (Mask) and come; the manufacture of array base palte just can be realized like this by four patterning processes; so, the manufacturing process of array base palte can be simplified, reduce production cost.
Fig. 2 is the manufacture method flow chart of the array base palte of the embodiment of the present invention, and with reference to Fig. 2, this manufacture method comprises the steps:
Step 100: deposit transparent conductive film and grid metallic film successively on substrate, forms the figure of ground floor pixel electrode, grid line and gate electrode by first time patterning processes;
First provide a substrate, described substrate can select glass substrate or quartz base plate; Then, as shown in Figure 3, adopt the metal level 31 of sputtering, thermal evaporation or other film build method deposit thickness to be the transparent conductive film 21 of 30-50nm and thickness be 200-400nm successively on substrate, described transparent conductive film can be tin indium oxide, zinc-tin oxide etc., metal level 31 can be Cu, Al, Mo, Ti etc., described transparent conductive film 21 is for the formation of described ground floor pixel electrode, and described metal level 31 is for the formation of described grid line and described gate electrode; Finally, as shown in Figure 5, the figure of ground floor pixel electrode, grid line and gate electrode is formed by first time patterning processes.
Step 200: deposit gate insulation layer and active layer successively on the substrate of completing steps 100, is formed with the figure of active layer by second time patterning processes;
First, using plasma strengthens chemical vapour deposition (CVD) (PECVD) or magnetically controlled sputter method, on the substrate of completing steps 100, deposit thickness is the gate insulation layer of 30nm-80nm and thickness is successively the active layer of 20nm-50nm, wherein, gate insulation layer can select oxide or nitride, the material of active layer is preferably metal oxide, and described metal oxide can be IGZO, ZnO or IZO etc.; Then, as shown in Figure 6, the figure of active layer is formed by second time patterning processes.
Step 300: depositing insulating layer on the substrate of completing steps 200, formed the figure on protective layer and barrier layer by third time patterning processes, described barrier layer is positioned at above the channel region of described active layer;
First, adopt PECVD or magnetically controlled sputter method, on the substrate of completing steps 200, deposit thickness is the insulating barrier of 100nm-200nm, and wherein, insulating barrier can select oxide or nitride; Then, as shown in Figure 7, the figure on protective layer and barrier layer is formed by third time patterning processes.
Step 400: deposit transparent conductive film and source and drain metallic film successively on the substrate of completing steps 300, forms the figure of second layer pixel electrode, source-drain electrode and data wire by the 4th patterning processes.
First, as shown in Figure 8, adopt sputtering, thermal evaporation or other film build method deposit thickness is the transparent conductive film of 30-50nm and thickness successively on the substrate of completing steps 300 is the metal level of 200-400nm, described transparent conductive film can be tin indium oxide, zinc-tin oxide etc., metal level can be Cu, Al, Mo, Ti etc., described transparent conductive film is for the formation of described second layer pixel electrode, and described metal level is for the formation of described data wire and described source-drain electrode; Then, as shown in Figure 1, by the figure of the 4th patterning processes formation second layer pixel electrode, source-drain electrode and data wire.
Below provide the detailed process of patterning processes in above-mentioned manufacture method.
In step 100, the described figure being formed ground floor pixel electrode, grid line and gate electrode by first time patterning processes, is specifically comprised:
Step S11: apply one deck photoresist 10 on grid metallic film;
Step S12: adopt gray tone or half-tone mask plate to expose photoresist, photoresist is made to form the non-reserve area of photoresist, photoresist part reserve area and the complete reserve area of photoresist, wherein, the figure region of the corresponding grid line of the complete reserve area of photoresist and gate electrode, the figure region of the corresponding ground floor pixel electrode of photoresist part reserve area, the region beyond the corresponding above-mentioned figure of the non-reserve area of photoresist;
Step S13: carry out development treatment, the photoresist of the non-reserve area of photoresist is completely removed, the photoresist lower thickness of photoresist part reserve area, and the photoresist thickness of the complete reserve area of photoresist remains unchanged;
As shown in Figure 4, in figure, WP is the non-reserve area of photoresist to the figure that development obtains, and HP is photoresist part reserve area, and NP is the complete reserve area of photoresist.
Step S14: the grid metallic film and the transparent conductive film that etch away the non-reserve area of photoresist, forms the figure of grid line and gate electrode;
Step S15: the photoresist being removed photoresist part reserve area by cineration technics, retains the photoresist of the complete reserve area of photoresist;
Step S16: the grid metallic film etching away photoresist part reserve area, forms the figure of ground floor pixel electrode;
Step S17: remove remaining photoresist.
In step 200, the described figure being formed with active layer by second time patterning processes, is specifically comprised:
Step S21: apply one deck photoresist on active layer;
Step S22: adopt mask plate to expose photoresist, photoresist is made to form photoresist reserve area and the non-reserve area of photoresist, wherein, the figure region of the corresponding active layer of photoresist reserve area, the region beyond the corresponding above-mentioned figure of the non-reserve area of photoresist;
Step S23: carry out development treatment, the photoresist of the non-reserve area of photoresist is completely removed, and the photoresist thickness of photoresist reserve area remains unchanged;
Step S24: the active layer etching away the non-reserve area of photoresist, is formed with the figure of active layer;
Step S25: remove remaining photoresist.
In step 300, the described figure being formed protective layer and barrier layer by third time patterning processes, is specifically comprised:
Step S31: apply one deck photoresist on the insulating layer;
Step S32: adopt mask plate to expose photoresist, photoresist is made to form photoresist reserve area and the non-reserve area of photoresist, wherein, the figure region on the corresponding protective layer of photoresist reserve area and barrier layer, the region beyond the corresponding above-mentioned figure of the non-reserve area of photoresist;
Step S33: carry out development treatment, the photoresist of the non-reserve area of photoresist is completely removed, and the photoresist thickness of photoresist reserve area remains unchanged;
Step S34: the insulating barrier etching away the non-reserve area of photoresist, forms the figure on protective layer and barrier layer;
Step S35: remove remaining photoresist.
By third time patterning processes, define TFT raceway groove via hole, for the electric connection of source-drain electrode and active layer.In addition, in third time patterning processes, also can form the external via hole of grid line simultaneously.
In step 400, the described figure passing through the 4th patterning processes formation second layer pixel electrode, source-drain electrode and data wire, specifically comprises:
Step S41: apply one deck photoresist 11 on source and drain metallic film;
Step S42: adopt gray tone or half-tone mask plate to expose photoresist, photoresist is made to form the non-reserve area of photoresist, photoresist part reserve area and the complete reserve area of photoresist, wherein, the figure region of the corresponding source-drain electrode of the complete reserve area of photoresist and data wire, the figure region of the corresponding second layer pixel electrode of photoresist part reserve area, the region beyond the corresponding above-mentioned figure of the non-reserve area of photoresist;
Step S43: carry out development treatment, the photoresist of the non-reserve area of photoresist is completely removed, the photoresist lower thickness of photoresist part reserve area, and the photoresist thickness of the complete reserve area of photoresist remains unchanged;
As shown in Figure 9, in figure, WP is the non-reserve area of photoresist to the figure that development obtains, and HP is photoresist part reserve area, and NP is the complete reserve area of photoresist.
Step S44: the source and drain metallic film and the transparent conductive film that etch away the non-reserve area of photoresist, forms the figure of source-drain electrode and data wire;
Step S45: the photoresist being removed photoresist part reserve area by cineration technics, retains the photoresist of the complete reserve area of photoresist;
Step S46: the source and drain metallic film etching away photoresist part reserve area, forms the figure of second layer pixel electrode;
Step S47: remove remaining photoresist.
In above-mentioned patterning processes, the formation of photoresist is the mode applied is example, and the modes such as deposition can certainly be adopted to form photoresist.
The embodiment of the present invention also provides a kind of display unit, it is characterized in that, comprising: color membrane substrates; Be engaged in the thin-film transistor array base-plate of described color membrane substrates; Be located in the liquid crystal layer between described color membrane substrates and described thin-film transistor array base-plate.Described thin-film transistor array base-plate comprises:
Be formed in ground floor pixel electrode, grid line and the gate electrode on substrate;
Be formed in the gate insulation layer on grid line, gate electrode and ground floor pixel electrode;
Be formed in the active layer on gate insulation layer and protective layer, and the barrier layer above the channel region being formed in active layer;
Be formed in the source-drain electrode above active layer and data wire, and form second layer pixel electrode on the protection layer.
Preferably, the material of described active layer is metal oxide.
It should be noted that, above-mentioned display unit can be display panels, liquid crystal display, LCD TV, AMOLED display floater, displayer etc., is not limited at this.
In sum; the technique scheme that the embodiment of the present invention provides; in the process manufacturing FFS type TFT; a patterning processes etching barrier layer and protective layer is utilized to complete; the manufacture of array base palte just can be realized like this by four patterning processes; thus shorten the production time, improve production efficiency, reduce production cost.
Finally should be noted that, above embodiment is only in order to illustrate technical scheme of the present invention and unrestricted, those of ordinary skill in the art is to be understood that, can modify to technical scheme of the present invention or equivalent replacement, and not departing from the scope of technical solution of the present invention, it all should be encompassed in the middle of right of the present invention.
Claims (10)
1. a manufacture method for array base palte, is characterized in that, comprising:
The figure of step 1, formation ground floor pixel electrode, grid line and gate electrode;
Step 2, be formed with the figure of active layer;
Step 3, form the figure on protective layer and barrier layer;
The figure of step 4, formation second layer pixel electrode, source-drain electrode and data wire.
2. manufacture method as claimed in claim 1, is characterized in that:
Described step 1 comprises: on substrate, form transparent conductive film and grid metallic film, is formed the figure of ground floor pixel electrode, grid line and gate electrode by patterning processes;
Described step 2 comprises: form gate insulation layer and active layer, be formed with the figure of active layer by patterning processes;
Described step 3 comprises: form insulating barrier, and formed the figure on protective layer and barrier layer by patterning processes, described barrier layer is positioned at above the channel region of described active layer;
Described step 4 comprises: form transparent conductive film and source and drain metallic film, is formed the figure of second layer pixel electrode, source-drain electrode and data wire by patterning processes.
3. manufacture method as claimed in claim 2, is characterized in that, the described figure being formed ground floor pixel electrode, grid line and gate electrode by patterning processes, being comprised:
Grid metallic film is formed one deck photoresist;
Gray tone or half-tone mask plate is adopted to expose photoresist, photoresist is made to form the non-reserve area of photoresist, photoresist part reserve area and the complete reserve area of photoresist, wherein, the figure region of the corresponding grid line of the complete reserve area of photoresist and gate electrode, the figure region of the corresponding ground floor pixel electrode of photoresist part reserve area, the region beyond the corresponding above-mentioned figure of the non-reserve area of photoresist;
Carry out development treatment, the photoresist of the non-reserve area of photoresist is completely removed, the photoresist lower thickness of photoresist part reserve area, and the photoresist thickness of the complete reserve area of photoresist remains unchanged;
Remove grid metallic film and the transparent conductive film of the non-reserve area of photoresist, form the figure of grid line and gate electrode;
Removed the photoresist of photoresist part reserve area by cineration technics, retain the photoresist of the complete reserve area of photoresist;
Remove the grid metallic film of photoresist part reserve area, form the figure of ground floor pixel electrode;
Remove remaining photoresist.
4. manufacture method as claimed in claim 2, it is characterized in that, the described figure being formed with active layer by patterning processes, being comprised:
Active layer is formed one deck photoresist;
Adopt mask plate to expose photoresist, make photoresist form photoresist reserve area and the non-reserve area of photoresist, wherein, the figure region of the corresponding active layer of photoresist reserve area, the region beyond the corresponding above-mentioned figure of the non-reserve area of photoresist;
Carry out development treatment, the photoresist of the non-reserve area of photoresist is completely removed, and the photoresist thickness of photoresist reserve area remains unchanged;
Remove the active layer of the non-reserve area of photoresist, be formed with the figure of active layer;
Remove remaining photoresist.
5. manufacture method as claimed in claim 2, is characterized in that, the described figure being formed protective layer and barrier layer by patterning processes, being comprised:
Form one deck photoresist on the insulating layer;
Mask plate is adopted to expose photoresist, photoresist is made to form photoresist reserve area and the non-reserve area of photoresist, wherein, the figure region on the corresponding protective layer of photoresist reserve area and barrier layer, the region beyond the corresponding above-mentioned figure of the non-reserve area of photoresist;
Carry out development treatment, the photoresist of the non-reserve area of photoresist is completely removed, and the photoresist thickness of photoresist reserve area remains unchanged;
Remove the insulating barrier of the non-reserve area of photoresist, form the figure on protective layer and barrier layer;
Remove remaining photoresist.
6. manufacture method as claimed in claim 2, is characterized in that, the described figure being formed second layer pixel electrode, source-drain electrode and data wire by patterning processes, being comprised:
Source and drain metallic film is formed one deck photoresist;
Gray tone or half-tone mask plate is adopted to expose photoresist, photoresist is made to form the non-reserve area of photoresist, photoresist part reserve area and the complete reserve area of photoresist, wherein, the figure region of the corresponding source-drain electrode of photoresist reserve area and data wire, the figure region of the corresponding second layer pixel electrode of photoresist part reserve area, the region beyond the corresponding above-mentioned figure of the non-reserve area of photoresist;
Carry out development treatment, the photoresist of the non-reserve area of photoresist is completely removed, the photoresist lower thickness of photoresist part reserve area, and the photoresist thickness of the complete reserve area of photoresist remains unchanged;
Remove source and drain metallic film and the transparent conductive film of the non-reserve area of photoresist, form the figure of source-drain electrode and data wire;
Removed the photoresist of photoresist part reserve area by cineration technics, retain the photoresist of the complete reserve area of photoresist;
Remove the source and drain metallic film of photoresist part reserve area, form the figure of second layer pixel electrode;
Remove remaining photoresist.
7. manufacture method as claimed in claim 1, is characterized in that:
The material of described active layer is metal oxide.
8. an array base palte, is characterized in that, comprising:
Be formed in ground floor pixel electrode, grid line and the gate electrode on substrate;
Be formed in the gate insulation layer on ground floor pixel electrode, grid line and gate electrode;
Be formed in the active layer on gate insulation layer and protective layer, and the barrier layer above the channel region being formed in active layer;
Be formed in the source-drain electrode above active layer and data wire, and form second layer pixel electrode on the protection layer.
9. array base palte as claimed in claim 8, is characterized in that:
The material of described active layer is metal oxide.
10. a display unit, is characterized in that, comprises array base palte as claimed in claim 8 or 9.
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| CN103337479B (en) | 2013-07-05 | 2016-03-30 | 合肥京东方光电科技有限公司 | The manufacture method of a kind of array base palte, display unit and array base palte |
| JP5822097B2 (en) * | 2013-09-20 | 2015-11-24 | Dic株式会社 | Liquid crystal display element and manufacturing method thereof |
| CN103762223A (en) * | 2013-12-31 | 2014-04-30 | 深圳市华星光电技术有限公司 | Light-emitting device with oxide thin-film transistor and manufacturing method thereof |
| CN104319274B (en) * | 2014-11-14 | 2017-03-29 | 京东方科技集团股份有限公司 | Array base palte and preparation method thereof, display floater and display device |
| CN106129071B (en) * | 2016-09-13 | 2018-12-25 | 京东方科技集团股份有限公司 | A kind of production method and related device of array substrate |
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| CN101373299A (en) * | 2007-08-21 | 2009-02-25 | 北京京东方光电科技有限公司 | FFS thin-film transistor LCD device pixel structure and manufacturing method thereof |
| CN101807550A (en) * | 2009-02-18 | 2010-08-18 | 北京京东方光电科技有限公司 | Array substrate and manufacturing method thereof and LCD monitor |
| CN101887186A (en) * | 2009-05-15 | 2010-11-17 | 乐金显示有限公司 | Array substrate for dislay device and method of fabricating the same |
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| KR20060131014A (en) * | 2005-06-14 | 2006-12-20 | 비오이 하이디스 테크놀로지 주식회사 | Fringe field switching mode lcd for high transmittance |
| CN101656232B (en) * | 2008-08-19 | 2011-10-12 | 北京京东方光电科技有限公司 | Method for manufacturing thin film transistor array substrate |
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| CN101373299A (en) * | 2007-08-21 | 2009-02-25 | 北京京东方光电科技有限公司 | FFS thin-film transistor LCD device pixel structure and manufacturing method thereof |
| CN101807550A (en) * | 2009-02-18 | 2010-08-18 | 北京京东方光电科技有限公司 | Array substrate and manufacturing method thereof and LCD monitor |
| CN101887186A (en) * | 2009-05-15 | 2010-11-17 | 乐金显示有限公司 | Array substrate for dislay device and method of fabricating the same |
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