CN102682163A - Grid optimization method for through silicon via (TSV) positions in automatic layout of three-dimensional (3D) integrated circuit - Google Patents
Grid optimization method for through silicon via (TSV) positions in automatic layout of three-dimensional (3D) integrated circuit Download PDFInfo
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Abstract
The invention discloses a grid position optimization method for through silicon vias (TSVs) in a three-dimensional (3D) integrated circuit, and belongs to the field of 3D integrated circuit designs. When the 3D integrated circuit is produced and manufactured, a manufacturer cannot process a layout in which intervals among the TSVs are smaller than interval constraint of a processing technology. According to the invention, the grid method is used to optimize the intervals among the TSVs, so that an optimized layout is obtained and the intervals among the TSVs satisfy the technological processing requirement and the manufacturing can be completed. The method disclosed by the invention is implemented according to the steps as follows: firstly, a rectangular coordinate system is established in a layout initially set for the TSVs; afterwards, coordinates of the TSVs are determined, then a grid is produced and the distance between every two grid points in the grid is guaranteed to be larger than the minimum distance capable of being technologically processed; next, each TSV is moved to a closest grid point; and finally, the phenomena that multiple TSVs exist on a single point are arranged to guarantee that only one TSV exists on each grid point of the final layout, then the optimization is completed and the integrated circuit is produced and manufactured.
Description
Invention field
Present invention relates in general to the design and the manufacturing of 3D integrated circuit, more specifically, the present invention relates to be used for the method for the autoplacement of three dimensional integrated circuits design, belong to circuit design field.
Background technology
Integrated circuit (integrated circuit) is a kind of microelectronic device or parts.Adopt certain process; Elements such as transistor, diode, resistance, electric capacity and inductance required in the circuit and wire interconnects together; Be produced on a fritter or a few fritter semiconductor wafer or the dielectric substrate; Be encapsulated in then in the shell, become microstructure with required circuit function.Today of integrated circuit develop rapidly can be on single chip integrated several hundred million transistors.More specifically, according to the description of Moore's Law, advanced technological level has reached nanoscale.But because the constraint in the plane of 2D integrated circuit structure, along with circuit towards littler, more intensive and more efficiently direction develop, a lot of thorny problems have appearred in the 2D integrated circuit on plane, the delay that long meeting brings chip like circuit.Yet the 3D integrated circuit can effectively reduce line length, improves arithmetic speed, reduces power consumption.
The 3D integrated circuit is a kind of emerging technology that under the development of 2D integrated circuit, produces.The 3D integrated circuit is piled up in vertical direction by a plurality of 2D circuit and forms, and can make its unit carry out the interconnected of interlayer through TSV (striding chip layer silicon hole) between the multilayer chiop.As long as it is reasonable that place the position of TSV, this 3D integrated circuit technique based on TSV can effectively reduce gauze length.
Like Fig. 1 is the synoptic diagram of a 3D integrated circuit, and this 3D circuit is piled up by top layer chip 6 and bottom chip 7 and forms.Standard block 8 in the circuit is the basic structure of circuit.The 3D circuit chip of certain one deck, its character and common 2D chip are similar.Standard block 8 carries out interconnected through metal interconnection line 9.And in the 3D circuit, standard block is interconnected in whole 3D circuit, and standard block 8 not only carries out interconnected through metal interconnection line 9, and utilizes TSV (silicon through hole) to carry out the interconnected of different layers unit.
Through silicon via is called for short TSV, and it is the via hole that passes chip.The effect of TSV mainly is two in the 3D integrated circuit, the first, and it is interconnected with the standard block of upper strata and the 2D of lower floor chip, and promptly TSV strides the bridge that the layer line net is in the upper and lower standard block for connecting; Secondly,, the material of TSV is superior to semiconductor materials such as silicon, so an amount of TSV of placement helps the heat radiation of circuit in circuit to heat energy power because being the very high material of thermal conductivity such as copper aluminium mostly.
Experiment shows, the minimizing degree of gauze length is relevant with the quantity of TSV, and TSV quantity can help the minimizing of gauze length at most, and the quantity of TSV is less than to a certain degree and can increases and outer gauze length on the contrary.And, as the TSV of heat sinking function in circuit, place many more, its heat radiation to circuit helps big more.
The manufacturing of 3D integrated circuit adds the processing technology that uses man-hour and has determined its line size and the spacing of TSV.So when the 3D circuit design, need consider the spacing between unit and the unit, especially will consider the spacing of TSV.In the domain of TSV Primary Location, need the spacing of TSV not violate processing technology spacing condition, its domain is carried out the constraint of processes spacing, and its domain is optimized.
Accomplish the TSV domain of optimizing and to satisfy the processing technology constraint, and go into operation and make.
Summary of the invention:
In order to solve to striding the too congestion problem of position, chip layer silicon hole (Through Silicon Via) in the 3D integrated circuit, the present invention proposes TSV position in a kind of 3D integrated circuit autoplacement apart from optimization.
When integrated circuit was made, manufacturer provided fabrication process condition or process.In the final 3D integrated circuit diagram, the chip line thickness equals the process that manufacturer provides, and the length of TSV spacing should be greater than the chip line thickness, and promptly the TSV spacing equals to add in factory the process constraint length in man-hour in the 3D integrated circuit diagram.Yet when when Primary Location designs, after the coordinate of TSV was tentatively confirmed, the spacing of TSV can be violated process constraint.Event needs to rearrange the position of TSV, makes the spacing of all TSV satisfy technological requirement.
The present invention adopts following technical scheme:
The grid optimization method of TSV position generates coordinate system in the 3D integrated circuit autoplacement in the domain of TSV Primary Location, in coordinate system, forms grid; Grid has two serial orthogonal parallel lines; Its intersection point is a lattice point, and TSV is placed on the grid, makes its distance satisfy the processes constraint; Concrete steps are following:
S1 sets up TSV domain coordinate system, and confirm each TSV coordinate of Primary Location: behind the 3D circuit layout, set up rectangular coordinate system A in the TSV domain of Primary Location, coordinate axis is along the edge of domain; After coordinate system is confirmed, confirm the coordinate of each TSV, utilize the coordinate points range formula of rectangular coordinate system to calculate the relative distance between per two TSV;
S2 sets up a secondary grid B, and the mesh lines of grid B vertical direction is perpendicular to the parallel lines series C of coordinate system A transverse axis, and the spacing of described parallel lines series C equals the processes spacing; The mesh lines of grid B horizontal direction is perpendicular to the parallel lines series D of the coordinate system A longitudinal axis, and the spacing of parallel lines series D equals the processes spacing; The intersection point of parallel lines series C and parallel lines series D constitutes the lattice point of grid B, and each lattice point has unique coordinate points in rectangular coordinate system A; The distance of above-mentioned any two adjacent lattice points equals the processes spacing;
S3 calculates the distance of each lattice point among each TSV and the said grid B respectively, judges and the nearest lattice point of each TSV, the selected target lattice point of lattice point as it that change; If the nearest lattice point number of certain TSV, is then got wherein any lattice point greater than 2 as the target lattice point;
S4 moves to each TSV on the target lattice point respectively, and the situation of processes spacing constraint can not appear violating in the TSV and the TSV on other lattice points that are placed on like this on the lattice point.
S5 is behind the execution of step S4, when there is the situation of a plurality of TSV in same lattice point; Then the lattice point around this lattice point is numbered; Unnecessary TSV is put on the idle point successively, whole when occupied when the lattice point around this lattice point, put for time peripheral that just will unnecessary TSV be placed into lattice point around it successively; S5 is carried out in circulation, is at most 1 until the number of each lattice point TSV.
Above-mentioned flow process is referring to shown in Figure 4.
The scale of the coordinate axis of above-mentioned coordinate system A conforms to the size of actual domain, is accurate to nanoscale.
The grid optimization device of TSV position in the 3D integrated circuit autoplacement, it includes:
Input block: be used for input and set up TSV domain coordinate system, confirm each TSV coordinate of Primary Location: behind the 3D circuit layout, set up rectangular coordinate system A in the TSV domain of Primary Location, coordinate axis is along the edge of domain; After coordinate system is confirmed, confirm the coordinate of each TSV, utilize the coordinate points range formula of rectangular coordinate system to calculate the relative distance between per two TSV;
The grid dividing unit: be used for setting up a secondary grid B at described TSV domain coordinate system, the mesh lines of grid B vertical direction is perpendicular to the parallel lines series C of coordinate system A transverse axis, and the spacing of described parallel lines series C equals the processes spacing; The mesh lines of grid B horizontal direction is perpendicular to the parallel lines series D of the coordinate system A longitudinal axis, and the spacing of parallel lines series D equals the processes spacing; The intersection point of parallel lines series C and parallel lines series D constitutes the lattice point of grid B, and each lattice point has unique coordinate points in rectangular coordinate system A; The distance of above-mentioned any two adjacent lattice points equals the processes spacing;
The target lattice point is chosen the unit: be used for calculating respectively the distance of each TSV and said each lattice point of grid B, judge and the nearest lattice point of each TSV, selected this lattice point is as its target lattice point; If the nearest lattice point number of certain TSV, is then got wherein any lattice point greater than 2 as the target lattice point;
Mobile unit: be used for respectively each TSV being moved to described target lattice point;
Adjustment unit: be used for through after mobile unit moves; When there is the situation of a plurality of TSV in same lattice point; Lattice point to around this lattice point is numbered, unnecessary TSV is put on the idle point successively, when the lattice point around this lattice point whole when occupied; Put for time peripheral that just will unnecessary TSV be placed into lattice point around it successively, be at most 1 until the number of each lattice point TSV.
Above-mentioned structure is as shown in Figure 5.
The present invention can obtain following beneficial effect:
In the 3D integrated circuit diagram, TSV has carried out Primary Location, but the requirement of processes spacing can not all be satisfied in the spacing position of TSV in twos.The present invention is devoted to utilize the position of TSV in the 3D circuit layout of gridding method standard, finally can be met the TSV domain that processes requires, and reaches the purpose of the crowded TSV of mediation, avoids the too intensive situation of TSV.Fig. 8 is the domain after the TSV Primary Location in the 3D circuit: Fig. 9 is the domain of gridding method optimization: through two figure relatively, can intuitively find out the domain through gridding method optimization, spacing satisfies the processes requirement between the TSV, and TSV arranges in order.
Description of drawings:
Fig. 1 is the diagrammatic cross-section of 3D IC chip;
The former domain of Fig. 2 TSV;
Fig. 3 (a) TSV closes on lattice point and places the selection synoptic diagram
Fig. 3 (b) TSV closes on lattice point and places the completion synoptic diagram
Fig. 4: the process flow diagram of the grid optimization method of TSV position in the 3D integrated circuit autoplacement of the present invention;
Fig. 5: the structural representation of the grid optimization device of TSV position in the 3D integrated circuit autoplacement of the present invention
The crowded lattice point TSV of Fig. 6 moves;
Fig. 7 optimizes back TSV domain;
Figure 83 D integrated circuit TSV Primary Location domain;
Domain after the optimization of Figure 93 D integrated circuit TSV gridding method;
Among the figure: 1, TSV, 2, the process constraint spacing, 3, coordinate system, 4, moving direction, 5, grid, 6, the top layer chip, 7, bottom chip, 8, standard block, 9, the metal interconnection line, 10, substrate, 11, lattice point, 12, ruling.
Embodiment:
3D integrated circuit structure synoptic diagram is as shown in Figure 1.The 3D circuit is the structure that multilayer 2D chip in the vertical direction piles up; Its arbitrarily two-layer adjacent chip structure relation is like Fig. 1 top layer chip 6 and bottom chip 7; Standard block 8 in the chip is that integrated circuit signal is preserved and the foundation structure of transmission, and metal interconnection line 9 connects that standard blocks are accomplished but interconnected on the layer chip.Standard block is striden layer and is used when interconnected TSV1 interconnected, and that accomplishes signal strides layer transmission.The structure of TSV1 is to pass the via hole of 3D IC chip adjacent two layers.。
The present invention is devoted to the domain of tentatively confirming the TSV position is optimized, and makes the spacing of all TSV satisfy the constraint of processes spacing, and the distance of promptly any two TSV is more than or equal to the spacing of process constraint.The method of its optimization is meant, sets up coordinate system 3 in the TSV domain, confirms the coordinate of TSV; The coordinate of each TSV is regarded as a coordinate points; Set up the coordinate system 3 that a secondary grid utilization is confirmed, the coordinate points of the intersection point of two serial mutually perpendicular parallel lines of the middle equidistance of grid is called lattice point 11, and promptly the intersection point of ruling 12 is lattice points 11; The spacing size of this two series of parallel line equals the spacing size of process constraint, and each lattice point 11 has coordinate separately.Calculate the distance of the coordinate of each TSV and lattice point 11, make the coordinate points of TSV into the lattice point nearest with it.Accomplish arrangement and optimize the process of TSV coordinate.Practical implementation step of the present invention is described below.
The first step is set up rectangular coordinate system, confirms the TSV coordinate.Like Fig. 2, black circles is TSV1 among the figure, sets up a rectangular coordinate system, and its coordinate axis generates along the domain edge.The transverse axis of coordinate system is set up along the horizontal direction edge of domain, and the longitudinal axis of coordinate system is set up along the vertical direction edge of domain.In coordinate system, the coordinate of calculating and definite TSV is regarded it as a coordinate points.
Second step, generating mesh in coordinate system. confirm the size of process constraint spacing.The process constraint spacing is the processing technology that the 3D integrated circuit is used when producing, metal interconnection line 9 width of processing technology decision 3D integrated circuit and the spacing of TSV1.In coordinate system, generate a series of parallel lines perpendicular to the X axle, the spacing of parallel lines equals processing technology spacing 2, generates a series of parallel lines perpendicular to the Y axle, and the spacing of parallel lines equals processing technology spacing 2, two series of parallel lines and is ruling 12.Two series of parallel lines intersect becomes grid 5, and intersection point is a lattice point 11, calculates and the definite coordinate points of each lattice point 11 in coordinate system.Each lattice point and its distance of four lattice points up and down are the processes spacing.
The 3rd step. calculate the distance of each TSV1 coordinate points and lattice point 11 coordinate points, utilize the distance calculation formula of rectangular coordinate system.
The 4th step, with each TSV1 move to its nearest lattice point 11 on, the coordinate that is about to TSV1 changes to the coordinate with the nearest lattice point of its coordinate points.This moment, all TSV were placed on the lattice point 11, and the distance of TSV1 on lattice point and the TSV on other lattice points is greater than the processing technology spacing, shown in Fig. 3 (a).
The 5th step, move to all TSV2 on the lattice point nearest 11 with it after, a plurality of TSV2 can occur and be moved on the same lattice point 11 situation, shown in Fig. 3 (b).
A plurality of TSV take the situation of same lattice point in the arrangement domain, and its step is following:
1. close on the lattice point 11 CWs numbering in a week for greater than 1 lattice point certain TSV number.
2. successively TSV unnecessary on this lattice point is moved to closing on the lattice point of having numbered.
3. when mobile TSV runs into lattice point and had other TSV, just skip this lattice point, TSV is moved to next lattice point clockwise.
4. when all lattice points of compiling number that comparatively close on have all been taken, just with all lattice point numberings of closing on of this all lattice point, with unnecessary lattice point by the 1st step numbering, by the 2nd, 3 moved further.
5. repeating step 1-4, the number of TSV is at most one on each lattice point.
For example, shown in (a) situation, there are 4 TSV in the lattice point at center among Fig. 4, and wherein 3 is unnecessary.The lattice point on this lattice point the right exists a TSV.In this case, unnecessary TSV is moved, at first the lattice point around the lattice point of center is once numbered, begin clockwise the lattice point around it successively from 1-8 number numbering from the lattice point of top.Then with the peripherad successively lattice point of unnecessary TSV; First unnecessary TSV moves on No. 1 lattice point; Second unnecessary TSV moves on No. 2 lattice points, and the 3rd unnecessary TSV moves to lattice point No. 3, but because there has been TSV in No. three lattice points; So should move to next lattice point in order by unnecessary TSV, so this TSV is placed into lattice point No. 4.At this moment on the lattice point around all unnecessary TSV have all moved to, like (b) among Fig. 4.Repeating above-mentioned flow process is routed to each lattice point with unnecessary TSV of all lattice points in the whole domain TSV is arranged at the most.
When TSV all in the circuit independent be placed on the corresponding lattice point after, whole optimizing process finishes.Obtain complete gridding TSV and optimize domain.As shown in Figure 5.The position of all TSV is neat in the circuit, can satisfy fabrication process condition and the manufacturing of can going into operation.
Claims (3)
1.3D the grid optimization method of TSV position in the integrated circuit autoplacement; It is characterized in that: in the domain of TSV Primary Location, generate coordinate system; In coordinate system, form grid, grid has two serial orthogonal parallel lines, and its intersection point is a lattice point; TSV is placed on the grid, makes its distance satisfy the processes constraint; Concrete steps are following:
S1 sets up TSV domain coordinate system, and confirm each TSV coordinate of Primary Location: behind the 3D circuit layout, set up rectangular coordinate system A in the TSV domain of Primary Location, coordinate axis is along the edge of domain; After coordinate system is confirmed, confirm the coordinate of each TSV, utilize the coordinate points range formula of rectangular coordinate system to calculate the relative distance between per two TSV;
S2 sets up a secondary grid B in TSV domain coordinate system, the mesh lines of grid B vertical direction is perpendicular to the parallel lines series C of coordinate system A transverse axis, and the spacing of described parallel lines series C equals the processes spacing; The mesh lines of grid B horizontal direction is perpendicular to the parallel lines series D of the coordinate system A longitudinal axis, and the spacing of parallel lines series D equals the processes spacing; The intersection point of parallel lines series C and parallel lines series D constitutes the lattice point of grid B, and each lattice point has unique coordinate points in rectangular coordinate system A; The distance of above-mentioned any two adjacent lattice points equals the processes spacing;
S3 calculates the distance of each lattice point among each TSV and the said grid B respectively, judges and the nearest lattice point of each TSV, the selected target lattice point of lattice point as it that change; If the nearest lattice point number of certain TSV, is then got wherein any lattice point greater than 2 as the target lattice point;
S4 moves to each TSV on the target lattice point respectively, and the situation of processes spacing constraint can not appear violating in the TSV and the TSV on other lattice points that are placed on like this on the lattice point;
S5; When there is the situation of a plurality of TSV in same lattice point; Then the lattice point around this lattice point is numbered, unnecessary TSV is put on the idle point successively, when the lattice point around this lattice point whole when occupied; Just will unnecessary TSV be placed into successively on peripheral the point of lattice point around it, circulation execution S5 is at most 1 until the number of each lattice point TSV.
2. the grid optimization method of TSV position in the 3D integrated circuit autoplacement according to claim 1, it is characterized in that: the scale of the coordinate axis of described coordinate system A conforms to the size of actual domain, is accurate to nanoscale.
3.3D the grid optimization device of TSV position in the integrated circuit autoplacement, it is characterized in that: it includes:
Input block: be used for input and set up TSV domain coordinate system, confirm each TSV coordinate of Primary Location: behind the 3D circuit layout, set up rectangular coordinate system A in the TSV domain of Primary Location, coordinate axis is along the edge of domain; After coordinate system is confirmed, confirm the coordinate of each TSV, utilize the coordinate points range formula of rectangular coordinate system to calculate the relative distance between per two TSV;
The grid dividing unit: be used for setting up a secondary grid B at described TSV domain coordinate system, the mesh lines of grid B vertical direction is perpendicular to the parallel lines series C of coordinate system A transverse axis, and the spacing of described parallel lines series C equals the processes spacing; The mesh lines of grid B horizontal direction is perpendicular to the parallel lines series D of the coordinate system A longitudinal axis, and the spacing of parallel lines series D equals the processes spacing; The intersection point of parallel lines series C and parallel lines series D constitutes the lattice point of grid B, and each lattice point has unique coordinate points in rectangular coordinate system A; The distance of above-mentioned any two adjacent lattice points equals the processes spacing;
The target lattice point is chosen the unit: be used for calculating respectively the distance of each TSV and said each lattice point of grid B, judge and the nearest lattice point of each TSV, selected this lattice point is as its target lattice point; If the nearest lattice point number of certain TSV, is then got wherein any lattice point greater than 2 as the target lattice point;
Mobile unit: be used for respectively each TSV being moved to described target lattice point;
Adjustment unit: be used for through after mobile unit moves; When there is the situation of a plurality of TSV in same lattice point; Lattice point to around this lattice point is numbered, unnecessary TSV is put on the idle point successively, when the lattice point around this lattice point whole when occupied; Put for time peripheral that just will unnecessary TSV be placed into lattice point around it successively, be at most 1 until the number of each lattice point TSV.
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Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103324773B (en) * | 2012-11-13 | 2016-08-03 | 北京工业大学 | The Trench raceway groove layout method of TSV in 3D integrated circuit |
| CN103870652B (en) * | 2014-03-24 | 2017-01-25 | 北京工业大学 | TSV automatic insertion method of three-dimensional integrated circuit |
| CN111651958A (en) * | 2020-05-22 | 2020-09-11 | 深圳华大九天科技有限公司 | Interactive wiring method following wiring lattice points in integrated circuit layout |
| CN111710644A (en) * | 2020-05-20 | 2020-09-25 | 西南科技大学 | Three-dimensional integrated circuit layout method based on through silicon via |
| CN113553796A (en) * | 2021-07-30 | 2021-10-26 | 上海华虹宏力半导体制造有限公司 | Method and system for acquiring through hole area position in layout file and electronic equipment |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20050240893A1 (en) * | 2000-12-07 | 2005-10-27 | Cadence Design Systems, Inc. | Method and arrangement for layout and manufacture of nonmanhattan semiconductor integrated circuit using simulated euclidean wiring |
| CN102314531A (en) * | 2010-07-02 | 2012-01-11 | 北京华大九天软件有限公司 | Automatic hierarchy construction method for integrated circuit layout |
-
2012
- 2012-04-25 CN CN 201210125758 patent/CN102682163B/en not_active Expired - Fee Related
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20050240893A1 (en) * | 2000-12-07 | 2005-10-27 | Cadence Design Systems, Inc. | Method and arrangement for layout and manufacture of nonmanhattan semiconductor integrated circuit using simulated euclidean wiring |
| CN102314531A (en) * | 2010-07-02 | 2012-01-11 | 北京华大九天软件有限公司 | Automatic hierarchy construction method for integrated circuit layout |
Non-Patent Citations (2)
| Title |
|---|
| LIGANG HOU, SHU BAI, JINHUI WANG: "Research on TSV positioning in 3D IC placement", 《ELECTRICAL DESIGN OF ADVANCED PACKAGING AND SYSTEMS SYMPOSIUM》 * |
| LIGANG HOU, SHU BAI, JINHUI WANG: "TSV based 3D IC wire length calculation algorithm", 《ASIC,2011 IEEE 9TH INTERNATIONAL CONFERENCE ON》 * |
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103324773B (en) * | 2012-11-13 | 2016-08-03 | 北京工业大学 | The Trench raceway groove layout method of TSV in 3D integrated circuit |
| CN103870652B (en) * | 2014-03-24 | 2017-01-25 | 北京工业大学 | TSV automatic insertion method of three-dimensional integrated circuit |
| CN111710644A (en) * | 2020-05-20 | 2020-09-25 | 西南科技大学 | Three-dimensional integrated circuit layout method based on through silicon via |
| CN111710644B (en) * | 2020-05-20 | 2022-01-04 | 西南科技大学 | Three-dimensional integrated circuit layout method based on through silicon via |
| CN111651958A (en) * | 2020-05-22 | 2020-09-11 | 深圳华大九天科技有限公司 | Interactive wiring method following wiring lattice points in integrated circuit layout |
| CN111651958B (en) * | 2020-05-22 | 2022-06-21 | 深圳华大九天科技有限公司 | Interactive wiring method following wiring lattice points in integrated circuit layout |
| CN113553796A (en) * | 2021-07-30 | 2021-10-26 | 上海华虹宏力半导体制造有限公司 | Method and system for acquiring through hole area position in layout file and electronic equipment |
| CN113553796B (en) * | 2021-07-30 | 2024-02-09 | 上海华虹宏力半导体制造有限公司 | Method and system for acquiring position of through hole area in layout file and electronic equipment |
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