CN102662908A - Method and system for controlling high-speed interface in multi-processor system-on-chip - Google Patents
Method and system for controlling high-speed interface in multi-processor system-on-chip Download PDFInfo
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Abstract
The invention discloses a method and a system for controlling a high-speed interface in a multi-processor system-on-chip, which are mainly used for solving the problems of low efficiency of receiving and sending data of the existing system. The system comprises data packet processing units, a data packet information register, a mailbox and an effective marker bit, wherein each data packet processing unit comprises multiple threads; at the data receiving end, the threads are used for directly sending out receiving requests at the speed which is close to the line speed, receiving data packets according to the receiving requests and generating data packet information; the data packet information is placed into the data packet information register, and the threads are used for keeping the sequence of the received data packets according to the data packet information in the data packet information register and working state information in the thread mailbox; and at the data sending end, the threads are used for accurately sending the data packets to corresponding ports of external equipment at high speed according to the position situation of the effective marker bit and information of a control domain. The system disclosed by the invention has the advantages of receiving and sending the data with high efficiency and reliability, and can be used for processing the network data.
Description
Technical field
The invention belongs to the communication facilities technical field, particularly the control method of high-speed interface and system can be used for the chip multi-core system and receive and send data.
Background technology
SOC(system on a chip) generally can be divided into three parts according to function; It is respectively data processing section; Data storage part and data exchange interface part; Can data rapid and reliable get into SOC(system on a chip) and then handled timely, is directly connected to the overall performance of system, for example in common network processing unit; A plurality of multithreading bag processing units are commonly referred to PE, general primary processor ARM, high speed low capacity static RAM SRAM, high capacity dynamic RAM DRAM, data exchange interface unit and constitute.Usually the performance parameter of examination network processing unit mainly contains the average latency of main equipment and average response time, delay, handling capacity and total line use ratio of slave unit.Wherein most important is exactly the handling capacity of bag.In order to handle and to transmit the data of external unit fast; The bag processing unit is resolved the header packet information in the data message that mails to this equipment; Extract the bag destination, information such as classification of service are through searching next jumping destination address of transmitting the specified data message; And then revise packet and mail to the corresponding network port, realize processing to packet.Fig. 1 provides a traditional network processing unit architectural schematic.The main equipment that this architecture comprises has a plurality of bag processing units 101 and primary processor 103; It mainly is responsible for the processing of abnormal conditions; And multiple shared slave unit resource, comprise sram cell 107, DRAM unit 109, initialization module 111 and data exchange interface 113.These units all interconnect through a group system shared bus 105, and generally network processor chip is connected with outside MAC equipment 115.Individual data bag from MAC equipment generally is 1518Byte to the maximum; When data stream is passed through the MAC layer; Packet is cut into little bag of 64Byte size, and first little bag is first data block in the packet, and interface is provided with the SOP mark when receiving this little bag; During the little bag of last in receiving packet, interface is provided with the EOP mark.If outside packet then is expressed as a little bag with its filling and with it less than the minimum length of little bag, at this moment interface both had been provided with the SOP mark, and the EOP mark is set again.The little bag of data can be recombinated under SOP and EOP sign, and network data processing unit can distribute a new buffer memory to give the little bag of data that is marked with SOP, and the SOP data can be placed on the reference position of buffer memory.Can directly be placed after the last little bag for the packet that does not indicate SOP, only after complete packet receives, just can be known its length.
When external a plurality of MAC at a slow speed, traditional method is to adopt the polling mechanism of port, when receiving data, normally carries out according to following step:
The first step: promptly high-speed packet processing engine thread is before sending Data Receiving instruction or data transmission instruction; At first need obtain the port status of MAC equipment through data exchange interface; Be that which port has been ready to send data; Which port has been ready to receive data, and for the port that is ready to send data, the bag processing unit just can send the request of reception.
Second step: the reception controller is put the data of corresponding port into the reception buffer memory according to accepting request of bag processing unit and is carried out next step processing; The port of being responsible for owing to each thread in this process is all different; A thread is responsible for the reception of a port data; They also are to carry out work in a certain order, are not also upset so receive the order of the bag of coming in.
The 3rd step: the port that writes the DRAM storer and will send after the header information renewal of bag processing unit with packet through look-up table specified data bag.
The 4th step: write transmission buffer unit to be sent to packet and control information, when the port that transmit control device will send being polled to had been ready to receive data, what the packet of handling well can be correct sent.
Articulating 71 port mac equipment with network processing unit is example, and a ready polling cycle comprises 12 instructions, wherein collects respectively from 7 MAC with two instructions to receive and the ready for sending sign, and other are dummy instruction.Only account for the sub-fraction of T.T. this moment the poll time, and most of the time all is used on the data forwarding, and this polling mode efficient when external a plurality of slow MAC is very high.But along with the minimizing of external MAC quantity, polling mode can be by subtracting particularly external two single port gigabit MAC on data forwarding efficient; One is used for receiving, and another is used for sending, and two instructions are at this moment collected respectively from two MAC and received and the ready for sending sign; Other is a dummy instruction; A polling cycle needs 36 bus cycles, and the poll time is 360ns under the frequency of 100MHz, and the data of transmitting two 64 bytes need 320ns.The poll time accounts for the about 53% of T.T., and the time all is used in the poll ready flag has got on, and efficient is very low, and the maximum data throughput is merely 1.5Gbps, can't satisfy the user growing network processing unit is used for the demand of high velocity environment.
Summary of the invention
The present invention is in order to solve the deficiency of above-mentioned technology, proposes method and system that the high-speed interface in the chip multi-core system is controlled, can satisfy the user growing network processing unit is used for the demand of high velocity environment.
Realize that the object of the invention technical thought is: a plurality of processing data packets unit is distributed the thread of a plurality of processing data packets unit receive packet as main control end from a high speed port for peripheral equipment.In order to solve the slow-footed problem of individual data bag processing unit, adopt the work of a plurality of bag processing unit for parallel to handle the data stream of a high-speed port, make the processing power of processing data packets unit not be subject to its highest point reason speed; The active request mode is used in the DRP data reception process, does not need the ready state of first poll port, and the Data Receiving under the active request mode can be near linear speed work; Guarantee that the order that receives into data is not upset, thread can be with the sequential working of setting simultaneously; Guarantee that data-interface can high efficient and reliable when sending data, adopt the mode of two effective marker bit to avoid processing data packets unit and storage unit also control information and packet not to be write all that transmitting element just sends data from the transmission buffer unit and the not stationary state that causes.Can receive the data stream of handling and transmit outside high-speed equipment like this, thereby satisfy performance requirement.
Technical scheme of the present invention is following:
One, the present invention system that the high-speed interface in the chip multi-core system is controlled:
The processing data packets unit is used for controlling the transmission of packet in reception, handle packet and the control high-speed interface of high-speed interface packet;
Reception buffer is used for temporary packet from external unit high speed port;
Receive controller, put into the reception buffer unit to packet according to the reception request gating port for peripheral equipment that the processing data packets unit directly sends;
Transmit buffer is used for depositing the packet that will send to the outside from DRAM;
Transmit control device, according to sending control information of sending of processing data packets unit sending the port for peripheral equipment that packet in the buffer unit sends to appointment;
The packet information register is used for depositing and receives the packet information that reception that controller produces is come in;
Whether the effective marker position is used for flag data bag processing unit packet and packet to have been sent control information and write the transmission buffer unit;
The thread mailbox is used for depositing the status information of thread work;
High capacity dynamic RAM DRAM is used to store the packet from after the processing data packets cell processing.
In the said system, described packet information register, they are respectively fast port sequence number registers, the sequence number register of joining the team, packet number register, little packet number register;
Fast port sequence number register is used for depositing little package informatin of the different pieces of information bag of reception, this slightly package informatin through reading of processing unit of bag the little bag in the different pieces of information bag is distinguished;
The packet number register is used to deposit the header packet information of a packet of reception, whenever deposits a packet header, and the value of packet number register is from increasing one, and passes to the sequence number register of joining the team to the value in the packet number register that increases certainly after;
Little packet number register is used for the non-header packet information of store data bag, whenever deposits a non-packet header, and the value of little packet number register is from increasing one, and passes to the sequence number register of joining the team to the value in the little packet number register that increases certainly after;
The sequence number register of joining the team; Be used to deposit packet number register and little packet number register from increasing the value after, thread is according to order between the maintenance of the information in join the team sequence number register, packet number register and the little packet number register packet and the order between little bag.
Two, the present invention's method that the high-speed interface in the chip multi-core system is controlled comprises the steps:
(1) the processing data packets unit with the chip multi-core system is divided into the reception processing unit and sends processing unit, and the working method that receives the processing unit and its respective thread of transmission processing unit is set respectively;
(2) at data receiver, for a high-speed port of external unit distributes the reception processing unit of M same programmable, the M value is 2,4,8,16;
(3) for each receives processing unit N thread is set, and makes at synchronization and have only a thread in running order, other thread is started from dormancy or waiting status, and the N value is 4,8,16,32;
(4) for each all thread that receive processing unit distributes one to receive buffer unit, in order to temporary packet from outside high-speed port;
(5) need not inquire about under the situation of each port ready state, the worker thread that receives processing unit directly sends the request of reception;
(6) thread that receives processing unit asks to receive and handle packet according to receiving, and keeps original order in order to make the packet that receives, and receives the packet information of coming in for each thread distributes four registers to be used for keeping in:
(7) for each thread that receives processing unit distributes a mailbox, a plurality of threads that receive processing unit in time exchange work state information through mailbox, are convenient to thread and switch;
(8), distribute the transmission processing unit of several same programmable for a high-speed port of external unit at data sending terminal;
(9) send processing unit for each N thread is set, wherein first is a scheduling thread, and other are several to be to fill thread, and controls the duty of filling thread through scheduling thread, and the N value is 4,8,16,32;
(10) each filling thread that sends processing unit is set and shares a plurality of transmission buffer units, and will send buffer cell and be divided into data field and control domain, be used for respectively keeping in and send to the packet of external unit and sending control information of packet;
(11) when data are ready for sending to external unit, send buffer cell for each data field zone bit and control domain zone bit are set, send behind thread data query territory zone bit and the control domain zone bit of processing unit the basis transmission packet that sends control information.
The present invention compared with prior art has the following advantages:
1) the present invention adopts a plurality of processing unit for parallel to handle the high-speed data from external unit, and is more a lot of soon than the processing speed of single bag processing unit, can make the processing power that receives processing unit not be subject to its highest point reason speed;
2) the present invention is divided into reception processing unit and transmission processing unit owing to will wrap processing unit, makes its work that can be absorbed in this processing unit, can not cause the confusion that receives and send process data packet;
3) the present invention does not need the ready state of first data query bag port owing to directly send the request of reception through the worker thread that receives processing unit, makes packet can in time get into SOC(system on a chip) and obtains handling and transmitting;
4) the present invention has guaranteed that the reception request of at every turn sending can both obtain carrying out owing to be the reception processing unit of M the same programmable of a packet port assignment of external unit, and thread can be near linear speed work to the reception of data bag under this mode;
5) the present invention carries out high speed and switches owing to for each thread that receives processing unit provides a mailbox, make the thread that receives processing unit in time exchange work state information through mailbox;
6) the present invention is because the thread of a plurality of reception processing units that has been a packet port assignment; And adopting four registers to be used for keeping in the packet information that receives high-speed port, the feasible order that receives the packet of coming in can not be upset and cause to handle and fail;
7) the present invention is at data sending terminal; Adopt the mode of two effective marker bit to guarantee that data can high-efficiency reliable send to external unit; Avoided not writing the control domain and the data field of transmission buffer unit with packet because of the thread that sends processing unit also will send control information; Thread just causes data from sending buffer unit and sending transmission failure has improved the success ratio of sending.
Description of drawings
Fig. 1 is typical network processor system architectural schematic;
Fig. 2 is a control system structural representation of the present invention;
Fig. 3 is a control method general flow chart of the present invention;
Fig. 4 is that the reception processing unit thread in the control method of the present invention switches sub-process figure;
Fig. 5 is the thread scheduling sub-process figure of the transmission processing unit in the control method of the present invention;
Fig. 6 is the synoptic diagram that keeps the packet sequence storage in the control method of the present invention;
Fig. 7 is that packet sends synoptic diagram in the control method of the present invention.
Embodiment
The present invention's mode is by way of example showed, but is not restricted to accompanying drawing, the identical in the accompanying drawings similar structure of reference number representative.
Below in conjunction with specific embodiment, the present invention is done further detailed description:
With reference to figure 2, be control system of the present invention, comprise processing data packets unit 202; Packet information register 204, reception buffer 206, transmit buffer 208; Receive controller 210, transmit control device 212, effective marker position 214; Thread mailbox 216 and high capacity dynamic RAM DRAM218, wherein:
Processing data packets unit 202, as the core parts that the network processing unit bag is handled, it and other unit frequent exchange data, the processing data packets unit comprises that four packets receive processing units in the present embodiment, two packets transmission processing units.These six packet processing units are the promoters of processing data packets task as main control end, and there are four threads each processing data packets unit;
Receive controller 210, receive the reception request gating port for peripheral equipment that processing unit sends, put into packet in the reception buffer unit that is assigned with by thread according to packet;
Fast port sequence number register 204a; Be used for depositing little package informatin of different pieces of information bag; Judge that by receiving controller 210 receiving little bag of coming in is packet header; If packet header, receiving controller is that the information of which packet is put into fast port sequence number register 204a with packet header just, this slightly package informatin through reading of processing unit of packet reception the little bag in the different pieces of information bag is distinguished;
Packet number register 204c; Be used to deposit the header packet information of a packet of reception; Judge that by receiving controller 210 receiving little bag of coming in is packet header, if packet header, packet receives the thread of processing unit and whenever deposits a packet header; The value of packet number register increases one certainly, and passes to the sequence number register of joining the team to the value in the packet number register that increases certainly after;
Little packet number register 204d; The non-header packet information that is used for the store data bag; Judge that by receiving controller 210 receiving little bag of coming in is packet header, if right and wrong packet header, packet receives the thread of processing unit and whenever deposits a non-packet header; The value of little packet number register increases one certainly, and passes to the sequence number register of joining the team to the value in the little packet number register that increases certainly after;
The sequence number register 204b that joins the team is used to deposit packet number register and little packet number register from increasing the value after;
Said these four registers assist thread to accomplish following function: the 1) ordering between little bag, and this is to guarantee that packet can be not random; 2) ordering between the packet, this is the packet queuing earlier that guarantees reception earlier; 3) identification of little bag in the different pieces of information bag, this is that the assurance packet can correctly be recombinated;
Transmit buffer 208 is used to deposit the packet and the packet control information that will send to the outside, receives buffer memory and is divided into 16 unit, and each unit is divided into data field and control domain;
Transmit control device 212, according to sending control information of sending of processing data packets unit 202 and effective marker position 214 sending the port for peripheral equipment that packets in the buffer units send to appointment;
High capacity dynamic RAM DRAM218 is used to store the packet from after the processing data packets cell processing.
The concrete participant that effective marker position 214, thread mailbox 216, fast port sequence number register 204a, the sequence number register 204b that joins the team, packet number register 204c and little packet sequence number register 204d are data processing; Receive controller 210, reception buffer 206, high capacity dynamic RAM DRAM218, transmit control device 212 and transmit buffer 208 practical implementation persons as data processing.They can be by arbitrary main control end visit as shared resource, and this control system connects the high-speed port of two external units in the present embodiment, and the whole system operation principle is following:
At first; Receive processing unit 202 by packet and directly send the request of reception; Receive controller 210 according to receiving request gating port for peripheral equipment; Thread receives into reception buffer unit to packet, produces the information of corresponding data bag and is stored in the packet information register 204 by receiving controller;
Then; After finishing receiving, produce the signal that wakes next thread up by receiving controller 210; Packet by packet receives in 202 pairs of reception buffers 206 of processing unit is handled; And dump to the little bag after handling among the DRAM218 by receiving the order of coming in according to the information in the packet information register, form a complete packet;
Then, send processing unit 202 by packet and write control domain in the transmission buffer unit to sending control information of this packet, the first effective marker position of putting this unit correspondence is effective;
At last, dump to the data field that sends in the buffer unit to packet by DRAM, the second effective marker position of putting this unit correspondence is effective; Transmit control device 212 sends to the packet in the transmission buffer unit according to the control domain information of effective marker position 214 and this unit the port for peripheral equipment of appointment.
With reference to Fig. 3, control method of the present invention comprises the steps:
Step 1: behind the system initialization, the working method that packet receives the processing unit thread is set.
With reference to Fig. 4, the concrete realization of this step is following:
(1a) thread of first packet reception processing unit is started working after the initialization system initialization; Receive a thread work completion of reason unit at first packet place after, No. five threads that switch to second packet reception processing unit are started working;
(1b) when other threads of first packet reception processing unit are in free time or dormant state, No. two threads that received first packet reception processing unit of No. five thread wakenings of processing unit by second packet are started working;
(1c) when other threads of second packet reception processing unit are in free time or dormant state, No. six threads that received second packet reception of No. two thread wakenings processing unit of processing unit by first packet are started working;
(1d) when other threads of first packet reception processing unit are in free time or dormant state, No. three threads that received first packet reception processing unit of No. six thread wakenings of processing unit by second packet are started working;
(1e) when other threads of second packet reception processing unit are in free time or dormant state, No. seven threads that received second packet reception of No. three thread wakenings processing unit of processing unit by first packet are started working;
(1f) when other threads of first packet reception processing unit are in free time or dormant state, No. four threads that received first packet reception processing unit of No. seven thread wakenings of processing unit by second packet are started working;
(1h) when other threads of second packet reception processing unit are in free time or dormant state, No. eight threads that received second packet reception of No. four thread wakenings processing unit of processing unit by first packet are started working;
(1i) when other threads of first packet reception processing unit are in free time or dormant state, a thread that is received first packet reception processing unit of No. eight thread wakenings of processing unit by second packet is started working.
Step 2: the working method that packet sends the processing unit thread is set.
With reference to Fig. 5, the concrete realization of this step is following:
(2a) first thread that each packet sends processing unit being set is scheduling thread, and whether be used to inquire about has new packet etc. to be sent, and is other thread distribution transmission task; Other three threads are used respectively No. one, No. two and three labelled notations for filling thread, are used to send packet;
(2b) if there is a new packet etc. to be sent, scheduling thread is then given this Task Distribution and is filled a thread; If a packet that is sending is arranged, certain filling thread is described in work, this moment is allocating task no longer, waits for a new packet;
(2c) fill threads when all being in free time or dormant state when No. one, No. two and No. three; Scheduling thread sends Task Distribution with a new data packets and gives the filling thread No. two; Fill thread for No. two and confirm to send buffer unit number, fill threads to No. three simultaneously and send ready signals according to filling completion signal that thread sends for No. one;
When (2d) after No. two are filled thread completion transmission task, getting into free time or dormant state, scheduling thread sends Task Distribution with next new data packets and fills thread to No. three.Scheduling thread is given the filling thread according to continue allocating task with upper type, all is sent to port for peripheral equipment up to all little bags of forming this packet.
Step 3: be that a port for peripheral equipment distributes two identical packets to receive processing unit, the worker thread that receives processing unit directly sends the request that initiatively receives, and does not need the ready state of inquiry external data bag port earlier.
Step 4: receive the effective information that controller extracts from the reception request that worker thread sent that receives processing unit; The gating port for peripheral equipment; Be stored in the reception buffer corresponding reception buffer unit to the little bag in the port for peripheral equipment by thread, this effective information is to receive the port for peripheral equipment that comprises in the request number.
Step 5: the worker thread of reception processing unit continues to receive other the little bag in the packet according to the mode of step 4; By receiving the relevant information that controller produces corresponding little bag; After whole packet reception finishes; Produce the relevant information of this packet, and be stored in the packet information register, produce a signal that is used to wake up next thread again by receiving controller then.
Step 6: after whole packet is put into the reception buffer unit; Reception buffer is sent to packet in the packet reception processing unit and handles; Receiving processing unit generation packet by packet sends control information; It is the storage space of allocation of packets DRAM that packet receives processing unit; Packet receives processing unit and dumps to the storage space of DRAM to the packet after handling in order according to the information in the packet information register, and generates the transmit queue order according to the storage order of packet; After a complete packet was received, receiving thread read the formation sequence number from the sequence number register of joining the team, and compared with the information in the packet number register, if equate this packet was put into transmit queue; If it is unequal; The thread that packet receives processing unit gets into dormancy and waits for that also sequence number changes, when sequence number changes, the thread of processing data packets unit read once more the formation sequence number also once more with the packet number register in information compare; If equate, put into transmit queue to packet.
Because the packet maximum is no more than 1518Byte, high capacity DRAM cell DRAM distributes the storage space of 2KByte on the sheet for each packet.This step is described to dump to the storage space of DRAM to packet in order, and with reference to shown in Figure 6, its step comprises as follows:
(6a) thread for each packet reception processing unit distributes a mailbox, and this mailbox is used for the work state information of record thread, and thread communicates through this mailbox.Worker thread is before the mailbox write state information of next thread; At first to read it self mailbox and need confirm to transmit which status information; Needing to transmit which information is to confirm according to the type of little bag of being received; If this little bag is a packet header, then this thread is just with new status information initialization mailbox; If this little bag is a bag tail, does not then need transmit mode information, and in mailbox, write one 0 value; If little bag of being received is a tundish, then this thread will be changed the status information in self mailbox, and write results in the mailbox of next thread;
(6b) according to the storage space of allocation of packets among the DRAM; The thread of being responsible for first little bag of unloading packet at first deposits little bag in first storage unit, and the thread of being responsible for second little bag of unloading notebook data bag through mail box notice is then wanted the storage addresses space;
(6c) according to the information in storage packet information register and the mailbox; The thread of being responsible for second little bag of unloading packet deposits second storage unit to little bag in, and the thread of being responsible for the little bag of the unloading notebook data bag next one through mail box notice is then wanted the storage addresses space;
(6d) according to the information in storage packet information register and the mailbox; The space address of notifying according to a last thread in order; This thread deposits corresponding little bag the address space of appointment in, and the thread of being responsible for the next little bag of unloading notebook data bag through mail box notice is then wanted the storage addresses space;
(6e) according to the information in storage packet information register and the mailbox; The space address of notifying according to a last thread in order; This thread deposits corresponding little bag the address space of appointment in, and the thread of being responsible for last little bag of unloading notebook data bag through mail box notice is then wanted the storage addresses space;
(6f) according to the information in storage packet information register and the mailbox, according to the space address of last thread notice, this thread deposits last little bag in the address space of appointment in order.
Step 7: distribute two packets to send the processing unit common service in two port for peripheral equipment; Packet sends the scheduling thread of processing unit according to the data packet transmission formation, confirms the packet that is ready for sending among the DRAM and is allocation of packets transmission buffer unit address to be sent.
Step 8: the filling thread that packet sends processing unit dumps to the corresponding packet in DRAM unit in the address space of the transmission buffer unit of distributing.Produce transmit queue according to the packet sequence of unloading, and after writing the control domain that sends the data buffer storage unit corresponding units to sending control information of packet, first effective marker position of this unit correspondence of set; After packet in DRAM218 write the data field that sends data buffer storage unit, it was effective to put second corresponding zone bit of this unit.
Step 9: for each transmit queue is provided with a transmitting element counter, be used for whether a new packet is arranged on the mark transmit queue, packet that is sending or do not have packets need to send.
Scheduling thread reads the transmitting element counter of this transmit queue, if there is a new packet etc. to be sent, then this Task Distribution given and fills thread; If a packet that is sending is arranged, certain transmission thread is described in work, this moment is allocating task no longer, waits for a new packet; If not having packets need sends; Just produce a skip order; When transmit control device sends buffer unit one of processing, wait for that this unit is effective, order makes next transmission buffer unit effective according to skip to fill thread; But do not write data, make transmit control device skip this transmission buffer unit and do not send data to port for peripheral equipment to it.
Step 10: fill the task that thread distributes according to scheduling thread; Behind transmit control device inquiry effective marker position; According to control domain information gating port for peripheral equipment; By filling thread packet is sent to the port for peripheral equipment of appointment, remove the effective marker position simultaneously, prepare for next packet sends.
The concrete mode of filling thread transmission packet in this step is with reference to shown in Figure 7:
At first, after scheduling thread write transmission buffer unit control corresponding territory with control information, first effective marker position of putting this unit correspondence was effective; After data in the DRAM storer write and send the corresponding data field of buffer unit, second effective marker position of putting this unit correspondence was effective.
Then, send pointer 701 and behind system initialization, point to the transmission buffer unit No. one, judge whether two effective marker positions are all effective, if not, then send pointer and remain unchanged, all effective up to two effective marker positions; If two effective marker positions are all effective, the control information of transmit control device reading unit.Port numbers according to the outside MAC703 of control information gating; Filling thread sends to the data that this sends in the buffer unit on the outside MAC703 corresponding ports; Whenever send out little bag back transmission pointer that sends in the data buffer storage unit and increase one, point to the next buffer unit that sends
At last, remove two effective marker positions of sending buffer unit No. by transmit control device; Fill thread and continue to send the little bag in the data buffer storage unit according to aforesaid way through sending pointer and transmit control device; When sending last transmission buffer unit of pointed; Send next jumping of pointer and will point to the transmission buffer unit No. one, restart to send.
The above technical scheme to the object of the invention, control method and system specifies; Should be understood that; Concerning those of ordinary skills; Can improve or conversion according to above-mentioned explanation, and all these improvement and conversion all should belong to the protection domain of accompanying claims of the present invention.
Claims (7)
1. system that the high-speed interface in the chip multi-core system is controlled comprises:
Processing data packets unit (202) is used for controlling the transmission of packet in reception, handle packet and the control high-speed interface of high-speed interface packet;
Reception buffer (206) is used for temporary packet from external unit high speed port;
Receive controller (210), put into the reception buffer unit to packet according to the reception request gating port for peripheral equipment that the processing data packets unit directly sends;
Transmit buffer (208) is used for depositing the packet that will send to the outside from DRAM;
Transmit control device (212), according to sending control information of sending of processing data packets unit sending the port for peripheral equipment that packet in the buffer unit sends to appointment;
Packet information register (204) is used for depositing and receives the packet information that reception that controller produces is come in;
Whether effective marker position (214) is used for flag data bag processing unit packet and packet to have been sent control information and write the transmission buffer unit;
Thread mailbox (216) is used for depositing the status information of thread work;
High capacity dynamic RAM DRAM (218) is used to store the packet from after the processing data packets cell processing.
2. the system that the high-speed interface in the chip multi-core system is controlled according to claim 1; It is characterized in that; Described packet information register, they are respectively fast port sequence number registers (204a), the sequence number register (204b) of joining the team; Packet number register (204c), little packet number register (204d);
Fast port sequence number register (204a) is used for depositing little package informatin of the different pieces of information bag of reception, this slightly package informatin through reading of processing unit of bag the little bag in the different pieces of information bag is distinguished;
Packet number register (204c) is used to deposit the header packet information of a packet of reception, whenever deposits a packet header, and the value of packet number register is from increasing one, and passes to the sequence number register of joining the team to the value in the packet number register that increases certainly after;
Little packet number register (204d) is used for the non-header packet information of store data bag, whenever deposits a non-packet header, and the value of little packet number register is from increasing one, and passes to the sequence number register of joining the team to the value in the little packet number register that increases certainly after;
The sequence number register (204b) of joining the team; Be used to deposit packet number register and little packet number register from increasing the value after, thread is according to order between the maintenance of the information in join the team sequence number register, packet number register and the little packet number register packet and the order between little bag.
3. the method that the high-speed interface in the chip multi-core system is controlled comprises the steps:
(1) the processing data packets unit with the chip multi-core system is divided into the reception processing unit and sends processing unit, and the working method that receives the processing unit and its respective thread of transmission processing unit is set respectively;
(2) at data receiver, for a high-speed port of external unit distributes the reception processing unit of M same programmable, the M value is 2,4,8,16;
(3) for each receives processing unit N thread is set, and makes at synchronization and have only a thread in running order, other thread is started from dormancy or waiting status, and the N value is 4,8,16,32;
(4) for each all thread that receive processing unit distributes one to receive buffer unit, in order to temporary packet from outside high-speed port;
(5) need not inquire about under the situation of each port ready state, the worker thread that receives processing unit directly sends the request of reception;
(6) thread that receives processing unit asks to receive and handle packet according to receiving, and keeps original order in order to make the packet that receives, and receives the packet information of coming in for each thread distributes four registers to be used for keeping in:
(7) for each thread that receives processing unit distributes a mailbox, a plurality of threads that receive processing unit in time exchange work state information through mailbox, are convenient to thread and switch;
(8), distribute the transmission processing unit of several same programmable for a high-speed port of external unit at data sending terminal;
(9) send processing unit for each N thread is set, wherein first is a scheduling thread, and other are several to be to fill thread, and controls the duty of filling thread through scheduling thread, and the N value is 4,8,16,32;
(10) each filling thread that sends processing unit is set and shares a plurality of transmission buffer units, and will send buffer cell and be divided into data field and control domain, be used for respectively keeping in and send to the packet of external unit and sending control information of packet;
(11) when data are ready for sending to external unit, send buffer cell for each data field zone bit and control domain zone bit are set, send behind thread data query territory zone bit and the control domain zone bit of processing unit the basis transmission packet that sends control information.
4. the method that the high-speed interface in the chip multi-core system is controlled according to claim 3; It is characterized in that; Its respective thread working method that receives processing unit is set in the said step (1); For high-speed port of external unit distributes the reception processing unit of two four threads, undertaken by following rule:
(1a) thread of first bag processing unit is started working after the initialization system initialization, and after a thread work of first bag processing unit was accomplished, No. five threads that switch to second bag processing unit were started working;
(1b) when other threads of first bag processing unit are in free time or dormant state, start working by first No. two threads that wrap processing unit of No. five thread wakenings of second bag processing unit;
(1c) when other threads of second bag processing unit are in free time or dormant state, start working by second No. six thread that wrap processing unit of No. two thread wakenings of first bag processing unit;
(1d) when other threads of first bag processing unit are in free time or dormant state, start working by first No. three threads that wrap processing unit of No. six thread wakenings of second bag processing unit;
(1e) when other threads of second bag processing unit are in free time or dormant state, start working by second No. seven thread that wrap processing unit of No. three thread wakenings of first bag processing unit;
(1f) when other threads of first bag processing unit are in free time or dormant state, start working by first No. four threads that wrap processing unit of No. seven thread wakenings of second bag processing unit;
(1h) when other threads of second bag processing unit are in free time or dormant state, start working by second No. eight thread that wrap processing unit of No. four thread wakenings of first bag processing unit;
(1i) when other threads of first bag processing unit are in free time or dormant state, start working by first thread that wraps processing unit of No. eight thread wakenings of second bag processing unit.
5. the method that the high-speed interface in the chip multi-core system is controlled according to claim 3; Its respective thread working method of sending processing unit is set in the said step (1); For high-speed port of external unit distributes the transmission processing unit of one four thread, carry out as follows:
At first; Read the buffer unit information of sending by the scheduling thread that sends processing unit; Whether confirm to send has a new packet or a packet that is sending is arranged in the buffer unit: if there is a new packet etc. to be sent, scheduling thread is then given this Task Distribution and is filled a thread; If a packet that is sending is arranged, represent that certain fills thread and work, so allocating task is no longer waited for a new packet;
Then; When the filling thread is in free time or dormant state; By scheduling thread a new data packets is sent Task Distribution and give the filling thread No. two; Fill thread for No. two and confirm to send buffer unit number, fill threads to No. three simultaneously and send ready signals, and by scheduling thread the transmission Task Distribution of next new data packets is given and to fill threads No. three according to filling completion signal that thread sends for No. one.
6. the method that the high-speed interface in the chip multi-core system is controlled according to claim 3; Wherein, The thread that receives processing unit in the said step (6) packet according to the request of reception, is before the packet of high-speed port gets into SOC(system on a chip), by external unit packet is divided into the identical little bag of several sizes earlier; Each receives the worker thread of processing unit according to the reception that receives the responsible little bag of request; And whether ready according to the packet of designated port in the definite reception request of reception request, receive little bag of this port if port is ready, otherwise this reception request is abandoned.
7. the method that the high-speed interface in the chip multi-core system is controlled according to claim 3; It is characterized in that; The thread of the described transmission processing unit of step (11) sends data according to data field zone bit and control domain zone bit, carries out as follows:
After (11a) thread of transmission processing unit will send control information and write the control domain that sends buffer unit, first effective marker position of putting this unit correspondence was effective;
After (11b) thread of transmission processing unit write the data packet the data field that sends buffer unit, second effective marker position of putting this unit correspondence was effective;
Whether simultaneously effectively the thread that (11c) sends processing unit confirms to send two corresponding effective marker positions of buffer unit; If simultaneously effectively, the thread of transmission processing unit then sends to packet in the external unit of appointment according to the control domain information that this sends buffer unit.
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