CN102655115A - TFT (thin film transistor) array substrate as well as production method and manufacturing equipment for same - Google Patents
TFT (thin film transistor) array substrate as well as production method and manufacturing equipment for same Download PDFInfo
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- CN102655115A CN102655115A CN2011100667100A CN201110066710A CN102655115A CN 102655115 A CN102655115 A CN 102655115A CN 2011100667100 A CN2011100667100 A CN 2011100667100A CN 201110066710 A CN201110066710 A CN 201110066710A CN 102655115 A CN102655115 A CN 102655115A
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Abstract
The embodiment of the invention provides a TFT (thin film transistor) array substrate as well as a production method and manufacturing equipment for the same, relating to the field of manufacturing for thin-film-transistor liquid crystal displayer, being capable of improving the charge characteristic of TFT and increasing the carrier mobility of TFT, as well as being simple and convenient in realization, and low in cost. The method comprises the following steps of: forming a gate insulating layer on a substrate; charging H2 to perform surface treatment on the gate insulating layer in a first CVD (chemical vapour deposition) cavity, and then depositing a first a-Si active layer on the gate insulating layer; performing annealing treatment on the first a-Si active layer in a second CVD cavity internally charged with high-pressure N2 and H2; and after the annealing treatment, depositing a second a-Si active layer and a third a-Si active layer on the first a-Si active layer respectively, and depositing a P-doped n<+> amorphous silicon layer on the third a-Si active layer in the first CVD cavity. The method provided by the embodiment of the invention is used for manufacturing a TFT array substrate.
Description
Technical field
The present invention relates to Thin Film Transistor-LCD and make the field, relate in particular to a kind of TFT-LCD array base palte and manufacturing approach and manufacturing equipment.
Background technology
TFT-LCD (Thin Film Transistor-Liquid Crystal Display, Thin Film Transistor-LCD) utilizes the variation that is clipped in electric field strength on the liquid crystal layer, changes the orientation of liquid crystal molecule, thereby the power of control printing opacity is come display image.In general, complete display panels must have backlight module, polaroid, TFT infrabasal plate and CF (color film) upper substrate and the box formed by their two substrates in the layer of liquid crystal molecule of filling constitute.A large amount of pixel electrodes is arranged on the TFT substrate, and voltage break-make on the pixel electrode and size are controlled by the grid that links to each other with horizontal grid line, the source signal that is connected with the longitudinal data line.Electric field strength between the pixel electrode on public electrode on the CF upper substrate and the TFT infrabasal plate changes the orientation of controlling liquid crystal molecule.On the TFT substrate parallel with grid line and be in be used for keeping next signal and arrive with the storage capacitance that can form between the storage capacitance common wire of one deck and the pixel electrode before the state of liquid crystal molecule.
The performance of TFT has determined the display quality of LCD.Adopt amorphous silicon as active semiconductor layer in the volume production, the N+ amorphous silicon that mixes with P is as the contact layer of active semiconductor layer and source-drain electrode.But amorphous silicon has more defective, and mobility is lower.The charge carrier actual migration rate μ of non-crystalline silicon tft
0Roughly at 10cm
2/ (V*s) about, but because the defective number is too many, most of electric charge that grid attracted is seized in defective and conductive capability can't be provided, and makes equivalent carrier mobility only remaining less than 1cm
2/ (V*s).In order to improve the mobility of amorphous silicon, after gate insulation layer has deposited, H is carried out on the surface usually
2Handle, make that the unsaturated linkage on surface is saturated.This way can still still be lower than 1cm so that the carrier mobility of amorphous silicon improves
2/ (V*s).
For amorphous silicon; Polysilicon has higher electron mobility (than high about 2 to 3 one magnitude of amorphous silicon); It is more good material as thin-film transistor; But generally speaking, polysilicon needs at high temperature deposition or annealing (temperature reaches more than 600 degree), and this temperature is near the fusing point of glass.Therefore need utilize special technique to make low temperature polycrystalline silicon, a kind of mode is to generate low temperature polycrystalline silicon in lower temperature deposit, but this mode needs expensive laser annealing apparatus, and the polysilicon that generates is inhomogeneous.Another kind of mode is to generate low temperature polycrystalline silicon through the metal inducement method, but this method needs extra splash-proofing sputtering metal inducing layer, and can in polysilicon, introduce metal impurities, causes Ioff to improve.In addition, the other shortcoming of using polysilicon is to need to increase the mask number of times, increases process cost and degree of difficulty.
Summary of the invention
Embodiments of the invention provide a kind of tft array substrate, and preparation method thereof and manufacturing equipment, can improve the charge characteristic of TFT, improve the TFT carrier mobility, and realize easy, cost is lower.
For achieving the above object, embodiments of the invention adopt following technical scheme:
On the one hand, a kind of manufacture method of tft array substrate is provided, comprises:
On substrate, form gate insulation layer;
In the first chemical meteorological deposit cavity, to the logical H of said gate insulation layer
2Carry out surface treatment, afterwards, the deposition first amorphous silicon active layer on said gate insulation layer;
Be filled with high pressure N in inside
2And H
2The second chemical meteorological deposit cavity in, the said first amorphous silicon active layer is carried out annealing in process;
After the annealing in process, in the said first chemical meteorological deposit cavity, on the said first amorphous silicon active layer, deposit the second amorphous silicon active layer and the 3rd amorphous silicon active layer respectively, deposition P Doped n+amorphous silicon layer on said the 3rd amorphous silicon active layer.
On the one hand, a kind of tft array substrate is provided, comprises:
Substrate;
On said substrate, be formed with gate insulation layer;
On said gate insulation layer, be formed with the first amorphous silicon active layer through annealing in process;
On the said first amorphous silicon active layer, be formed with the second amorphous silicon active layer and the 3rd amorphous silicon active layer respectively;
On said the 3rd amorphous silicon active layer, be formed with P Doped n+amorphous silicon layer.
On the one hand, provide a kind of chemistry meteorological deposition apparatus, comprising:
The first chemical meteorological deposit cavity is used for the logical H of gate insulation layer to forming on the substrate
2Carry out surface treatment, afterwards, the deposition first amorphous silicon active layer on said gate insulation layer; After the annealing in process, on the said first amorphous silicon active layer, deposit the second amorphous silicon active layer and the 3rd amorphous silicon active layer respectively, deposition P Doped n+amorphous silicon layer on said the 3rd amorphous silicon active layer;
The second chemical meteorological deposit cavity, inside is filled with high pressure N
2And H
2, be used for the said first amorphous silicon active layer is carried out annealing in process.
The embodiment of the invention provide a kind of tft array substrate, and preparation method thereof and manufacturing equipment, on substrate, form gate insulation layer; In the first chemical meteorological deposit cavity, to the logical H of this gate insulation layer
2Carry out surface treatment, afterwards, the deposition first amorphous silicon active layer on gate insulation layer; Be filled with high pressure N in inside
2And H
2The second chemical meteorological deposit cavity in, this first amorphous silicon active layer is carried out annealing in process; After the annealing in process, in the first chemical meteorological deposit cavity, on the first amorphous silicon active layer, deposit the second amorphous silicon active layer and the 3rd amorphous silicon active layer respectively, deposition P Doped n+amorphous silicon layer on the 3rd amorphous silicon active layer.Like this, after carrying out annealing in process, be positioned at the first amorphous silicon active layer parts of fine crystallization at gate insulation layer and amorphous silicon active layer interface; Form fine grain relatively uniformly, because atom queueing discipline in the fine grain silicon, defective and dangling bonds are less; Electronics transmission speed in fine grain silicon is fast; And the less morphogenetic ability of the local trap that receives hinders, thereby has improved the carrier mobility of active layer, has improved the charge characteristic of TFT.In addition; Improve carrier mobility through the amorphous silicon active layer is carried out interface processing, the cost of having avoided bringing because of the low temperature polycrystalline silicon that adopts in the prior art improves, realizes complicated shortcoming, therefore in the charge characteristic of having improved TFT; Also realize easyly, cost is lower.
Description of drawings
In order to be illustrated more clearly in the embodiment of the invention or technical scheme of the prior art; To do to introduce simply to the accompanying drawing of required use in embodiment or the description of the Prior Art below; Obviously, the accompanying drawing in describing below only is some embodiments of the present invention, for those of ordinary skills; Under the prerequisite of not paying creative work, can also obtain other accompanying drawing according to these accompanying drawings.
Fig. 1 is the TFT substrate CVD multilayer film deposition sketch map of prior art;
The schematic flow sheet of the tft array substrate manufacture method that Fig. 2 provides for the embodiment of the invention;
Fig. 3 is the TFT substrate CVD multilayer film deposition sketch map of prior art
The structural representation of the chemical meteorological deposition apparatus that Fig. 4 provides for the embodiment of the invention.
Embodiment
To combine the accompanying drawing in the embodiment of the invention below, the technical scheme in the embodiment of the invention is carried out clear, intactly description, obviously, described embodiment only is the present invention's part embodiment, rather than whole embodiment.Based on the embodiment among the present invention, those of ordinary skills are not making the every other embodiment that is obtained under the creative work prerequisite, all belong to the scope of the present invention's protection.
In the prior art, as shown in Figure 1, after forming grid 11 on the substrate 10, on substrate 10, deposit gate insulation layer 12, a-Si (amorphous silicon) active layer 13 and P Doped n+amorphous silicon layer 14 again.The gate insulation layer 12 that will carry out is referred to as CVD (Chemical Vapor Deposition, chemical meteorological deposit) multilayer film deposition with the deposition of a-Si active layer 13 and P Doped n+amorphous silicon layer 14.
Concrete, deposited in the prior art after the gate insulation layer 12, can be in the CVD inside cavity to this gate insulation layer 12 logical H
2Carry out surface treatment, make that the surperficial dangling bonds of gate insulation layer 12 are saturated.Then, deposit an a-Si active layer 131, wherein, the deposition power of an a-Si active layer 131 is 550W～750W; SiH
4Gas flow is 1400sccm～1600sccm; H
2Gas flow is 7000sccm～8500sccm; Deposition pressure is 2500mtorr～2700mtorr.Afterwards, deposition the 2nd a-Si active layer 132 on an a-Si active layer 131, wherein, the deposition power of the 2nd a-Si active layer 132 is 2300W～2500W; SiH
4Gas flow is 2200sccm～2600sccm; H
2Gas flow is 12000sccm～15000sccm; Deposition pressure is 2500mtorr～2700mtorr.The deposition rate of the 2nd a-Si active layer 132 is greater than the deposition rate of an a-Si active layer 131.The thickness of the 2nd a-Si active layer 132 is two to three times of an a-Si active layer 131 thickness for
.At last, deposition P Doped n+amorphous silicon layer 14 on the 2nd a-Si active layer 132.
The manufacture method of the tft array substrate that the embodiment of the invention provides, its step is as shown in Figure 2, comprising:
S201, on substrate, form gate insulation layer.
S202, in a CVD cavity, to the logical H of this gate insulation layer
2Carry out surface treatment, afterwards, deposition the one a-Si active layer on this gate insulation layer.
S203, be filled with high pressure N in inside
2And H
2The 2nd CVD cavity in, an a-Si active layer is carried out annealing in process.
After S204, the annealing in process, change in the CVD cavity, on an a-Si active layer, deposit the 2nd a-Si active layer and the 3rd a-Si active layer respectively, deposition P Doped n+amorphous silicon layer on the 3rd a-Si active layer first.
The manufacture method of the tft array substrate that the embodiment of the invention provides forms gate insulation layer on substrate; In a CVD cavity, to the logical H of this gate insulation layer
2Carry out surface treatment, afterwards, deposition the one a-Si active layer on gate insulation layer; Be filled with high pressure N in inside
2And H
2The 2nd CVD cavity in, an a-Si active layer is carried out annealing in process; After the annealing in process, in a CVD cavity, on an a-Si active layer, deposit the 2nd a-Si active layer and the 3rd a-Si active layer respectively, deposition P Doped n+amorphous silicon layer on the 3rd a-Si active layer.Like this, after carrying out annealing in process, be positioned at an a-Si active layer parts of fine crystallization at gate insulation layer and a-Si active layer interface; Form fine grain relatively uniformly, because atom queueing discipline in the fine grain silicon, defective and dangling bonds are less; Electronics transmission speed in fine grain silicon is fast, and lessly receives that local is morphogenetic can trap to be hindered, thereby has improved the carrier mobility of active layer; Thereby improved the carrier mobility of active layer, improved the charge characteristic of TFT.In addition; Improve carrier mobility through the amorphous silicon active layer is carried out interface processing, the cost of having avoided bringing because of the low temperature polycrystalline silicon that adopts in the prior art improves, realizes complicated shortcoming, therefore in the charge characteristic of having improved TFT; Also realize easyly, cost is lower.
The manufacture method of the tft array substrate that another embodiment of the present invention is provided with reference to Fig. 3 describes.Wherein, Fig. 3 is the TFT substrate CVD multilayer film deposition sketch map of present embodiment.
Step 1, on substrate 30, form grid 31.Afterwards, carry out CVD multilayer film deposition, deposition gate insulation layer 32 on substrate 30.
Step 2, this gate insulation layer 32 logical H2 are carried out surface treatment, make that the surperficial dangling bonds of gate insulator are saturated in a CVD inside cavity.Then, deposition the one a-Si active layer 331 on gate insulation layer 32.
Wherein, the deposition power of an a-Si active layer 331 can be 150W～300W, preferably can be 200W; SiH
4Gas flow can be 500sccm～750sccm, preferably can be 550sccm; H
2Gas flow can be 2500sccm～4000sccm, preferably can be 3000sccm; Deposition pressure can be 1600mtorr～2200mtorr, preferably can be 1800mtorr; Deposit thickness can for
Preferably can be
At this moment, the deposition rate of an a-Si active layer 331 of present embodiment is lower than the deposition rate of an a-Si active layer 131 of prior art, and the film compactness that is deposited, membrane structure are better than an a-Si active layer 131 of prior art.The thickness of the one a-Si active layer 331 of present embodiment is thin more a lot of than an a-Si active layer 131 of prior art.
After the deposition of step 3, completion the one a-Si active layer 331, substrate is forwarded in the 2nd CVD cavity.
Step 4, fill high pressure N in inside
2And H
2The 2nd CVD cavity in, an a-Si active layer 331 is carried out annealing in process, the annealing temperature of this annealing in process can be 250 ℃～350 ℃, preferably can be 300 ℃; Annealing time can be 240s～420s, preferably can be 300s.After in the 2nd CVD cavity, carrying out short annealing, an a-Si active layer 331 parts of fine crystallization form fine grain relatively uniformly.Because atom queueing discipline in the fine grain silicon, defective and dangling bonds are less, and electronics transmission speed in fine grain silicon is fast, and less receive that local is morphogenetic can the trap obstruction, thereby improved the carrier mobility of active layer.
After step 5, the annealing in process,, regulate the speed of manipulator, in the time it is gone in the CVD cavity at 35s～65s according to the difference of substrate thickness.
Step 6, in a CVD cavity, on an a-Si active layer 331, proceed the deposition of the 2nd a-Si active layer 332.The sedimentary condition of the 2nd a-Si active layer 332 of present embodiment is identical with an a-Si active layer 131 of prior art, and promptly deposition power can be 550W～750W; SiH
4Gas flow can be 1400sccm～1600sccm; H
2Gas flow can be 7000sccm～8500sccm; Deposition pressure can be 2500mtorr～2700mtorr.Just the deposit thickness of the 2nd a-Si active layer 332 of present embodiment is slightly less than an a-Si active layer 131 of prior art, compares an a-Si active layer 131 thickness few
of prior art like the 2nd a-Si active layer 332 of present embodiment
On the 2nd a-Si active layer 332, deposit the 3rd a-Si active layer 333 then.The sedimentary condition of the 3rd a-Si active layer 333 of present embodiment is identical with the 2nd a-Si active layer 132 of prior art, and promptly deposition power can be 2300W～2500W; SiH
4Gas flow can be 2200sccm～2600sccm; H
2Gas flow can be 12000sccm～15000sccm; Deposition pressure can be 2500mtorr～2700mtorr.The deposit thickness of the 3rd a-Si active layer 333 is about two to three times of the 2nd a-Si active layer 332.
At last, deposition P Doped n+amorphous silicon layer 34 on the 3rd a-Si active layer 333 is as the ohmic contact layer of a-Si active layer 33 with source, drain electrode (not expression among Fig. 3).
After step 7, the completion CVD multilayer film deposition, the deposition according to other each layers of prior art completion forms thin-film transistor.
The manufacture method of the tft array substrate that the embodiment of the invention provides forms gate insulation layer on substrate; In a CVD cavity, to the logical H of this gate insulation layer
2Carry out surface treatment, afterwards, deposition the one a-Si active layer on gate insulation layer; Be filled with high pressure N in inside
2And H
2The 2nd CVD cavity in, an a-Si active layer is carried out annealing in process; After the annealing in process, in a CVD cavity, on an a-Si active layer, deposit the 2nd a-Si active layer and the 3rd a-Si active layer respectively, deposition P Doped n+amorphous silicon layer on the 3rd a-Si active layer.Like this, after carrying out annealing in process, be positioned at an a-Si active layer parts of fine crystallization at gate insulation layer and a-Si active layer interface; Form fine grain relatively uniformly, because atom queueing discipline in the fine grain silicon, defective and dangling bonds are less; Electronics transmission speed in fine grain silicon is fast, and lessly receives that local is morphogenetic can trap to be hindered, thereby has improved the carrier mobility of active layer; Thereby improved the carrier mobility of active layer, improved the charge characteristic of TFT.In addition; Improve carrier mobility through the amorphous silicon active layer is carried out interface processing, the cost of having avoided bringing because of the low temperature polycrystalline silicon that adopts in the prior art improves, realizes complicated shortcoming, therefore in the charge characteristic of having improved TFT; Also realize easyly, cost is lower.
The tft array substrate that the embodiment of the invention provides, as shown in Figure 3, comprising:
On substrate 30, be formed with gate insulation layer 32;
On gate insulation layer 32, be formed with the first amorphous silicon active layer 331 through annealing in process;
On this first amorphous silicon active layer 331, be formed with the second amorphous silicon active layer 332 and the 3rd amorphous silicon active layer 333 respectively;
On the 3rd amorphous silicon active layer 333, be formed with P Doped n+amorphous silicon layer 34.
Further, forming this first amorphous silicon active layer 331 comprises: the deposition power of first amorphous silicon, 331 active layers can be 150W～300W, preferably can be 200W; SiH
4Gas flow can be 500sccm～750sccm, preferably can be 550sccm; H
2Gas flow can be 2500sccm～4000sccm, preferably can be 3000sccm; Deposition pressure can be 1600mtorr～2200mtorr, preferably can be 1800mtorr; The deposit thickness of the first amorphous silicon active layer can for
Preferably can be
In addition, the annealing temperature of annealing in process can be 250 ℃～350 ℃, preferably can be 300 ℃; The annealing time of annealing in process can be 240s～420s, preferably can be 300s.
The tft array substrate that the embodiment of the invention provides comprises: substrate; On substrate, be formed with gate insulation layer; On gate insulation layer, be formed with the first amorphous silicon active layer through annealing in process; On this first amorphous silicon active layer, be formed with the second amorphous silicon active layer and the 3rd amorphous silicon active layer respectively; On the 3rd amorphous silicon active layer, be formed with P Doped n+amorphous silicon layer.Like this, after carrying out annealing in process, be positioned at an a-Si active layer parts of fine crystallization at gate insulation layer and a-Si active layer interface; Form fine grain relatively uniformly, because atom queueing discipline in the fine grain silicon, defective and dangling bonds are less; Electronics transmission speed in fine grain silicon is fast, and lessly receives that local is morphogenetic can trap to be hindered, thereby has improved the carrier mobility of active layer; Thereby improved the carrier mobility of active layer, improved the charge characteristic of TFT.In addition; Improve carrier mobility through the amorphous silicon active layer is carried out interface processing, the cost of having avoided bringing because of the low temperature polycrystalline silicon that adopts in the prior art improves, realizes complicated shortcoming, therefore in the charge characteristic of having improved TFT; Also realize easyly, cost is lower.
The chemical meteorological deposition apparatus 40 that the embodiment of the invention provides, as shown in Figure 4, comprising:
The first chemical meteorological deposit cavity 401 is used for the logical H of gate insulation layer to forming on the substrate
2Carry out surface treatment, afterwards, the deposition first amorphous silicon active layer on this gate insulation layer; After the annealing in process, on the first amorphous silicon active layer, deposit the second amorphous silicon active layer and the 3rd amorphous silicon active layer respectively, deposition P Doped n+amorphous silicon layer on the 3rd amorphous silicon active layer.
The second chemical meteorological deposit cavity 402, inside is filled with high pressure N
2And H
2, be used for the first amorphous silicon active layer is carried out annealing in process.
Further, in the first chemical meteorological deposit cavity 401, deposit the first amorphous silicon active layer and comprise: the deposition power of first amorphous silicon 331 can be 150W～300W, preferably can be 200W; SiH
4Gas flow can be 500sccm～750sccm, preferably can be 550sccm; H
2Gas flow can be 2500sccm～4000sccm, preferably can be 3000sccm; Deposition pressure can be 1600mtorr～2200mtorr, preferably can be 1800mtorr; The deposit thickness of the first amorphous silicon active layer can for
Preferably can be
In addition, in addition, in the second chemical meteorological deposit cavity 402, the annealing temperature of annealing in process can be 250 ℃～350 ℃, preferably can be 300 ℃; The annealing time of annealing in process can be 240s～420s, preferably can be 300s.
The chemical meteorological deposition apparatus that the embodiment of the invention provides comprises: the first chemical meteorological deposit cavity is used for the logical H of gate insulation layer to forming on the substrate
2Carry out surface treatment, afterwards, the deposition first amorphous silicon active layer on this gate insulation layer; After the annealing in process, on the first amorphous silicon active layer, deposit the second amorphous silicon active layer and the 3rd amorphous silicon active layer respectively, deposition P Doped n+amorphous silicon layer on the 3rd amorphous silicon active layer.The second chemical meteorological deposit cavity, inside is filled with high pressure N
2And H
2, be used for the first amorphous silicon active layer is carried out annealing in process.Like this, after carrying out annealing in process, be positioned at an a-Si active layer parts of fine crystallization at gate insulation layer and a-Si active layer interface; Form fine grain relatively uniformly, because atom queueing discipline in the fine grain silicon, defective and dangling bonds are less; Electronics transmission speed in fine grain silicon is fast, and lessly receives that local is morphogenetic can trap to be hindered, thereby has improved the carrier mobility of active layer; Thereby improved the carrier mobility of active layer, improved the charge characteristic of TFT.In addition; Improve carrier mobility through the amorphous silicon active layer is carried out interface processing, the cost of having avoided bringing because of the low temperature polycrystalline silicon that adopts in the prior art improves, realizes complicated shortcoming, therefore in the charge characteristic of having improved TFT; Also realize easyly, cost is lower.
One of ordinary skill in the art will appreciate that: all or part of step that realizes said method embodiment can be accomplished through the relevant hardware of program command; Aforesaid program can be stored in the computer read/write memory medium; This program the step that comprises said method embodiment when carrying out; And aforesaid storage medium comprises: various media that can be program code stored such as ROM, RAM, magnetic disc or CD.
The above; Be merely embodiment of the present invention, but protection scope of the present invention is not limited thereto, any technical staff who is familiar with the present technique field is in the technical scope that the present invention discloses; Can expect easily changing or replacement, all should be encompassed within protection scope of the present invention.Therefore, protection scope of the present invention should be as the criterion with the protection range of said claim.
Claims (16)
1. the manufacture method of a tft array substrate is characterized in that, comprising:
On substrate, form gate insulation layer;
In the first chemical meteorological deposit cavity, to the logical H of said gate insulation layer
2Carry out surface treatment, afterwards, the deposition first amorphous silicon active layer on said gate insulation layer;
Be filled with high pressure N in inside
2And H
2The second chemical meteorological deposit cavity in, the said first amorphous silicon active layer is carried out annealing in process;
After the annealing in process, in the said first chemical meteorological deposit cavity, on the said first amorphous silicon active layer, deposit the second amorphous silicon active layer and the 3rd amorphous silicon active layer respectively, deposition P Doped n+amorphous silicon layer on said the 3rd amorphous silicon active layer.
2. method according to claim 1 is characterized in that, deposits the said first amorphous silicon active layer and comprises:
The deposition power of the said first amorphous silicon active layer is 150W～300W;
SiH
4Gas flow is 500sccm～750sccm;
H
2Gas flow is 2500sccm～4000sccm;
Deposition pressure is 1600mtorr～2200mtorr;
The deposit thickness of the said first amorphous silicon active layer is
3. method according to claim 1 and 2 is characterized in that, deposits the said first amorphous silicon active layer and comprises:
The deposition power of the said first amorphous silicon active layer is 200W;
SiH
4Gas flow is 550sccm;
H
2Gas flow is 3000sccm;
Deposition pressure is 1800mtorr;
The deposit thickness of the said first amorphous silicon active layer is
4. method according to claim 1 is characterized in that, in the said second chemical meteorological deposit cavity, finish annealing in process after, in the time of 35s～65s, said substrate is changed in the said first chemical meteorological deposit cavity.
5. method according to claim 1 is characterized in that,
The annealing temperature of said annealing in process is 250 ℃～350 ℃;
The annealing time of said annealing in process is 240s～420s.
6. according to claim 1 or 5 described methods, it is characterized in that,
The annealing temperature of said annealing in process is 300 ℃;
The annealing time of said annealing in process is 300s.
7. a tft array substrate is characterized in that, comprising:
Substrate;
On said substrate, be formed with gate insulation layer;
On said gate insulation layer, be formed with the first amorphous silicon active layer through annealing in process;
On the said first amorphous silicon active layer, be formed with the second amorphous silicon active layer and the 3rd amorphous silicon active layer respectively;
On said the 3rd amorphous silicon active layer, be formed with P Doped n+amorphous silicon layer.
8. tft array substrate according to claim 7 is characterized in that, forms the said first amorphous silicon active layer and comprises:
The deposition power of the said first amorphous silicon active layer is 150W～300W;
SiH
4Gas flow is 500sccm～750sccm;
H
2Gas flow is 2500sccm～4000sccm;
Deposition pressure is 1600mtorr～2200mtorr;
The deposit thickness of the said first amorphous silicon active layer is
9. according to claim 7 or 8 described tft array substrates, it is characterized in that, form the said first amorphous silicon active layer and comprise:
The deposition power of the said first amorphous silicon active layer is 200W;
SiH
4Gas flow is 550sccm;
H
2Gas flow is 3000sccm;
Deposition pressure is 1800mtorr;
The deposit thickness of the said first amorphous silicon active layer is
10. tft array substrate according to claim 7 is characterized in that,
The annealing temperature of said annealing in process is 250 ℃～350 ℃;
The annealing time of said annealing in process is 240s～420s.
11. according to claim 7 or 10 described tft array substrates, it is characterized in that,
The annealing temperature of said annealing in process is 300 ℃;
The annealing time of said annealing in process is 300s.
12. the meteorological deposition apparatus of chemistry is characterized in that, comprising:
The first chemical meteorological deposit cavity is used for the logical H2 of gate insulation layer that forms on the substrate is carried out surface treatment, afterwards, and the deposition first amorphous silicon active layer on said gate insulation layer; After the annealing in process, on the said first amorphous silicon active layer, deposit the second amorphous silicon active layer and the 3rd amorphous silicon active layer respectively, deposition P Doped n+amorphous silicon layer on said the 3rd amorphous silicon active layer;
The second chemical meteorological deposit cavity, inside is filled with high pressure N
2And H
2, be used for the said first amorphous silicon active layer is carried out annealing in process.
13. equipment according to claim 12 is characterized in that, in the said first chemical meteorological deposit cavity, deposits the said first amorphous silicon active layer and comprises:
The deposition power of the said first amorphous silicon active layer is 150W～300W;
SiH
4Gas flow is 500sccm～750sccm;
H
2Gas flow is 2500sccm～4000sccm;
Deposition pressure is 1600mtorr～2200mtorr;
The deposit thickness of the said first amorphous silicon active layer is
14. according to claim 12 or 13 described equipment, it is characterized in that, in the said first chemical meteorological deposit cavity, deposit the said first amorphous silicon active layer and comprise:
The deposition power of the said first amorphous silicon active layer is 200W;
SiH
4Gas flow is 550sccm;
H
2Gas flow is 3000sccm;
Deposition pressure is 1800mtorr;
The deposit thickness of the said first amorphous silicon active layer is
15. equipment according to claim 12 is characterized in that, in the said second chemical meteorological deposit cavity, the annealing temperature of said annealing in process is 250 ℃～350 ℃; The annealing time of said annealing in process is 240s～420s.
16., it is characterized in that in the said second chemical meteorological deposit cavity, the annealing temperature of said annealing in process is 300 ℃ according to claim 12 or 15 described equipment; The annealing time of said annealing in process is 300s.
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Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106019752A (en) * | 2016-07-29 | 2016-10-12 | 深圳市华星光电技术有限公司 | Liquid crystal display panel and manufacturing method thereof |
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Cited By (10)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN106019752A (en) * | 2016-07-29 | 2016-10-12 | 深圳市华星光电技术有限公司 | Liquid crystal display panel and manufacturing method thereof |
| WO2018018855A1 (en) * | 2016-07-29 | 2018-02-01 | 深圳市华星光电技术有限公司 | Liquid crystal display panel and manufacturing method thereof |
| CN106019752B (en) * | 2016-07-29 | 2020-05-05 | 深圳市华星光电技术有限公司 | Liquid crystal display panel and manufacturing method thereof |
| CN106835289A (en) * | 2016-12-30 | 2017-06-13 | 武汉华星光电技术有限公司 | A kind of device and method for preparing low temperature polycrystalline silicon |
| CN107833835A (en) * | 2017-11-03 | 2018-03-23 | 惠科股份有限公司 | The manufacture method of low-temperature polysilicon film and transistor |
| CN107919270A (en) * | 2017-11-03 | 2018-04-17 | 惠科股份有限公司 | The manufacture method of low-temperature polysilicon film and transistor |
| WO2019085009A1 (en) * | 2017-11-03 | 2019-05-09 | 惠科股份有限公司 | Fabrication method for low-temperature polycrystalline silicon thin film and transistor |
| US11205712B2 (en) | 2017-11-03 | 2021-12-21 | HKC Corporation Limited | Methods of manufacturing low-temperature polysilicon thin film and transistor |
| US11309407B2 (en) | 2017-11-03 | 2022-04-19 | HKC Corporation Limited | Methods of manufacturing low-temperature polysilicon thin film and transistor |
| CN109817576A (en) * | 2018-12-25 | 2019-05-28 | 惠科股份有限公司 | Preparation method, array substrate and the display panel of array substrate |
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