CN102637460B - Bias voltage provides device, memorizer and reading amplifying device thereof - Google Patents
Bias voltage provides device, memorizer and reading amplifying device thereof Download PDFInfo
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- CN102637460B CN102637460B CN201210124636.8A CN201210124636A CN102637460B CN 102637460 B CN102637460 B CN 102637460B CN 201210124636 A CN201210124636 A CN 201210124636A CN 102637460 B CN102637460 B CN 102637460B
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Abstract
Technical solution of the present invention provides a kind of bias voltage to provide device, including: the first PMOS transistor, the second PMOS transistor, the first nmos pass transistor, the first resistance and the second resistance；The source electrode of described first PMOS transistor and the source electrode of described second PMOS transistor are connected to supply voltage；The grid of described first PMOS transistor and drain electrode, and the grid of described second PMOS transistor is connected to the first end of described first resistance；The drain electrode of described second PMOS transistor and the drain electrode of described first nmos pass transistor are connected to the grid of described first nmos pass transistor, and the grid of described first nmos pass transistor is adapted to provide for bias voltage；The source electrode of described first nmos pass transistor is connected to the first end of described second resistance；Second end of described first resistance and the second end ground connection of described second resistance.
Description
Technical field
The present invention relates to circuit design field, particularly to a kind of bias voltage provide device, memorizer and
It reads amplifying device.
Background technology
Storage arrangement including Nonvolatile memory devices and volatile storage is typically by right
The storage of electric charge stores data " 0 " and " 1 " with release.In order to by the storage number in the memory element of memorizer
Reading out according to (" 0 " and " 1 "), general employing sense amplifier circuit senses the electric current in memory element
And/or voltage, and the storage data judged in memory element according to the electric current sensed and/or voltage are assorted
(" 0 " or " 1 ").
For Nonvolatile memory devices, when memory element stores different data value (" 0 " or " 1 "),
The threshold voltage vt of memory element is different.Therefore, in fixing gate source voltage Vgs and fixing source and drain
Under voltage Vds, the size of current flowing through memory element is different.
As it is shown in figure 1, a kind of existing sense amplifier includes: PMOS transistor M11, PMOS crystal
Pipe M12, nmos pass transistor M13, current comparator 100, and current source Iref.Sense amplifier root
The data value of the preservation of memory element CL1 is judged according to output voltage VO UT1 of current comparator 100.Specifically
Ground is said, if flowing through the electric current Icell (equal to I2) the reference current Iref more than current source of memory element CL1,
The data value that then memory element CL1 preserves is 1；If flowing through the electric current Icell (equal to I2) of memory element CL1
Less than the reference current Iref of current source, then the data value of the preservation of memory element CL1 is 0.
It addition, the grid of the nmos pass transistor M13 shown in Fig. 1 is for input offset voltage, prior art
Utilize current source or voltage source circuit to provide circuit as bias voltage, in order to obtain accurate biased electrical more
Pressure, current source circuit or voltage source circuit are complex.
As in figure 2 it is shown, another kind of existing sense amplifier includes: resistance R11, resistance R12, voltage ratio
Relatively device 200, and current source Iref.Sense amplifier is according to output voltage VO UT2 of voltage comparator 200
Judging the data value that memory element CL2 preserves, the resistance of described resistance R11 and resistance R12 is equal.Specifically
Ground is said, if flowing through the electric current Icell reference current Iref more than current source of memory element CL2, voltage ratio
The negative input voltage of relatively device is less than electrode input end voltage, then the data value that memory element CL2 preserves is
1；If flowing through the electric current Icell reference current Iref less than current source of memory element CL2, voltage comparator
Negative input voltage more than electrode input end voltage, then the data value of the preservation of memory element CL2 is 0.
From the foregoing, it will be observed that existing sense amplifier and bias voltage provide circuit to be required for accurate current source,
And current source to realize circuit complex, and sense amplifier easily produces by the inaccuracy of current source
The reading error caused.
Summary of the invention
What technical solution of the present invention solved is that existing sense amplifier and bias voltage provide circuit to be required for essence
True current source, and current source to realize circuit complex, and sense amplifier easily produces by electric current
The inaccuracy in source and the reading error that causes.
Technical solution of the present invention provides a kind of bias voltage to provide device, including: the first PMOS transistor,
Second PMOS transistor, the first nmos pass transistor, the first resistance and the second resistance；
The source electrode of described first PMOS transistor and the source electrode of described second PMOS transistor are connected to electricity
Source voltage；
The grid of described first PMOS transistor and drain electrode, and the grid of described second PMOS transistor
Pole is connected to the first end of described first resistance；
The drain electrode of described second PMOS transistor and the drain electrode of described first nmos pass transistor are connected to institute
Stating the grid of the first nmos pass transistor, the grid of described first nmos pass transistor is adapted to provide for biased electrical
Pressure；
The source electrode of described first nmos pass transistor is connected to the first end of described second resistance；
Second end of described first resistance and the second end ground connection of described second resistance.
Technical solution of the present invention also provides for the reading amplifying device of a kind of memorizer, including being suitable to read storage
The sensing element of the data of unit storage；Above-mentioned bias voltage provides device, is suitable to described sensing element
Bias voltage is provided.
Technical solution of the present invention also provides for a kind of memorizer, and including memory element, and above-mentioned reading is amplified
Device.
Compared with prior art, technical solution of the present invention has the advantage that
The bias voltage that technical solution of the present invention provides provides device to need not precision current source or voltage source,
Therefore, reduce biasing and device and the manufacture difficulty reading amplifying device of memorizer and complexity are provided.
Especially, the bias voltage that technical solution of the present invention provides provides device can be less than 1V's at supply voltage
In the case of work, not only power consumption is little, and processing speed is the highest.
The reading amplifying device of the memorizer that technical solution of the present invention provides is judged by resistance comparative result
The data value that memory element preserves, rather than the comparison of curtage, because of without precision current source or
Voltage source, reduce further manufacture difficulty and complexity.
Accompanying drawing explanation
Fig. 1 is an existing sense amplifier structural representation；
Fig. 2 is another existing sense amplifier structural representation；
Fig. 3 provides the example structure schematic diagram of device for bias voltage of the present invention；
Fig. 4 is the example structure schematic diagram of memorizer of the present invention.
Detailed description of the invention
Below in conjunction with the accompanying drawings the detailed description of the invention of the present invention is described in detail.The following passage is joined
According to the accompanying drawing present invention the most more particularly described below.According to following explanation, advantages of the present invention and spy
Levy and will be apparent from.
As it is shown on figure 3, technical solution of the present invention provides a kind of bias voltage to provide device, including: first
PMOS transistor MP1, the second PMOS transistor MP2, the first nmos pass transistor MN1,
One resistance R1 and the second resistance R2.
The source electrode of described first PMOS transistor MP1 and the source of described second PMOS transistor MP2
Pole is connected to supply voltage VDD.
The grid of described first PMOS transistor MP1 and drain electrode, and described second PMOS transistor
The grid of MP2 is connected to first end of described first resistance R1.
The drain electrode of described second PMOS transistor MP2 and the leakage of described first nmos pass transistor MN1
Pole is connected to the grid of described first nmos pass transistor MN1, described first nmos pass transistor MN1
Grid be adapted to provide for bias voltage Vbias.
The source electrode of described first nmos pass transistor MN1 is connected to first end of described second resistance R2.
Second end of described first resistance R1 and the second end ground connection of described second resistance R2.
Described first PMOS transistor MP1 becomes with the breadth length ratio of described second PMOS transistor MP2
Ratio, can arrange corresponding ratio with the resistance of the first resistance R1 in combined circuit and the second resistance R2,
Such as, described first PMOS transistor MP1 and the breadth length ratio of described second PMOS transistor MP2
Equal, i.e. 1:1.
Described first resistance R1 is proportional to the resistance of described second resistance R2.
Described bias voltage Vbias, the gate source voltage Vgsmn1 of the first nmos pass transistor MN1, electricity
Source voltage VDD, the threshold voltage vt p1 of the first PMOS transistor MP1, and the second resistance R2
And the relation between resistance ratio S1 of the first resistance R1 meets:
Vbias=Vgsmn1+ (VDD-Vtp1) * S1
Such as, the resistance ratio of described second resistance R2 and described first resistance R1 is 1:4, then
Vbias=Vgsmn1+ (VDD-Vtp1) * 0.25.
Described first PMOS transistor MP1, the second PMOS transistor MP2 and a NMOS are brilliant
Body pipe MN1 is all operated in linear zone.
The bias voltage offer device of the present embodiment can also be for the sense amplifier shown in Fig. 1 or other classes
The sense amplifier of type provides bias voltage.Bias voltage provides device to be the sense amplifier shown in Fig. 1
When bias voltage is provided, the grid of the first nmos pass transistor MN1 can be connected to NMOS crystal
The grid of pipe M13.
As shown in Figure 4, technical solution of the present invention also provides for a kind of memorizer, including memory element CL3 and
Reading amplifying device, described reading amplifying device includes being suitable to reading the data of memory element CL3 storage
Sensing element 2, and above-mentioned bias voltage offer device 1.Described bias voltage provide device 1 be suitable to
Described sensing element 2 provides bias voltage Vbias.
Described sensing element 2 includes: the 3rd PMOS transistor MP3, the 4th PMOS transistor MP4,
Second nmos pass transistor MN2, the 3rd nmos pass transistor MN3 and reference resistance Rref.
The source electrode of described 3rd PMOS transistor MP3 and the source of described 4th PMOS transistor MP4
Pole is connected to supply voltage VDD.
The grid of described 3rd PMOS transistor MP3 and drain electrode, and described 4th PMOS transistor
The grid of MP4 is connected to the drain electrode of described second nmos pass transistor MN2.
The drain electrode of described 4th PMOS transistor MP4 is connected to described 3rd nmos pass transistor MN3
Drain electrode.
The grid of described second nmos pass transistor MN2 and described 3rd nmos pass transistor MN3's
Grid is connected to the grid of the first nmos pass transistor MN1.
The source electrode of described 3rd nmos pass transistor MN3 is connected to first end of described reference resistance Rref.
The second end ground connection of described reference resistance Rref.
The source electrode of described second nmos pass transistor MN2 is connected to described memory element CL3；
The grid of described second nmos pass transistor MN2 and the 3rd nmos pass transistor MN3 inputs institute
State bias voltage Vbias.
The explanation providing device 1 about bias voltage refer to foregoing description, and here is omitted.
Described 3rd PMOS transistor MP3, the 4th PMOS transistor MP4, the 2nd NMOS are brilliant
Body pipe MN2, the 3rd nmos pass transistor MN3 are all operated in linear zone.
Described first PMOS transistor MP1, described second PMOS transistor MP2, the described 3rd
The breadth length ratio of PMOS transistor MP3 and described 4th PMOS transistor MP4 is proportional.Such as,
Described first PMOS transistor MP1, described second PMOS transistor MP2, described 3rd PMOS
The breadth length ratio of transistor MP3 and described 4th PMOS transistor MP4 is equal, i.e. 1:1:1:1.
Described first nmos pass transistor MN1, described second nmos pass transistor MN2 and the described 3rd
The breadth length ratio of nmos pass transistor MN3 is proportional.Such as, described first nmos pass transistor MN1,
The breadth length ratio of described second nmos pass transistor MN2 and described 3rd nmos pass transistor MN3 is equal,
I.e. 1:1.
The grid of the first nmos pass transistor MN1 provides bias voltage Vbias.2nd NMOS crystal
The clamper of bit line when pipe MN2 can read as memory element CL3.3rd nmos pass transistor MN3
There is clamper and the amplification of output circuit so that the voltage on reference resistance Rref is less than biased electrical
Pressure Vbias and the difference of the 3rd nmos pass transistor MN3 threshold voltage, thus accelerate output voltage
The output speed of VOUT.
The resistance of described reference resistance Rref between described memory element CL3 preserve data value be 1 time etc.
Effect resistance and preservation data value are between the resistance of equivalent resistance when 0.Such as, described reference resistance Rref
Resistance be that to preserve data value be equivalent resistance when 1 and to preserve data value be 0 to described memory element CL3
Time the intermediate value of resistance of equivalent resistance.
The data value that the resistance size of the equivalent resistance of described memory element CL3 stores with memory element CL3
Relevant, and output voltage VO UT is corresponding with the data value that memory element CL3 stores.
It is little that memory element CL3 preserves electric current when data value is 0, and the resistance of equivalent resistance is big；Memory element
It is big that CL3 preserves electric current when data value is 1, and the resistance of equivalent resistance is little.By comparing memory element CL3
Equivalent resistance and reference resistance Rref resistance, the data value that memory element CL3 is preserved can be judged.
Output voltage VO UT can embody equivalent resistance and the reference resistance Rref resistance of memory element CL3
Comparative result, therefore, by reading output voltage VO UT, it is possible to obtain memory element CL3 is preserved
Data value.
It is assumed that the resistance of the equivalent resistance of memory element CL3 is Rcell, then Rcell=k/ (Vwl-Vth).
Wherein, k is the coefficient relevant to bit location characteristic；Bit location wordline institute making alive when Vwl is for reading；Vth
Threshold voltage for memory element CL3.It can be seen that the threshold voltage vt h of memory element CL3 is the biggest,
Resistance Rcell of the equivalent resistance of memory element CL3 is the biggest.
According to the circuit shown in the present embodiment Fig. 4:
Icell=Imp3
Icell=(Vbias-Vgsmn2)/Rcell
Vgsmn3=Vbias-Rref*Icell
=Vbias-Rref* (Vbias-Vgsmn2)/Rcell
=Vbias* (1-Rref/Rcell)+Rref/Rcell*Vgsmn2
Owing to Vbias is much larger than Vgsmn2, so Vgsmn3 ≈ Vbias* (1-Rref/Rcell)
Wherein, Icell is the source current of the second nmos pass transistor MN2, and Imp3 is the 4th PMOS
The drain current of transistor MP4, the gate source voltage of Vgsmn2 the second nmos pass transistor MN2,
Vgsmn3 is the gate source voltage of the 3rd nmos pass transistor MN3.
By Vgsmn3 ≈ Vbias* (1-Rref/Rcell) it can be seen that
If Rcell < Rref, then Vgsmn3 < 0, the 3rd nmos pass transistor MN3 cut-off, output electricity
Pressure VOUT is high level, shows that the data value that memory element CL3 preserves is 1；
If Rcell > Rref, then Vgsmn3 > 0, the 3rd nmos pass transistor MN3 conducting, output
Voltage VOUT is low level, shows that the data value that memory element CL3 preserves is 0.
It should be noted that the sensing element of the present embodiment can also for the sense amplifier shown in Fig. 1,
Including: PMOS transistor M11, PMOS transistor M12, nmos pass transistor M13, current ratio
Relatively device 100, and current source Iref.Or other kinds of sense amplifier.
The bias voltage that technical solution of the present invention provides provides device to need not precision current source or voltage source,
Therefore, reduce biasing and device and the manufacture difficulty reading amplifying device of memorizer and complexity are provided.
Especially, the bias voltage that technical solution of the present invention provides provides device can be less than 1V's at supply voltage
In the case of work, not only power consumption is little, and processing speed is the highest.
Further, the reading amplifying device of the memorizer that technical solution of the present invention provides is by resistance comparative result
Judge the data value that memory element preserves, rather than the comparison of curtage, because of without accurately electricity
Stream source or voltage source, reduce further manufacture difficulty and complexity.
Although the present invention discloses as above with preferred embodiment, but the present invention is not limited to this.Any
Skilled person, without departing from the spirit and scope of the present invention, all can make various changes or modifications,
Therefore protection scope of the present invention should be with the limited scope of claim.
Claims (11)
1. a bias voltage provides device, it is characterised in that including: the first PMOS transistor, the
Two PMOS transistor, the first nmos pass transistor, the first resistance and the second resistance；
The source electrode of described first PMOS transistor and the source electrode of described second PMOS transistor are connected to electricity
Source voltage；
The grid of described first PMOS transistor and drain electrode, and the grid of described second PMOS transistor
Pole is connected to the first end of described first resistance；
The drain electrode of described second PMOS transistor and the drain electrode of described first nmos pass transistor are connected to institute
Stating the grid of the first nmos pass transistor, the grid of described first nmos pass transistor is adapted to provide for biased electrical
Pressure；
The source electrode of described first nmos pass transistor is connected to the first end of described second resistance；
Second end of described first resistance and the second end ground connection of described second resistance.
2. bias voltage as claimed in claim 1 provides device, it is characterised in that a described PMOS
The breadth length ratio of transistor and described second PMOS transistor is proportional.
3. bias voltage as claimed in claim 1 provides device, it is characterised in that described first resistance
Proportional to the resistance of described second resistance.
4. a reading amplifying device for memorizer, including being suitable to read the reading of the data of memory element storage
Go out unit, it is characterised in that also include: the bias voltage described in claim 1 provides device, is suitable to
Bias voltage is provided to described sensing element.
Read amplifying device the most as claimed in claim 4, it is characterised in that described sensing element includes:
3rd PMOS transistor, the 4th PMOS transistor, the second nmos pass transistor, the 3rd NMOS
Transistor and reference resistance；
The source electrode of described 3rd PMOS transistor and the source electrode of described 4th PMOS transistor are connected to electricity
Source voltage；
The grid of described 3rd PMOS transistor and drain electrode, and the grid of described 4th PMOS transistor
Pole is connected to the drain electrode of described second nmos pass transistor；
The drain electrode of described 4th PMOS transistor is connected to the drain electrode of described 3rd nmos pass transistor；
The grid of described second nmos pass transistor and the grid of described 3rd nmos pass transistor are connected to
The grid of one nmos pass transistor；
The source electrode of described 3rd nmos pass transistor is connected to the first end of described reference resistance；
Second end ground connection of described reference resistance；
The source electrode of described second nmos pass transistor is connected to described memory element；
The grid of described second nmos pass transistor and the 3rd nmos pass transistor inputs described bias voltage.
Read amplifying device the most as claimed in claim 5, it is characterised in that a described PMOS is brilliant
Body pipe, described second PMOS transistor, described 3rd PMOS transistor and described 4th PMOS are brilliant
The breadth length ratio of body pipe is proportional.
Read amplifying device the most as claimed in claim 5, it is characterised in that a described NMOS is brilliant
The breadth length ratio of body pipe, described second nmos pass transistor and described 3rd nmos pass transistor is proportional.
Read amplifying device the most as claimed in claim 5, it is characterised in that link together is described
The drain electrode of the 4th PMOS transistor and the drain electrode of the 3rd nmos pass transistor are adapted to provide for output voltage.
Read amplifying device the most as claimed in claim 5, it is characterised in that described first resistance and institute
The resistance stating the second resistance is proportional.
Read amplifying device the most as claimed in claim 5, it is characterised in that described reference resistance
Resistance preserves data value between described memory element and is equivalent resistance when 1 and preserves when data value is 0
Between the resistance of equivalent resistance.
11. 1 kinds of memorizeies, including memory element, it is characterised in that also include: claim 4 to
Reading amplifying device described in 10 any one.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201210124636.8A CN102637460B (en) | 2012-04-25 | 2012-04-25 | Bias voltage provides device, memorizer and reading amplifying device thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201210124636.8A CN102637460B (en) | 2012-04-25 | 2012-04-25 | Bias voltage provides device, memorizer and reading amplifying device thereof |
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| Publication Number | Publication Date |
|---|---|
| CN102637460A CN102637460A (en) | 2012-08-15 |
| CN102637460B true CN102637460B (en) | 2016-12-14 |
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| CN201210124636.8A Active CN102637460B (en) | 2012-04-25 | 2012-04-25 | Bias voltage provides device, memorizer and reading amplifying device thereof |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN103077745A (en) * | 2012-12-24 | 2013-05-01 | 上海宏力半导体制造有限公司 | Reading circuit for memory elements and memorizer |
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Owner name: SHANGHAI HUAHONG GRACE SEMICONDUCTOR MANUFACTURING Free format text: FORMER OWNER: HONGLI SEMICONDUCTOR MANUFACTURE CO LTD, SHANGHAI Effective date: 20140414 |
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Effective date of registration: 20140414 Address after: 201203 Shanghai city Zuchongzhi road Pudong New Area Zhangjiang hi tech Park No. 1399 Applicant after: Shanghai Huahong Grace Semiconductor Manufacturing Corporation Address before: Zuchongzhi road in Pudong Zhangjiang hi tech park Shanghai city Pudong New Area No. 1399 201203 Applicant before: Hongli Semiconductor Manufacture Co., Ltd., Shanghai |
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