CN102621938A - Triple redundancy control system in process control and method thereof - Google Patents
Triple redundancy control system in process control and method thereof Download PDFInfo
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Abstract
The invention discloses a triple redundancy control system in process control and a method thereof. The system comprises three independent processors. The processors are connected with each other through a bus. The control system also comprises one output vote terminal which is connected with the three processors and is used to vote three processor output taken as voting input. Each processor comprises: one input voting module, which is used for the each processor to carry out input voting on the obtained three path input respectively; one calculation processing module, which is used for the each processor to carry out calculation according to a preset control logic respectively after the input voting, and adding 1 to respective cycle count after the calculation; one synchronous processing module, which is used for carrying out comparison taking a master processor as a reference, and sending the synchronization information to a slave processor after the main processor completes calculation. In the invention, by using a synchronization mechanism, a voting mechanism and a master-slave switching mechanism, high reliability and high security of the system can be guaranteed.
Description
Technical field
The present invention relates to triplex level redundancy control and be applied to high reliability, high security occasion in the industrial process control, like fields such as nuclear power, chemical industry.
Background technology
The emphasis of triplex level redundancy technology is exactly the reliability and the security of system.Existing triplex level redundancy technology has multiple mode: a kind of is that three CPU of configuration carry out redundant computation on same card, and this mode must cause three CPU calculating to carry out when card breaks down, thereby causes the system failure, and system reliability is poor; A kind of is to adopt the CPU of three PLC as triplex level redundancy, and this mode depends on business-like PLC, and the synchronous grade between while three PLC is difficult to effectively guaranteed.
Summary of the invention
The technical matters that the present invention will solve is in order to overcome triplex level redundancy method poor reliability in the prior art, to be difficult to the defective that guarantees synchronously, triplex level redundancy control system and method thereof in a kind of process control being provided.
The present invention solves above-mentioned technical matters through following technical proposals:
Triplex level redundancy control system in a kind of process control; Its characteristics are; It comprises three separate processor; Said processor is connected through bus in twos, and this control system also comprises the output voting terminal that all is connected with said three processors, is used for the output of three processors is put to the vote as the voting input;
Wherein, said each processor includes:
One input voting module is used for each processor voting is imported in three tunnel inputs that obtain respectively;
One computing module is used for after input voting, and each processor calculates according to preset steering logic respectively, calculate finish after, separately cycle count is added 1;
One synchronous processing module, being used for the primary processor is that benchmark compares, primary processor is after calculating completion; Synchronizing information is sent to from processor, after accomplishing from processor calculating, the cycle count of self and the cycle count of primary processor are compared; If not in the scope that deviation allows; Then the result of calculation of self is invalid, and with the cycle count of primary processor device, state value cycle count and the state value as self, is used for calculating next time.
Preferably, this system also comprises the signal output module that links to each other with output voting terminal, be used for the output voting after, voting result is exported through output channel.
Preferably, input voting module switch amount adopts three to select two voting principle, if one tunnel input is invalid, the two-way input all is 1 or all is 0 in addition, produces effectively output so: be 1 or 0; If in the two-way input, the one tunnel is 1, the one tunnel to be 0, does not then satisfy three and selects two principles, can not produce effective output.
Preferably, output voting terminal switch amount adopts three to select two voting principle, if the calculating of three processors is all effective, selects two principle to put to the vote according to three; If have only the calculating of two processors effective in three processors, if then the result of calculation of two processors is identical, then by identical result's output; If the result of calculation of two processors is inequality, then do not export; If have only the calculating of a processor effective in three processors, then do not export.
Preferably, input voting module is selected one+Gao Xuan/low choosing to analog quantity through three, or average puts to the vote, and promptly in three tunnel inputs, selects maximal value or minimum value as effective input value, or with the mean value of three tunnel inputs as effective input value.
Preferably, output voting terminal selects one+Gao Xuan/low choosing to analog quantity through three, or average puts to the vote, if the calculating of three processors is all effective, select one+Gao Xuan/low choosing according to three, or the principle of average is put to the vote; If have only the calculating of two processors effective in three processors,, get the high value/low value or the average of two processor result of calculations and export as effective then according to the voting principle; If have only the calculating of a processor effective in three processors, then do not export.
Another technical scheme of the present invention is: a kind of control method of above-mentioned system, and its characteristics are that it may further comprise the steps:
After S1, signal inserted, Fen Sanlu was input to said three processors, after each processor is received input, carries out information interaction through bus, makes each processor all obtain 3 input values;
S2, each processor are imported voting respectively to obtaining three tunnel inputs;
After S3, the input voting, each processor calculates according to preset steering logic respectively, calculate finish after, separately cycle count is added 1;
S4, synchronous processing are that benchmark compares with the primary processor, and primary processor sends to synchronizing information from processor after calculating completion; After processor calculating completion; The cycle count of self and the cycle count of primary processor are compared, if not in the scope that deviation allows, then the result of calculation of self is invalid; And, be used for calculating next time with the cycle count of master server, state value cycle count and state value as self;
S5, output voting terminal are put to the vote as the voting input to the output of three processors;
S6, signal output module are exported voting result after the output voting through output channel.
Preferably, input voting module switch amount adopts three to select two voting principle among the step S2, if one tunnel input is invalid, the two-way input all is 1 or all is 0 in addition, produces effectively output so: be 1 or 0; If in the two-way input, the one tunnel is 1, the one tunnel to be 0, does not then satisfy three and selects two principles, can not produce effective output.
Preferably, output voting terminal switch amount adopts three to select two voting principle among the step S5, if the calculating of three processors is all effective, selects two principle to put to the vote according to three; If have only the calculating of two processors effective in three processors, if then the result of calculation of two processors is identical, then by identical result's output; If the result of calculation of two processors is inequality, then do not export; If have only the calculating of a processor effective in three processors, then do not export.
Preferably, input voting module is selected one+Gao Xuan/low choosing to analog quantity through three among the step S2, or average puts to the vote, and promptly in three tunnel inputs, selects maximal value or minimum value as effective input value, or with the mean value of three tunnel inputs as effective input value.
Preferably, output voting terminal selects one+Gao Xuan/low choosing to analog quantity through three among the step S5, or average puts to the vote, if the calculating of three processors is all effective, select one+Gao Xuan/low choosing according to three, or the principle of average is put to the vote; If have only the calculating of two processors effective in three processors,, get the high value/low value or the average of two processor result of calculations and export as effective then according to the voting principle; If have only the calculating of a processor effective in three processors, then do not export.
Preferably; Primary processor and from the priority of each processor at first relatively of the switching between the processor, the highest processor of priority is as primary processor, if a plurality of processor has identical priority; Then carry out node number relatively, the processor that node number is low obtains ownership.
Preferably, priority is divided according to the processor current states, comprises communication state, the I/O state, and priority is divided into a plurality of ranks, if network communication is interrupted or the I/O status error, then processor will be demoted.
Preferably, node number is the unique identifying number for processor distribution, and different processors has different identification numbers.
Positive progressive effect of the present invention is: triplex level redundancy controlling mechanism of the present invention, guarantee in the high security occasion, as: the work that occasions such as nuclear power, control system can be reliable, safe.The present invention sets up the perfect triplex level redundancy architecture of a cover, utilizes synchronization mechanism, voting mechanism, principal and subordinate's handover mechanism to guarantee high reliability, the high security of system.Particularly, adopt the triplex level redundancy of three independent processors assurance systems, guaranteed the reliability of system.The cycle of operation of adopting accurate hardware time pulse to trigger processor, guaranteed the synchronism of calculating.Principal and subordinate processor calculates the synchronous fault-tolerant coordination system, guarantees that each processor always is in normal computing rhythm, thereby guarantees the rationality of output.Voting machine is all adopted in the input or the output of processor that are processor, puts to the vote according to the voting principle, guarantees that input and output all are reliable, reasonable, safe and effective, thereby has guaranteed the security of system.
Description of drawings
Fig. 1 is the system assumption diagram of triplex level redundancy control system of the present invention.
Fig. 2 is the process flow diagram of triplex level redundancy control method of the present invention.
Fig. 3 is the synoptic diagram of triplex level redundancy voting mechanism of the present invention.
Fig. 4 is the synoptic diagram of triplex level redundancy synchronization mechanism of the present invention.
Fig. 5 is the synoptic diagram of triplex level redundancy principal and subordinate's handover mechanism of the present invention.
Embodiment
Provide preferred embodiment of the present invention below in conjunction with accompanying drawing, to specify technical scheme of the present invention.
One, the architecture of at first introducing triplex level redundancy control system of the present invention as shown in Figure 1.
1) triplex level redundancy adopts three separate processor to carry out parallel processing.Like this, the one tunnel is not all right, also can work normally in other several roads.
2) carry out communication and message exchange through interconnective bus (for example TriBus) between three processors.
3) same input is divided into three the tunnel simultaneously; Gathered by three processors, three processors carry out exchanges data through TriBus, make each processor all obtain three sampled values; Each processor according to after the voting mechanism stated import voting, obtain reliable input value.For instance, the value of collection can be rotating speed, pressure or temperature etc.
4) each processor calculates according to input value and steering logic, obtains output valve, in calculating process, is worth between each processor, state synchronization guarantees to obtain reliable, rational output valve, states behind the synchronization mechanism.The steering logic is here decided according to the requirement of system self; Such as being pid algorithm or the like, for example in the boiler control, when pressure surpasses certain value; Calculate output valve according to certain formula or algorithm, the valve of boiler is passed in and out control of gas or the like.
5) output of each processor after the output voting, is exported final output valve to control port.The voting terminal is a module separate with each processor among the figure, the symbology signal of right ends among the figure.
Two, the control method of triplex level redundancy control system
At first, the basic thought of triplex level redundancy control method is in the present embodiment: same input signal is divided into three the road and is input to three separate processor simultaneously; TriBus through special use between three processors carries out information interaction.Each processor is imported voting to input signal separately; Carry out synchronous processing between three processors; Signal output is carried out in three tunnel outputs of three processors after the output voting.
Embodiment 1
Be example to be input as switching value below, specify the treatment scheme that signal input, input voting, synchronous processing, output voting, signal among the present invention are exported.
As shown in Figure 2, may further comprise the steps generally: signal input, input voting, computing, synchronous processing, output voting, signal output.
1, signal input, after the switching value signal inserted, Fen Sanlu was input to processor A, processor B, processor C, after each processor is received input, carries out information interaction through the TriBus bus, makes each processor all obtain 3 input values.
2, input voting, each processor is imported voting respectively to obtaining three tunnel inputs.Switching value selects two to put to the vote through three, and promptly in three tunnel inputs, if there are 2 tunnel inputs to be all 1 or 0, this value is effective input value so.Details are as follows to voting here, like Fig. 3.
Voting promptly is from the input of participating in voting, obtains the most reasonably value conduct voting output according to voting rule.The voting of triplex level redundancy is divided into input voting and output voting.The input voting refers to the input of processor is put to the vote; The output voting refers to the output of three processors is put to the vote as the voting input.The state input that switch input in the present embodiment is meant open and close or opens, stops, its input value is 0 or 1.Adopt three to select two voting formula for switch input present embodiment, also can be configured according to engine request.Voting is based upon on the basis that voting machine effectively imported, if can not effectively be imported, voting machine can't effectively be decided by vote output, will not export.Switch amount is selected under two the voting principle three, if one tunnel input is invalid, the two-way input all is 1 or all is 0 in addition, can produce effective output so: be 1 or 0; If in the two-way input, the one tunnel for being 1, the one tunnel to be 0, then satisfied three do not select two principles, can not produce effective output.
3, after the computing, input voting, each processor calculates according to calculatings/steering logic respectively, calculate end after, separately cycle count is added 1.
4, synchronous processing, synchronous processing are that benchmark compares with the primary processor.Be described below:
Primary processor sends to synchronizing information from processor after calculating completion, and synchronizing information comprises: cycle count, result of calculation, state value etc.
After processor calculating completion; The cycle count of self and the cycle count of primary processor are compared; If not in the scope that deviation allows; Then the result of calculation of self is invalid, and with the cycle count of primary processor, state value cycle count and the state value as self, is used for calculating next time.It is as shown in Figure 4 that to introduce synchronization mechanism in detail following.
1), produce the timing pip of 50ms from hardware, guarantee that the calculating of each processor is synchronous, when receiving the hardware timing pip first, each processor begins to calculate simultaneously.Wherein, before calculating, in CPUA, B, C, have the input voting to carry out, the CPU here that is to say processor.
2) calculate, at every turn and finish, each processor all increases 1 with the cycle count of oneself.
3), after primary processor calculate to finish, send synchronizing information from processor, comprising: cycle count, calculated value, state (being intermediate variable, intermediateness etc.) etc. to all the other two.
4), collect the synchronizing information that primary processor sends from processor.
5), from processor after self calculate to accomplish, compare with self the cycle count of cycle count and primary processor transmission.If the cycle count deviation is in allowed limits, think that then from the calculating of processor and primary processor be synchronous, then result of calculation is effectively, can participate in voting; Occur leading or hysteresis if the cycle count deviation not in allowed limits, is then thought from the calculating of processor, its result of calculation is invalid, can not participate in voting.
For instance, the cycle count of each CPU is 1 when beginning to calculate, and each then calculating finished; Each processor all increases 1 with the cycle count of oneself; But each CPU might receive unexpected interference and influence in computation process, will cause this moment final cycle count different, is 10 such as the cycle count of CPU A; And B and C be respectively 12 and 9, deviation has just appearred in this moment.That is to say, begin simultaneously though calculate, is that the meeting appearance is nonsynchronous in the computation process.
5, output voting if the calculating of three processors is all effective, selects two principle to put to the vote according to three.If have only the calculating of two processors effective in three processors, if then the result of calculation of two processors is identical, then by identical result's output; If the result of calculation of two processors is inequality, then do not export.If have only the calculating of a processor effective in three processors, then do not export.
6, signal output after the output voting, is exported voting result through output channel.
There is principal and subordinate's branch in three processors of triplex level redundancy control system, and the period ratio in synchronizing process is that the cycle count with primary processor is a benchmark, simultaneously primary processor calculate finish after, synchronizing information is sent to from processor, discuss above.More than be to select a processor as primary processor, all the other two conducts are from the situation of processor.But also can between the three, switch, the switching between the principal and subordinate, as shown in Figure 5, based on two principles promptly: priority and node number.
Priority is to divide according to the processor current states, comprising: communication state, I/O state etc.Can be divided into a plurality of ranks, as: the 0-7 level, 0 is highest, 7 is lowermost level.0 expression processor fully normally has no fault.If network communication interruption, I/O mistake etc., then processor will be demoted.
Node number is the unique identifying number for processor distribution, and different processors has different identification numbers.
The handover mechanism of processor is following:
The priority of each processor at first relatively, the highest processor of priority if exist a plurality of processors to have under the situation of identical highest level, then need carry out node number relatively as primary processor.
If a plurality of processors have identical priority, then carry out node number relatively, the processor that node number is low obtains ownership.
Embodiment 2
Be example to be input as analog quantity below, specify the treatment scheme that signal input, input voting, synchronous processing, output voting, signal among the present invention are exported.
As shown in Figure 2, may further comprise the steps generally: signal input, input voting, computing, synchronous processing, output voting, signal output.
1, signal input, after analog signals inserted, Fen Sanlu was input to processor A, processor B, processor C, after each processor is received input, carries out information interaction through the TriBus bus, makes each processor all obtain 3 input values.
2, input voting, each processor is imported voting respectively to obtaining three tunnel inputs.Analog quantity is selected one+Gao Xuan/low choosing through three, or average puts to the vote, and promptly in three tunnel inputs, selects maximal value or minimum value as effective input value, or with the mean value of three tunnel inputs as effective input value.Analog input refers to the input of engineering values such as flow, temperature, pressure, and its input value is integer or decimal.Adopt three to select mode+Gao Xuan/low voting formula that selects of one to analog quantity, or adopt the voting formula of average.As far as analog quantity, select under the voting principle of one voting principle or average three, if any one tunnel input is invalid, then can not produce effective output.
3, after the computing, input voting, each processor calculates according to calculatings/steering logic respectively, calculate end after, separately cycle count is added 1.
4, synchronous processing, synchronous processing are that benchmark compares with the primary processor.Be described below:
Primary processor sends to synchronizing information from processor after calculating completion, and synchronizing information comprises: cycle count, result of calculation, state value etc.
After processor calculating completion; The cycle count of self and the cycle count of primary processor are compared; If not in the scope that deviation allows; Then the result of calculation of self is invalid, and with the cycle count of master server, state value cycle count and the state value as self, is used for calculating next time.
5, output voting, if the calculating of three processors is all effective, foundation three is selected one+Gao Xuan/low choosing, or the principle of average is put to the vote.If have only the calculating of two processors effective in three processors,, get the high value/low value or the average of two processor result of calculations and export as effective then according to the voting principle; If the result of calculation of two processors is invalid, then do not export.If have only the calculating of a processor effective in three processors, then do not export.
6, signal output after the output voting, is exported voting result through output channel.
Voting mechanism in the present embodiment is different like embodiment 1 as stated, and synchronization mechanism, principal and subordinate's handover mechanism and embodiment 1 are basic identical, does not do at this and gives unnecessary details.
Though more than described embodiment of the present invention, it will be understood by those of skill in the art that these only illustrate, protection scope of the present invention is limited appended claims.Those skilled in the art can make numerous variations or modification to these embodiments under the prerequisite that does not deviate from principle of the present invention and essence, but these changes and modification all fall into protection scope of the present invention.
Claims (14)
1. the triplex level redundancy control system in the process control; It is characterized in that; It comprises three separate processor; Said processor is connected through bus in twos, and this control system also comprises the output voting terminal that all is connected with said three processors, is used for the output of three processors is put to the vote as the voting input;
Wherein, said each processor includes:
One input voting module is used for each processor voting is imported in three tunnel inputs that obtain respectively;
One computing module is used for after input voting, and each processor calculates according to preset steering logic respectively, calculate finish after, separately cycle count is added 1;
One synchronous processing module, being used for the primary processor is that benchmark compares, primary processor is after calculating completion; Synchronizing information is sent to from processor, after accomplishing from processor calculating, the cycle count of self and the cycle count of primary processor are compared; If not in the scope that deviation allows; Then the result of calculation of self is invalid, and with the cycle count of primary processor device, state value cycle count and the state value as self, is used for calculating next time.
2. triplex level redundancy control system as claimed in claim 1 is characterized in that, this system also comprises the signal output module that links to each other with output voting terminal, be used for the output voting after, voting result is exported through output channel.
3. triplex level redundancy control system as claimed in claim 1 is characterized in that, input voting module switch amount adopts three to select two voting principle, if one tunnel input is invalid, the two-way input all is 1 or all is 0 in addition, produces effectively output so: be 1 or 0; If in the two-way input, the one tunnel is 1, the one tunnel to be 0, does not then satisfy three and selects two principles, can not produce effective output.
4. triplex level redundancy control system as claimed in claim 1 is characterized in that, output voting terminal switch amount adopts three to select two voting principle, if the calculating of three processors is all effective, selects two principle to put to the vote according to three; If have only the calculating of two processors effective in three processors, if then the result of calculation of two processors is identical, then by identical result's output; If the result of calculation of two processors is inequality, then do not export; If have only the calculating of a processor effective in three processors, then do not export.
5. triplex level redundancy control system as claimed in claim 4; It is characterized in that; Input voting module is selected one+Gao Xuan/low choosing to analog quantity through three, or average puts to the vote, promptly in three tunnel inputs; Select maximal value or minimum value as effective input value, or with the mean value of three tunnel inputs as effective input value.
6. triplex level redundancy control system as claimed in claim 1 is characterized in that, output voting terminal selects one+Gao Xuan/low choosing to analog quantity through three; Or average is put to the vote; If the calculating of three processors is all effective, foundation three is selected one+Gao Xuan/low choosing, or the principle of average is put to the vote; If have only the calculating of two processors effective in three processors,, get the high value/low value or the average of two processor result of calculations and export as effective then according to the voting principle; If have only the calculating of a processor effective in three processors, then do not export.
7. the control method of the system of claim 1 is characterized in that, it may further comprise the steps:
After S1, signal inserted, Fen Sanlu was input to said three processors, after each processor is received input, carries out information interaction through bus, makes each processor all obtain 3 input values;
S2, each processor are imported voting respectively to obtaining three tunnel inputs;
After S3, the input voting, each processor calculates according to preset steering logic respectively, calculate finish after, separately cycle count is added 1;
S4, synchronous processing are that benchmark compares with the primary processor, and primary processor sends to synchronizing information from processor after calculating completion; After processor calculating completion; The cycle count of self and the cycle count of primary processor are compared, if not in the scope that deviation allows, then the result of calculation of self is invalid; And, be used for calculating next time with the cycle count of master server, state value cycle count and state value as self;
S5, output voting terminal are put to the vote as the voting input to the output of three processors;
S6, signal output module are exported voting result after the output voting through output channel.
8. control method as claimed in claim 7 is characterized in that, input voting module switch amount adopts three to select two voting principle among the step S2, if one tunnel input is invalid, the two-way input all is 1 or all is 0 in addition, produces effectively output so: be 1 or 0; If in the two-way input, the one tunnel is 1, the one tunnel to be 0, does not then satisfy three and selects two principles, can not produce effective output.
9. control method as claimed in claim 7 is characterized in that, output voting terminal switch amount adopts three to select two voting principle among the step S5, if the calculating of three processors is all effective, selects two principle to put to the vote according to three; If have only the calculating of two processors effective in three processors, if then the result of calculation of two processors is identical, then by identical result's output; If the result of calculation of two processors is inequality, then do not export; If have only the calculating of a processor effective in three processors, then do not export.
10. control method as claimed in claim 7; It is characterized in that; Input voting module is selected one+Gao Xuan/low choosing to analog quantity through three among the step S2, or average puts to the vote, promptly in three tunnel inputs; Select maximal value or minimum value as effective input value, or with the mean value of three tunnel inputs as effective input value.
11. control method as claimed in claim 7 is characterized in that, output voting terminal selects one+Gao Xuan/low choosing to analog quantity through three among the step S5; Or average is put to the vote; If the calculating of three processors is all effective, foundation three is selected one+Gao Xuan/low choosing, or the principle of average is put to the vote; If have only the calculating of two processors effective in three processors,, get the high value/low value or the average of two processor result of calculations and export as effective then according to the voting principle; If have only the calculating of a processor effective in three processors, then do not export.
12. control method as claimed in claim 7; It is characterized in that; Primary processor and from the priority of each processor at first relatively of the switching between the processor, the highest processor of priority is as primary processor, if a plurality of processor has identical priority; Then carry out node number relatively, the processor that node number is low obtains ownership.
13. control method as claimed in claim 12 is characterized in that, priority is divided according to the processor current states; Comprise communication state, the I/O state, priority is divided into a plurality of ranks; If network communication is interrupted or the I/O status error, then processor will be demoted.
14. control method as claimed in claim 13 is characterized in that, node number is the unique identifying number for processor distribution, and different processors has different identification numbers.
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