CN102621395A - Capacitor measurement circuit structure with charge transfer circuit - Google Patents

Capacitor measurement circuit structure with charge transfer circuit Download PDF

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Publication number
CN102621395A
CN102621395A CN2011100355626A CN201110035562A CN102621395A CN 102621395 A CN102621395 A CN 102621395A CN 2011100355626 A CN2011100355626 A CN 2011100355626A CN 201110035562 A CN201110035562 A CN 201110035562A CN 102621395 A CN102621395 A CN 102621395A
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China
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electrically connected
input end
output terminal
charge transfer
selected cell
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CN2011100355626A
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Chinese (zh)
Inventor
张宝兴
连政清
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RUIYI ELECTRONIC CO Ltd
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RUIYI ELECTRONIC CO Ltd
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Priority to CN2011100355626A priority Critical patent/CN102621395A/en
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Abstract

The invention provides a capacitor measurement circuit structure with a charge transfer circuit. The structure comprises a selection module, a signal processing control module and a charge transfer module. The selection module is used for electrically connecting with a capacitor to be measured and enabling the capacitor to be measured to be electrically connected with the signal processing control module selectively. The charge transfer module receives a control signal outputted by the signal processing control module so as to adjust the output voltage of an adjustable voltage supply unit in the charge transfer module and enable a voltage comparison signal outputted by the signal processing control module to approach a specific value gradually. Thereby, through transferring a load of the capacitor to be measured to a sampling capacitor in the charge transfer circuit, an efficacy of obtaining a capacitance value of the capacitor to be measured or obtaining the capacitance value change of the capacitor to be measured is achieved.

Description

Electric capacitance measurement circuit structure with charge transfer circuit
Technical field
The present invention relates to a kind of electric capacitance measurement circuit structure, particularly relate to a kind of electric capacitance measurement circuit structure with charge transfer circuit.
Background technology
Along with development of science and technology, common people can often touch touch control type screen, touch switch or the like product with the touch control manner operation in daily life.Wherein, can use capacitance-type switch mostly, and whether the capacitance size of capacitance-type switch through the induction testing capacitance changes, and then judge whether approaching the user is and control by the product of touch control manner operation.Existing technology is used the capacitance variation that the electric capacitance measurement circuit comes sense capacitance formula switch mostly, to reach corresponding control in response to user's operation.
Developed at present the electric capacitance measurement circuit that to utilize charge transfer technology; Wherein in charge transfer technology, probably be divided into two stages such as charging stage and charge transfer phase; Be that a testing capacitance and a voltage source are electrically connected in the charging stage, so that electric charge can be accumulate in the testing capacitance.And in charge transfer phase, the electric charge that is stored in the testing capacitance is released in the known capacitance.Above-mentioned two stages can repeat repeatedly, and to improve the voltage of known capacitance, the quantity of electric charge that at every turn is transferred to known capacitance afterwards can reduce with the index ratio.Then, can the voltage and a reference voltage of known capacitance be made comparisons, utilize comparer and/or analog-digital converter again and cooperate associated processing circuit, with capacitance or the capacitance variations that obtains testing capacitance.
In order to measure the capacitance of testing capacitance more accurately or whether the capacitance of learning testing capacitance changes; All circles are devoted to develop the electric capacitance measurement circuit invariably, and how to design one of real direction of constantly endeavouring for industry of electric capacitance measurement circuit that cost is lower, highly sensitive and reaction velocity is fast.
Summary of the invention
The objective of the invention is to; A kind of electric capacitance measurement circuit structure with charge transfer circuit of new structure is provided; Technical matters to be solved is to make it make the electric charge in the testing capacitance be transferred to the sampling capacitor in the charge transfer circuit by charge transfer circuit; And through signal Processing control module generation control signal, with the voltage of adjustable voltage feeding unit generation in the adjusting charge transfer circuit, and then the voltage difference at right property ground adjustment testing capacitance two ends; Obtain the capacitance of testing capacitance whereby or learn that whether the capacitance of testing capacitance changes, and is very suitable for practicality.
Another object of the present invention is to; A kind of multiplex's electric capacitance measurement circuit structure with charge transfer circuit of new structure is provided; Technical matters to be solved is to make it can after the primary signal processing module, be connected in series multistage secondary signal processing module; The reaction velocity of the electric capacitance measurement of the speed of faster signal processing, and then raising whereby circuit structure, thus be suitable for practicality more.
The object of the invention and solve its technical matters and adopt following technical scheme to realize.A kind of electric capacitance measurement circuit structure according to the present invention's proposition with charge transfer circuit; In order to detect at least one testing capacitance; It comprises: one selects module; It comprises: one first selected cell and one second selected cell, and wherein this testing capacitance is electrically connected between this first selected cell and this second selected cell; One signal Processing control module, it comprises: a voltage comparison unit, it has: a first input end, it is series at an end of this first selected cell; One second input end, it is series at an end of this second selected cell; And one first output terminal, it is in order to export a voltage comparison signal; One first switch, it is electrically connected between this first input end and this second input end; And a control signal generating unit, it has: one the 3rd input end, and it is electrically connected at this first output terminal to receive this voltage comparison signal; And one second output terminal and one the 3rd output terminal, it is in order to export a control signal respectively; And an electric charge shift module, it comprises: one first charge transfer circuit, and it comprises: one first adjustable voltage feeding unit, its input end are electrically connected at this second output terminal in order to receive this control signal; And one first sampling capacitor, it has: one first end points, and it is electrically connected at the output terminal of this first adjustable voltage feeding unit; And one second end points, it is electrically connected at this first input end; And one second charge transfer circuit, it comprises: one second adjustable voltage feeding unit, its input end are electrically connected at the 3rd output terminal in order to receive this control signal; And one second sampling capacitor, it has: one the 3rd end points, and it is electrically connected at the output terminal of this second adjustable voltage feeding unit; And one the 4th end points, it is electrically connected at this second input end; Wherein, this control signal generating unit reads this voltage comparison signal at N during the cycle, to determine this control signal, makes this voltage comparison signal during cycle more level off to a particular value than this N in N+1 during the cycle whereby, and wherein N is a positive integer.
The object of the invention and solve its technical matters and also can adopt following technical measures further to realize.
Aforesaid electric capacitance measurement circuit structure with charge transfer circuit; The wherein said first adjustable voltage feeding unit is one first resistance-type D/A conversion circuit; Its voltage input end receives one first upper voltage limit and one first lower voltage limit; And the control end of this first resistance-type D/A conversion circuit is electrically connected at this second output terminal and controls to receive this control signal; So that this first resistance-type D/A conversion circuit is exported one first aanalogvoltage; And this output terminal of this first resistance-type D/A conversion circuit is electrically connected at this first end points by a second switch selectivity, and this first end points is electrically connected at one first reference voltage source by one the 3rd switch selectivity again, to receive one first reference voltage.
Aforesaid electric capacitance measurement circuit structure with charge transfer circuit; The wherein said second adjustable voltage feeding unit is one second resistance-type D/A conversion circuit; Its voltage input end receives one second upper voltage limit and one second lower voltage limit; And the control end of this second resistance-type D/A conversion circuit is electrically connected at the 3rd output terminal and controls to receive this control signal; So that this second resistance-type D/A conversion circuit is exported one second aanalogvoltage; And this output terminal of this second resistance-type D/A conversion circuit is electrically connected at the 3rd end points by one the 4th switch selectivity, and the 3rd end points is electrically connected at one second reference voltage source by one the 5th switch selectivity again, to receive one second reference voltage.
Aforesaid electric capacitance measurement circuit structure with charge transfer circuit, wherein said first selected cell comprises: one the 6th switch, it is serially connected with this first input end; And one minion close, it is serially connected with the 6th switch; And this second selected cell comprises: an octavo is closed, and it is serially connected with this second input end; And one the 9th switch; It is serially connected with this octavo and closes; Wherein an end of this testing capacitance is electrically connected at the first node between the 6th switch and this minion pass, and the other end of this testing capacitance is electrically connected at the Section Point between this octavo pass and the 9th switch.
Aforesaid electric capacitance measurement circuit structure with charge transfer circuit, wherein said first selected cell and this second selected cell are respectively a multiplexer, are electrically connected at this testing capacitance with selectivity.
Aforesaid electric capacitance measurement circuit structure with charge transfer circuit, wherein said signal Processing control module further comprises at least one analog signal processing circuit, it is series between this first switch and this voltage comparison unit.
Aforesaid electric capacitance measurement circuit structure with charge transfer circuit, wherein said analog signal processing circuit comprises: an analog wave filter, its input end are serially connected with this first switch; And an adjustable sequencing amplifier, its input end is serially connected with the output terminal of this analog wave filter, and the output terminal of this is adjustable sequencing amplifier is serially connected with this voltage comparison unit.
Aforesaid electric capacitance measurement circuit structure with charge transfer circuit, wherein said analog signal processing circuit comprises: an adjustable sequencing amplifier, its input end is serially connected with this first switch; And an analog wave filter, its input end is serially connected with the output terminal of this adjustable sequencing amplifier, and the output terminal of this analog wave filter is serially connected with this voltage comparison unit.
Aforesaid electric capacitance measurement circuit structure with charge transfer circuit, wherein said control signal generating unit are a flash type (Flash) analog-digital converter or a successive approximation (SAR) analog-digital converter.
Aforesaid electric capacitance measurement circuit structure with charge transfer circuit, it further comprises a control module, its this first selected cell of control and this second selected cell optionally electrically connect this testing capacitance with this first input end and this second input end.
The object of the invention and solve its technical matters and also adopt following technical scheme to realize.A kind of multiplex's electric capacitance measurement circuit structure according to the present invention's proposition with charge transfer circuit; In order to detect at least one testing capacitance; It comprises: one first selects module; It comprises: one first selected cell and one second selected cell, and wherein this testing capacitance is electrically connected between this first selected cell and this second selected cell; One primary signal processing module, it comprises: a primary signal processing and control module, its input end and this first selected cell and this second selected cell electrically connect, and its output terminal is exported a primary control signal; And an elementary electric charge shift module, its input end receives this primary control signal, and its output terminal is electrically connected at the input end of this primary signal processing and control module; And at least one secondary signal processing module; And each this secondary signal processing module is connected in series in regular turn each other; This secondary signal processing module of the first order is serially connected with this primary signal processing module in those secondary signal processing modules; Wherein each this secondary signal processing module comprises: one second selects module, its input end to be electrically connected at the input end of a level signal Processing control module of this primary signal processing and control module or the previous stage of previous stage; This secondary signal processing and control module, its input end and this second selection module electrically connect, and level control signal of its output terminal output; And a level electric charge shift module, its input end receives this primary control signal of previous stage output or this secondary control signal of previous stage output, and the output terminal of this secondary electric charge shift module is electrically connected at the input end of this secondary signal processing and control module.
The object of the invention and solve its technical matters and also can adopt following technical measures further to realize.
Aforesaid multiplex's electric capacitance measurement circuit structure with charge transfer circuit, wherein said primary signal processing and control module comprises: a primary voltage comparing unit, it has: a first input end, it is electrically connected at an end of this first selected cell; One second input end, it is series at an end of this second selected cell; And one first output terminal, it is in order to export one first voltage comparison signal; One first switch, it is electrically connected between this first input end and this second input end; And a primary control signal generation unit, it has: one the 3rd input end, and it is electrically connected at this first output terminal to receive this first voltage comparison signal; And one second output terminal and one the 3rd output terminal, it is in order to export this primary control signal respectively.
Aforesaid multiplex's electric capacitance measurement circuit structure with charge transfer circuit, wherein said primary signal processing and control module further comprises at least one first analog signal processing circuit, it is series between this first switch and this primary voltage comparing unit.
Aforesaid multiplex's electric capacitance measurement circuit structure with charge transfer circuit, wherein said first analog signal processing circuit comprises: one first analog wave filter, its input end are serially connected with this first switch; And one first adjustable sequencing amplifier, its input end is serially connected with the output terminal of this first analog wave filter, and the output terminal of this first adjustable sequencing amplifier is serially connected with this primary voltage comparing unit.
Aforesaid multiplex's electric capacitance measurement circuit structure with charge transfer circuit, wherein said first analog signal processing circuit comprises: one first adjustable sequencing amplifier, its input end is serially connected with this first switch; And one first analog wave filter, its input end is serially connected with the output terminal of this first adjustable sequencing amplifier, and the output terminal of this first analog wave filter is serially connected with this primary voltage comparing unit.
Aforesaid multiplex's electric capacitance measurement circuit structure with charge transfer circuit, wherein said primary control signal generation unit are a flash type (Flash) analog-digital converter or a successive approximation (SAR) analog-digital converter.
Aforesaid multiplex's electric capacitance measurement circuit structure with charge transfer circuit; Wherein said elementary electric charge shift module; Comprise: one first charge transfer circuit; It comprises: one first adjustable voltage feeding unit, its input end are electrically connected at this second output terminal in order to receive this primary control signal; And one first sampling capacitor, it has: one first end points, and it is electrically connected at the output terminal of this first adjustable voltage feeding unit; And one second end points, it is electrically connected at this first input end; And one second charge transfer circuit, it comprises: one second adjustable voltage feeding unit, its input end are electrically connected at the 3rd output terminal in order to receive this primary control signal; And one second sampling capacitor, it has: one the 3rd end points, and it is electrically connected at the output terminal of this second adjustable voltage feeding unit; And one the 4th end points, it is electrically connected at this second input end.
Aforesaid multiplex's electric capacitance measurement circuit structure with charge transfer circuit; The wherein said first adjustable voltage feeding unit is one first resistance-type D/A conversion circuit; Its voltage input end receives one first upper voltage limit and one first lower voltage limit; And the control end of this first resistance-type D/A conversion circuit is electrically connected at this second output terminal and controls to receive this primary control signal; So that this first resistance-type D/A conversion circuit is exported one first aanalogvoltage; Not only this output terminal of this first resistance-type D/A conversion circuit but also be electrically connected at this first end points by a second switch selectivity, and this first end points is electrically connected at one first reference voltage source by one the 3rd switch selectivity again, to receive one first reference voltage; And this second adjustable voltage feeding unit is one second resistance-type D/A conversion circuit; Its voltage input end receives one second upper voltage limit and one second lower voltage limit; And the control end of this second resistance-type D/A conversion circuit is electrically connected at the 3rd output terminal and controls to receive this primary control signal; So that this second resistance-type D/A conversion circuit is exported one second aanalogvoltage; And this output terminal of this second resistance-type D/A conversion circuit is electrically connected at the 3rd end points by one the 4th switch selectivity; And the 3rd end points is electrically connected at one second reference voltage source by one the 5th switch selectivity again, to receive one second reference voltage.
Aforesaid multiplex's electric capacitance measurement circuit structure with charge transfer circuit, wherein said first selected cell comprises: one the 6th switch, it is serially connected with this first input end; And one minion close, it is serially connected with the 6th switch; And this second selected cell comprises: an octavo is closed, and it is serially connected with this second input end; And one the 9th switch; It is serially connected with this octavo and closes; Wherein an end of this testing capacitance is electrically connected at the first node between the 6th switch and this minion pass, and the other end of this testing capacitance is electrically connected at the Section Point between this octavo pass and the 9th switch.
Aforesaid multiplex's electric capacitance measurement circuit structure with charge transfer circuit; Wherein said second selects module to comprise: one the 3rd selected cell and one the 4th selected cell, and be electrically connected with a transfer electric capacity between the 3rd selected cell and the 4th selected cell.
Aforesaid multiplex's electric capacitance measurement circuit structure with charge transfer circuit; Wherein in this secondary signal processing module of the first order; The 3rd selected cell is electrically connected at an end of this first selected cell, and the 4th selected cell then is electrically connected at an end of this second selected cell.
Aforesaid multiplex's electric capacitance measurement circuit structure with charge transfer circuit; In the wherein said secondary signal processing module; The 3rd selected cell is electrically connected at the 3rd selected cell of previous stage, and the 4th selected cell then is electrically connected at the 4th selected cell of previous stage.
Aforesaid multiplex's electric capacitance measurement circuit structure with charge transfer circuit, wherein each this secondary signal processing and control module comprises: a secondary voltage comparing unit, it has: a four-input terminal, it is series at an end of the 3rd selected cell; One the 5th input end, it is series at an end of the 4th selected cell; And one the 4th output terminal, it is in order to export one second voltage comparison signal; The tenth switch, it is electrically connected between this four-input terminal and the 5th input end; And a level control signal generating unit, it has: one the 6th input end, and it is electrically connected at the 4th output terminal to receive this second voltage comparison signal; And one the 5th output terminal and one the 6th output terminal, it is in order to this secondary control signal of output respectively.
Aforesaid multiplex's electric capacitance measurement circuit structure with charge transfer circuit, wherein said secondary signal processing and control module further comprises at least one second analog signal processing circuit, it is series between the tenth switch and this secondary voltage comparing unit.
Aforesaid multiplex's electric capacitance measurement circuit structure with charge transfer circuit, wherein said second analog signal processing circuit comprises: one second analog wave filter, its input end is serially connected with the tenth switch; And one second adjustable sequencing amplifier, its input end is serially connected with the output terminal of this second analog wave filter, and the output terminal of this second adjustable sequencing amplifier is serially connected with this secondary voltage comparing unit.
Aforesaid multiplex's electric capacitance measurement circuit structure with charge transfer circuit, wherein said second analog signal processing circuit comprises: one second adjustable sequencing amplifier, its input end is serially connected with the tenth switch; And one second analog wave filter, its input end is serially connected with the output terminal of this second adjustable sequencing amplifier, and the output terminal of this second analog wave filter is serially connected with this secondary voltage comparing unit.
Aforesaid multiplex's electric capacitance measurement circuit structure with charge transfer circuit, wherein said secondary control signal generating unit are a flash type (Flash) analog-digital converter or a successive approximation (SAR) analog-digital converter.
Aforesaid multiplex's electric capacitance measurement circuit structure with charge transfer circuit; This secondary electric charge shift module of the first order wherein; It comprises: a tricharged carry circuit; It comprises: one the 3rd adjustable voltage feeding unit, and its input end is electrically connected at this second output terminal, to receive this primary control signal; And one the 3rd sampling capacitor, it has: a five terminal point, and it is electrically connected at the output terminal of the 3rd adjustable voltage feeding unit; And one the 6th end points, it is electrically connected at this four-input terminal; And one the 4th charge transfer circuit, it comprises: one the 4th adjustable voltage feeding unit, and its input end is electrically connected at the 3rd output terminal, to receive this primary control signal; And one the 4th sampling capacitor, it has: one the 7th end points, and it is electrically connected at the output terminal of the 4th adjustable voltage feeding unit; And one the 8th end points, it is electrically connected at the 5th input end.
Aforesaid multiplex's electric capacitance measurement circuit structure with charge transfer circuit; Wherein except that this secondary electric charge shift module of the first order; Each this secondary charge transfer circuit of level comprises: one the 5th charge transfer circuit; It comprises: one the 5th adjustable voltage feeding unit, and its input end is electrically connected at the 5th output terminal of this secondary signal processing and control module of previous stage, to receive this secondary control signal; And one the 5th sampling capacitor, it has: one the 9th end points, and it is electrically connected at the output terminal of the 5th adjustable voltage feeding unit; And 1 the tenth end points, it is electrically connected at this four-input terminal; And one the 6th charge transfer circuit, it comprises: one the 6th adjustable voltage feeding unit, and its input end is electrically connected at the 6th output terminal of this secondary signal processing and control module of previous stage, to receive this secondary control signal; And one the 6th sampling capacitor, it has: 1 the 11 end points, and it is electrically connected at the output terminal of the 6th adjustable voltage feeding unit; And 1 the 12 end points, it is electrically connected at the 5th input end.
Aforesaid multiplex's electric capacitance measurement circuit structure with charge transfer circuit, wherein said first selected cell and this second selected cell are respectively a multiplexer, are electrically connected at this testing capacitance with selectivity.
Aforesaid multiplex's electric capacitance measurement circuit structure with charge transfer circuit; It further comprises a control module, the on off state of one the 3rd selected cell and one the 4th selected cell in its this first selected cell of control, this second selected cell and each this second selection module.
The present invention compared with prior art has tangible advantage and beneficial effect.By technique scheme, the electric capacitance measurement circuit structure that the present invention has charge transfer circuit has advantage and beneficial effect at least:
The present invention is through the voltage of its output of adjustable voltage feeding unit control, and then the voltage difference at right property ground adjustment testing capacitance two ends, can obtain the capacitance of testing capacitance whereby or whether the capacitance of learning testing capacitance changes.
The present invention is by the multistage secondary signal processing module of serial connection after the primary signal processing module, to handle and then to improve the reaction velocity of electric capacitance measurement circuit structure through multilevel signal.
In sum, the invention relates to a kind of electric capacitance measurement circuit structure with charge transfer circuit, it comprises: select module; The signal Processing control module; And electric charge shift module.Select module in order to electrically connect testing capacitance; And testing capacitance is optionally electrically connected with the signal Processing control module; And the control signal of electric charge shift module acknowledge(ment) signal processing and control module output; With the output voltage of adjustable voltage feeding unit in the adjustment electric charge shift module, and the voltage comparison signal that makes the signal Processing control module exported levels off to a certain particular value gradually.By being transferred to the sampling capacitor in the charge transfer circuit, to reach the capacitance of obtaining testing capacitance or to learn the effect of the capacitance variation of testing capacitance through electric charge with testing capacitance.The present invention has obvious improvement technically, and has tangible good effect, really is the new design of a novelty, progress, practicality.
Above-mentioned explanation only is the general introduction of technical scheme of the present invention; Understand technological means of the present invention in order can more to know; And can implement according to the content of instructions, and for let of the present invention above-mentioned with other purposes, feature and advantage can be more obviously understandable, below special act preferred embodiment; And conjunction with figs., specify as follows.
Description of drawings
Figure 1A is a kind of synoptic diagram with electric capacitance measurement circuit structure of charge transfer circuit of first embodiment of the invention.
Figure 1B is the synoptic diagram of the electric capacitance measurement circuit structure with charge transfer circuit of another example of first embodiment of the invention.
Fig. 1 C is the synoptic diagram of the electric capacitance measurement circuit structure with charge transfer circuit of the another example of first embodiment of the invention.
Fig. 2 A is a kind of synoptic diagram with electric capacitance measurement circuit of charge transfer circuit at the circuit structure of charging stage of first embodiment of the invention.
Fig. 2 B is a kind of synoptic diagram with electric capacitance measurement circuit of charge transfer circuit at the circuit structure of charge transfer phase of first embodiment of the invention.
Fig. 3 is a kind of signal timing diagram with electric capacitance measurement circuit structure of charge transfer circuit of first embodiment of the invention.
Fig. 4 is the synoptic diagram of the voltage comparison signal of electric capacitance measurement circuit structure with charge transfer circuit of first embodiment of the invention a kind of.
Fig. 5 A is a kind of synoptic diagram with multiplex's electric capacitance measurement circuit structure of charge transfer circuit of second embodiment of the invention.
Fig. 5 B is the synoptic diagram of the multiplex's electric capacitance measurement circuit structure with charge transfer circuit of another example of second embodiment of the invention.
Fig. 5 C is the synoptic diagram of the multiplex's electric capacitance measurement circuit structure with charge transfer circuit of the another example of second embodiment of the invention.
Fig. 6 is the second embodiment of the invention synoptic diagram of the multiplex's electric capacitance measurement circuit structure with charge transfer circuit of an example again.
Fig. 7 A is the synoptic diagram of second embodiment of the invention at the circuit structure of first charging stage.
Fig. 7 B is the synoptic diagram of second embodiment of the invention at the circuit structure of first charge transfer phase.
Fig. 7 C is the synoptic diagram of second embodiment of the invention at the circuit structure of second charging stage.
Fig. 7 D is the synoptic diagram of second embodiment of the invention at the circuit structure of second charge transfer phase.
Fig. 7 E is the synoptic diagram of second embodiment of the invention at the circuit structure of the 3rd charging stage.
Fig. 7 F is the synoptic diagram of second embodiment of the invention at the circuit structure of tricharged transition phase.
Fig. 7 G is the synoptic diagram of second embodiment of the invention at the circuit structure of the 4th charging stage.
Fig. 7 H is the synoptic diagram of second embodiment of the invention at the circuit structure of the 4th charge transfer phase.
Fig. 8 is the signal timing diagram of second embodiment of the invention successive approximation simulation digital quantizer.
Fig. 9 is the signal timing diagram of second embodiment of the invention flash type analog-digital converter.
Figure 10 is the map of the signal sequence of the first embodiment of the invention and second embodiment.
10: select module 10 ': the first to select module
10 ": second selects 11: the first selected cells of module
Selected cell 13 in 12: the second: voltage source
13a: the first reference voltage source 13b: second reference voltage source
13c: 14: the three selected cells of reference voltage source
Selected cell 20 in 15: the four: the signal Processing control module
21: voltage comparison unit 22: control signal generating unit
23: analog signal processing circuit 23a: analog wave filter
23b: adjustable sequencing amplifier 30: electric charge shift module
30 ': elementary electric charge shift module 30 ": secondary electric charge shift module
31: the first charge transfer circuit 31a: the first adjustable voltage feeding unit
31b: 32: the second charge transfer circuits of the first resistance-type D/A conversion circuit
32a: the second adjustable voltage feeding unit 32b: the second resistance-type D/A conversion circuit
33: the tricharged carry circuit 33a: the 3rd adjustable voltage feeding unit
34: the four charge transfer circuit 34a: the 4th adjustable voltage feeding unit
35: the five charge transfer circuit 35a: the 5th adjustable voltage feeding unit
36: the six charge transfer circuit 36a: the 6th adjustable voltage feeding unit
40,40a, 40b, 40c, 40d: testing capacitance
41,41 ', 41 ": shift electric capacity
50: control module 60: the primary signal processing module
61: primary signal processing and control module 61a: primary voltage comparing unit
61b: 62: the first analog signal processing circuits of primary control signal generation unit
62a: the first analog wave filter 62b: the first adjustable sequencing amplifier
70,70 ', 70 ": secondary signal processing module 71: the secondary signal processing and control module
71a, 71a ', 71a ": the secondary voltage comparing unit
71b, 71b ', 71b ": secondary control signal generating unit
72: the second analog signal processing circuit 72a: the second analog wave filter
72b: the second adjustable sequencing amplifier S1: first switch
S2: second switch S3: the 3rd switch
S4: 5: the five switches of the 4th switch S
S6: 7: the minions of the 6th switch S are closed
S8: octavo is closed S9: the 9th switch
S10, S10 ', S10 ": the tenth switch S 11-S34: switch
I1: first input end I2: second input end
I3: the 3rd input end I4, I4 ': four-input terminal
I5, I5 ': the 5th input end I6: the 6th input end
O1: the first output terminal O2: second output terminal
O3: the 3rd output terminal O4: the 4th output terminal
O5: the 5th output terminal O6: the 6th output terminal
C1: the first sampling capacitor C2: second sampling capacitor
C3: the 3rd sampling capacitor C4: the 4th sampling capacitor
C5, C5 ': the 5th sampling capacitor C6, C6 ': the 6th sampling capacitor
P1: the first end points P2: second end points
P3: the 3rd end points P4: the 4th end points
P5: five terminal point P6: the 6th end points
P7: the 7th end points P8: the 8th end points
P9: the 9th end points P10: the tenth end points
P11: the 11 end points P12: the 12 end points
N1: first node N2: Section Point
Embodiment
Reach technological means and the effect that predetermined goal of the invention is taked for further setting forth the present invention; Below in conjunction with accompanying drawing and preferred embodiment; To its embodiment of electric capacitance measurement circuit structure, structure, characteristic and the effect thereof that proposes according to the present invention with charge transfer circuit, specify as after.
Relevant aforementioned and other technology contents, characteristics and effect of the present invention can be known to appear in the following detailed description that cooperates with reference to graphic preferred embodiment.Through the explanation of embodiment, when can being to reach technological means that predetermined purpose takes and effect to obtain one more deeply and concrete understanding to the present invention, yet the appended graphic usefulness that only provides reference and explanation be not to be used for the present invention is limited.
[first embodiment]
Figure 1A is a kind of synoptic diagram with electric capacitance measurement circuit structure of charge transfer circuit of first embodiment of the invention.Figure 1B is the synoptic diagram of the electric capacitance measurement circuit structure with charge transfer circuit of another example of first embodiment of the invention.Fig. 1 C is the synoptic diagram of the electric capacitance measurement circuit structure with charge transfer circuit of the another example of first embodiment of the invention.Fig. 2 A is a kind of synoptic diagram with electric capacitance measurement circuit of charge transfer circuit at the circuit structure of charging stage of first embodiment of the invention.Fig. 2 B is a kind of synoptic diagram with electric capacitance measurement circuit of charge transfer circuit at the circuit structure of charge transfer phase of first embodiment of the invention.Fig. 3 is a kind of signal timing diagram with electric capacitance measurement circuit structure of charge transfer circuit of first embodiment of the invention.Fig. 4 is the synoptic diagram of the voltage comparison signal of electric capacitance measurement circuit structure with charge transfer circuit of first embodiment of the invention a kind of.
Shown in Figure 1A, first embodiment of the invention is a kind of electric capacitance measurement circuit structure with charge transfer circuit, and it comprises: one selects module 10; One signal Processing control module 20; An and electric charge shift module 30.The electric capacitance measurement circuit structure of present embodiment can that is to say in order to detect at least one testing capacitance 40, can be in order to the capacitance size of detecting one or more electric capacity or the variation of capacitance.
Select module 10; It comprises: one first selected cell 11 and one second selected cell 12; Wherein testing capacitance 40 is electrically connected between first selected cell 11 and second selected cell 12; And an end of first selected cell 11 and second selected cell 12 electrically connects with two voltage sources 13 respectively, can make testing capacitance 40 receive the voltage of two voltage sources, 13 outputs by switching first selected cell 11 and second selected cell 12, makes testing capacitance 40 chargings whereby.Testing capacitance 40 after the charging can be electrically connected at signal Processing control module 20 by switching first selected cell 11 and second selected cell 12 again.
Signal Processing control module 20, it comprises: a voltage comparison unit 21; One first switch S 1; An and control signal generating unit 22.
Voltage comparison unit 21, it has: a first input end I1; One second input end I2; And one first output terminal O1.Wherein, First input end I1 is connected in series with an end of first selected cell 11; The second input end I2 then is connected in series with an end of second selected cell 12; And then electrically connect with testing capacitance 40, with the voltage between testing capacitance 40 two ends relatively, the first output terminal O1 then exports a voltage comparison signal in view of the above.
First switch S 1, it is electrically connected between the first input end I1 and the second input end I2 of voltage comparison unit 21, when first switch S 1 is " ON ", even win the input end I1 and the second input end I2 short circuit, eliminates the drift potential in the circuit whereby.
Control signal generating unit 22 can be a flash type (Flash) analog-digital converter or a successive approximation (SAR) analog-digital converter, and control signal generating unit 22 has: one the 3rd input end I3; One second output terminal O2; And one the 3rd output terminal O3.The 3rd input end I3 is electrically connected at the first output terminal O1 of voltage comparison unit 21, and in order to receive voltage comparison signal, then in order to export a control signal respectively, wherein control signal is a digital signal for the second output terminal O2 and the 3rd output terminal O3.Control signal generating unit 22 reads the voltage comparison signal that voltage comparison unit 21 produces at N during the cycle; With the decision control signal; And make voltage comparison signal more level off to a particular value during cycle than N during the cycle at N+1 by control signal, wherein N is a positive integer.
Electric charge shift module 30, it comprises: one first charge transfer circuit 31; And one second charge transfer circuit 32.Wherein, first charge transfer circuit 31 comprises: one first adjustable voltage feeding unit 31a; And one first sampling capacitor C1, second charge transfer circuit 32 then comprises: one second adjustable voltage feeding unit 32a; And one second sampling capacitor C2.
Shown in Figure 1B, the first adjustable voltage feeding unit 31a, it can be one first resistance-type D/A conversion circuit 31b, for example can be the trapezoidal formula digital analog converter of weighting resistor formula digital analog converter or R-2R.The voltage input end of the first resistance-type D/A conversion circuit 31b can further receive one first upper voltage limit and one first lower voltage limit, and the scope of output voltage that makes the first resistance-type D/A conversion circuit 31b is between first upper voltage limit and first lower voltage limit.The input end of the first resistance-type D/A conversion circuit 31b (being control end) is electrically connected at the second output terminal O2 of control signal generating unit 22; With the control of suspension control signal, and according to the voltage swing of its output of control signal adjustment and then export one first aanalogvoltage.
Shown in Figure 1A; The first sampling capacitor C1; It has: one first end points P1 and one second end points P2, and wherein the first end points P1 is electrically connected at the output terminal of the first adjustable voltage feeding unit 31a, and the second end points P2 then is electrically connected at the first input end I1 of voltage comparison unit 21.In other words, the first sampling capacitor C1 is electrically connected between the output terminal of first input end I1 and the first adjustable voltage feeding unit 31a of voltage comparison unit 21.
And for example shown in Figure 1B; The output terminal of the first resistance-type D/A conversion circuit 31b is electrically connected at the first end points P1 of the first sampling capacitor C1 by a second switch S2 selectivity; And the first end points P1 is electrically connected at one first reference voltage source 13a by one the 3rd switch S, 3 selectivity again, to receive one first reference voltage.That is to say, can make the first sampling capacitor C1 and the first reference voltage source 13a electrically connect or make the first sampling capacitor C1 and the first resistance-type D/A conversion circuit 31b to electrically connect by switching second switch S2 and the 3rd switch S 3.
In like manner; The second adjustable voltage feeding unit 32a; It can be one second resistance-type D/A conversion circuit 32b; Can realize by weighting resistor formula digital analog converter or the trapezoidal formula digital analog converter of R-2R equally; The voltage input end of the second resistance-type D/A conversion circuit 32b receives one second upper voltage limit and one second lower voltage limit, and the scope of the output voltage of the second resistance-type D/A conversion circuit 32b is between second upper voltage limit and second lower voltage limit.
The input end of the second adjustable voltage feeding unit 32a (being control end) is electrically connected at the 3rd output terminal O3 of control signal generating unit 22; With the control of suspension control signal, and make the second resistance-type D/A conversion circuit 32b export one second aanalogvoltage according to control signal.
Shown in Figure 1A; The second sampling capacitor C2; It has: one the 3rd end points P3 and one the 4th end points P4, and wherein the 3rd end points P3 is electrically connected at the output terminal of the second adjustable voltage feeding unit 32a, and the 4th end points P4 then is electrically connected at the second input end I2 of voltage comparison unit 21.That is to say that the second sampling capacitor C2 is electrically connected at second input end I2 of voltage comparison unit 21 and the output terminal of the second adjustable voltage feeding unit 32a.
In addition; See also shown in Figure 1B; The output terminal of the second resistance-type D/A conversion circuit 32b also can be electrically connected at the 3rd end points P3 of the second sampling capacitor C2 by one the 4th switch S, 4 selectivity; And the 3rd end points P3 is electrically connected at one second reference voltage source 13b by one the 5th switch S, 5 selectivity again, to receive one second reference voltage.That is to say, can make the second sampling capacitor C2 and the second reference voltage source 13b electrically connect or make the second sampling capacitor C2 and the second resistance-type D/A conversion circuit 32b to electrically connect by switching the 4th switch S 4 and the 5th switch S 5.
And for example shown in Figure 1B, first selected cell 11 comprises: one the 6th switch S 6 and a minion are closed S7, and second selected cell 12 comprises octavo pass S8 and one the 9th switch S 9.Wherein, the 6th switch S 6 is serially connected with the first input end I1 of voltage comparison unit 21, and minion pass S7 is serially connected with between the 6th switch S 6, the minions pass S7 and the 6th switch S 6 has a first node N1.Octavo is closed the second input end I2 that S8 is serially connected with voltage comparison unit 21; 9 of the 9th switch S are serially connected with octavo and close S8; And between the 9th switch S 9 and octavo pass S8, has a Section Point N2; And an end of testing capacitance 40 is electrically connected at first node N1, and the other end then is electrically connected at Section Point N2.
Shown in Fig. 1 C, first selected cell 11 and second selected cell 12 also can be respectively that a multiplexer can select a certain testing capacitance 40 to operate from a plurality of testing capacitances 40.That is to say, when a plurality of testing capacitance 40, can select a desire to measure or the testing capacitance 40 of detecting electrically connects with signal Processing control module 20 by multiplexer.
In addition; Signal Processing control module 20 can further include at least one analog signal processing circuit 23; It is series between first switch S 1 and the voltage comparison unit 21, can be in order to the noise in the received signal of filtering, to improve the accuracy of capacitance sensing.Analog signal processing circuit 23 comprises: an analog wave filter 23a and an adjustable sequencing amplifier 23b, wherein analog wave filter 23a and adjustable sequencing amplifier 23b be connected in series each other and serial connection sequence unrestricted.For instance; The input end of analog wave filter 23a can be serially connected with first switch S 1; And its output terminal is serially connected with the input end of adjustable sequencing amplifier 23b; The output terminal of adjustable sequencing amplifier 23b is serially connected with voltage comparison unit 21 again, that is adjustable sequencing amplifier 23b is electrically connected at (serial connection sequence is shown in Fig. 1 C) between analog wave filter 23a and the voltage comparison unit 21.Or; The input end of adjustable sequencing amplifier 23b is serially connected with first switch S 1; Its output terminal then is connected in series to the input end of analog wave filter 23a; The output terminal of analog wave filter 23a is connected in series respectively to the first input end I1 of voltage comparison unit 21 and the second input end I2 again, makes analog wave filter 23a be serially connected with (figure does not show) between adjustable sequencing amplifier 23b and the voltage comparison unit 21.
Shown in Figure 1B; The electric capacitance measurement circuit structure can further comprise a control module 50; It is in order to control first selected cell 11 and second selected cell 12; Testing capacitance 40 can be optionally electrically connected with the first input end I1 and the second input end I2, and control module 50 control first switch S 1, second switch S2, the 3rd switch S 3, the 4th switch S 4 and the 5th switch S 5 again, so that the electric capacitance measurement circuit structure can switch between charging stage and charge transfer phase.
Shown in Fig. 2 A; When the charging stage; Control module 50 makes first switch S 1, the 3rd switch S 3, the 5th switch S 5, minion close the state that S7 and the 9th switch S 9 are in " ON "; And make second switch S2, the 4th switch S 4, the 6th switch S 6 and octavo close the state that S8 is in " OFF "; Testing capacitance 40 and signal Processing control module 20 and electric charge shift module 30 (please consulting Figure 1A simultaneously) are isolated, and make the two ends of testing capacitance 40 and two voltage sources 13 electrically connect, to make testing capacitance 40 chargings through voltage source 13.In this simultaneously, electric charge shift module 30 is also isolated with signal Processing control module 20, and respectively the first sampling capacitor C1 and the second sampling capacitor C2 is charged by the first reference voltage source 13a and the second reference voltage source 13b.
Then; Shown in Fig. 2 B; At charge transfer phase; Control module 50 makes second switch S2, the 4th switch S 4, the 6th switch S 6 and octavo close S8 to be in the state of " ON ", and makes first switch S 1, the 3rd switch S 3, the 5th switch S 5, minion close the state that S7 and the 9th switch S 9 are in " OFF ".At this moment; Testing capacitance 40, the first sampling capacitor C1 and the second sampling capacitor C2 form a capacitance partial pressure loop; The first adjustable voltage feeding unit 31a and the second adjustable voltage feeding unit 32a then the control of suspension control signal generation unit 22 to this capacitance partial pressure loop bias voltage; Adjusting the bias voltage on the first sampling capacitor C1 and the second sampling capacitor C2, and then make the electric charge on the testing capacitance 40 be transferred to the first sampling capacitor C1 and the second sampling capacitor C2.
Because the electric differential pressure between the first input end I1 and the second input end I2 is the voltage difference at testing capacitance 40 two ends; Therefore the non-vanishing current potential of being exported when voltage comparison unit 21 of voltage comparison signal; When then representing still to have voltage difference between testing capacitance 40 two ends; Promptly representing the electric charge on the testing capacitance 40 not to be transferred to the first sampling capacitor C1 and the second sampling capacitor C2 as yet fully; So the control signal that control signal generating unit 22 is exported still can be adjusted the magnitude of voltage that the first adjustable voltage feeding unit 31a and the second adjustable voltage feeding unit 32a are produced, and then the voltage difference at adjustment testing capacitance 40 two ends, to reach the purpose of electric capacity detecting.
Therefore; Can be through the output voltage of the adjustment first adjustable voltage feeding unit 31a and the second adjustable voltage feeding unit 32a; To change the potential difference (PD) at testing capacitance 40 two ends; And the potential difference (PD) up to testing capacitance 40 two ends is zero or during convergence zero, the capacitance of testing capacitance 40 can calculate according to formula:
Cx＝[(Ca*Cb)/(V3-V4)]*[(Vp-Vq)/(Ca+Cb)]
Wherein, Cx is the capacitance of testing capacitance 40; Ca and Cb are respectively the capacitance of the first sampling capacitor C1 and the second sampling capacitor C2; V3 and V4 are respectively the magnitude of voltage of testing capacitance 40 two ends two voltage sources 13; And Vp and Vq are respectively the magnitude of voltage (i.e. the output voltage values of the first adjustable voltage feeding unit 31a and the second adjustable voltage feeding unit 32a) of the first end points P1 and the 3rd end points P3.
As shown in Figure 3; And please consult Figure 1A simultaneously; In the charging stage; Control module 50 makes first switch S 1, the 3rd switch S 3, the 5th switch S 5, minion close the state that S7 and the 9th switch S 9 are in " ON "; Control signal generating unit 22 promptly receives the control of start signal STAR, and when getting into charge transfer phase, and control module 50 makes second switch S2, the 4th switch S 4, the 6th switch S 6, octavo close the state that S8 is in " ON "; Control signal generating unit 22 receives the control of the voltage comparison signal of clock signal CLK and voltage comparison unit 21 outputs, in time to change its control signal and to make win adjustable voltage feeding unit 31a and the specific voltage of the second adjustable voltage feeding unit 32a output.
As shown in Figure 4; Also please consult Figure 1A simultaneously; When simulating digital quantizer as control signal generating unit 22 with successive approximation; Control signal generating unit 22 can be adjusted the control signal of output one by one, adjusting the voltage that the first adjustable voltage feeding unit 31a and the second adjustable voltage feeding unit 32a produce, and then regulates first input end I1 and the received voltage difference of the second input end I2; And make voltage comparison signal more level off to a particular value during cycle than N during the cycle whereby at N+1, wherein particular value can level off to zero current potential for zero potential or a utmost point.
[second embodiment]
Fig. 5 A is a kind of synoptic diagram with multiplex's electric capacitance measurement circuit structure of charge transfer circuit of second embodiment of the invention.Fig. 5 B is the synoptic diagram of the multiplex's electric capacitance measurement circuit structure with charge transfer circuit of another example of second embodiment of the invention.Fig. 5 C is the synoptic diagram of the multiplex's electric capacitance measurement circuit structure with charge transfer circuit of the another example of second embodiment of the invention.Fig. 6 is the second embodiment of the invention synoptic diagram of the multiplex's electric capacitance measurement circuit structure with charge transfer circuit of an example again.
Shown in Fig. 5 A, second embodiment of the invention is a kind of multiplex's electric capacitance measurement circuit structure with charge transfer circuit, and it comprises: one first selects module 10 '; One primary signal processing module 60; And at least one secondary signal processing module 70.Multiplex's electric capacitance measurement circuit structure of present embodiment is to detect the capacitance size of at least one testing capacitance 40 or the variation of capacitance with pipeline circuit (pipeline circuit) with multiplex's mode.And the present embodiment utilization is connected in series a plurality of signal processing modules 60,70, can accelerate to detect the speed of testing capacitance 40 capacitances, and makes the capacitance number of interior detecting of unit interval increase.
First selects module 10 '; The result of its function, the mode of action and generation or effect; Identical with each example of selection module among first embodiment; First selects module 10 ' to comprise: one first selected cell 11 and one second selected cell 12, and wherein testing capacitance 40 is electrically connected between first selected cell 11 and second selected cell 12, and an end of first selected cell 11 and second selected cell 12 electrically connects with two voltage sources 13 equally respectively.Testing capacitance 40 can electrically connect with two voltage sources 13 by switching first selected cell 11 and second selected cell 12, and through two voltage sources 13 testing capacitance 40 is charged.Testing capacitance 40 can be electrically connected at primary signal processing module 60 by first selected cell 11 and second selected cell 12 again, therefore can testing capacitance 40 and primary signal processing module 60 electrically connected through switching first selected cell 11 and second selected cell 12.
Primary signal processing module 60, it comprises: a primary signal processing and control module 61; An and elementary electric charge shift module 30 '.
Primary signal processing and control module 61, the result of its function, the mode of action and generation or effect are identical with each example of signal Processing control module among first embodiment.The input end of primary signal processing and control module 61 and first selected cell 11 and second selected cell 12 electrically connect, and the output terminal of primary signal processing module 60 is in order to export a primary control signal.Primary signal processing and control module 61 comprises again: a primary voltage comparing unit 61a; One first switch S 1; An and primary control signal generation unit 61b.
Primary voltage comparing unit 61a, it has: a first input end I1; One second input end I2; And one first output terminal O1.Wherein, First input end I1 is electrically connected at an end of first selected cell 11; And the second input end I2 also is electrically connected at an end of second selected cell 12; Therefore make testing capacitance 40 to electrically connect, and then compare the voltage at testing capacitance 40 two ends, export one first voltage comparison signal in view of the above by the first output terminal O1 again through the first input end I1 and the second input end I2 of first selected cell 11 and second selected cell 12 and primary voltage comparing unit 61a.
First switch S 1; It is electrically connected between the first input end I1 and the second input end I2 of primary voltage comparing unit 61a; When first switch S 1 is " ON ",, eliminate the drift potential in the circuit whereby even win the input end I1 and the second input end I2 short circuit.
Primary control signal generation unit 61b, it can be a flash type (Flash) analog-digital converter or a successive approximation (SAR) analog-digital converter, it has: one the 3rd input end I3; And one second output terminal O2 and one the 3rd output terminal O3.Wherein, The 3rd input end I3 is electrically connected at the first output terminal O1 of primary voltage comparing unit 61a, and in order to receiving first voltage comparison signal, and the second output terminal O2 and the 3rd output terminal O3; Then in order to export primary control signal respectively, this primary control signal is a digital signal.
Shown in Fig. 5 C; Primary signal processing and control module 61 further comprises at least one first analog signal processing circuit 62 again; It is series between first switch S 1 and the primary voltage comparing unit 61a, in order to the noise in the filtered signal, can promote the accuracy of sensing testing capacitance 40 voltage.
First analog signal processing circuit 62 comprises: one first analog wave filter 62a; And one first adjustable sequencing amplifier 62b, wherein the first analog wave filter 62a and the first adjustable sequencing amplifier 62b be connected in series each other and serial connection sequence unrestricted.For instance; The input end of the first analog wave filter 62a can be serially connected with first switch S 1; And its output terminal is serially connected with the input end of the first adjustable sequencing amplifier 62b; The output terminal of the first adjustable sequencing amplifier 62b is serially connected with primary voltage comparing unit 61a again, that is the first adjustable sequencing amplifier 62b is electrically connected between the first analog wave filter 62a and the primary voltage comparing unit 61a (serial connection sequence is shown in Fig. 5 C).Or; The input end of the first adjustable sequencing amplifier 62b is serially connected with first switch S 1; Its output terminal then is connected in series to the input end of the first analog wave filter 62a; The output terminal of the first analog wave filter 62a is connected in series respectively to the first input end I1 of the first primary voltage comparing unit 61a and the second input end I2 again, makes the analog wave filter 62a that wins be serially connected with (figure does not show) between the first adjustable sequencing amplifier 62b and the primary voltage comparing unit 61a.
Please consult again shown in Fig. 5 A, elementary electric charge shift module 30 ', the result of its function, the mode of action and generation or effect are identical with each example of electric charge shift module among first embodiment.Elementary electric charge shift module 30 ' comprising: one first charge transfer circuit 31; And one second charge transfer circuit 32.Wherein, the input end of elementary electric charge shift module 30 ' receives primary control signal, and its output terminal is electrically connected at the input end of primary signal processing and control module 61.First charge transfer circuit 31, it comprises: one first adjustable voltage feeding unit 31a; And one first sampling capacitor C1, and second charge transfer circuit 32, it comprises: one second adjustable voltage feeding unit 32a; And one second sampling capacitor C2.
The first adjustable voltage feeding unit 31a, its input end is electrically connected at the second output terminal O2 of primary control signal generation unit 61b, and in order to receive primary control signal.In addition, please consult simultaneously shown in Fig. 5 B, the first adjustable voltage feeding unit 31a can be one first resistance-type D/A conversion circuit 31b, for example can be the trapezoidal formula digital analog converter of weighting resistor formula digital analog converter or R-2R.
Moreover; The voltage input end of the first resistance-type D/A conversion circuit 31b can receive one first upper voltage limit and one first lower voltage limit; The output voltage range that makes the first resistance-type D/A conversion circuit 31b is between first upper voltage limit and first lower voltage limit; And the control end of the first resistance-type D/A conversion circuit 31b (being input end) is electrically connected at the second output terminal O2 and controls to receive primary control signal, and control makes the first resistance-type D/A conversion circuit 31b export one first aanalogvoltage according to primary control signal.
Shown in Fig. 5 A and Fig. 5 B, the first sampling capacitor C1, it has: one first end points P1; And one second end points P2.The first end points P1 is electrically connected at the output terminal of the first adjustable voltage feeding unit 31a, and the second end points P2 then is electrically connected at first input end I1.See also again shown in Fig. 5 B; The output terminal of the first resistance-type D/A conversion circuit 31b can be electrically connected at the first end points P1 by second switch S2 selectivity; The first end points P1 can relend again by one the 3rd switch S, 3 selectivity and be electrically connected at one first reference voltage source 13a, to receive one first reference voltage.
The second adjustable voltage feeding unit 32a, its control end (being input end) are electrically connected at the 3rd output terminal O3 in order to receive primary control signal.See also again shown in Fig. 5 B, the second adjustable voltage feeding unit 32a can be one second resistance-type D/A conversion circuit 32b, can realize through weighting resistor formula digital analog converter or the trapezoidal formula digital analog converter of R-2R too.
The second resistance-type D/A conversion circuit 32b voltage input end can receive one second upper voltage limit and one second lower voltage limit; Make output voltage range between second upper voltage limit and second lower voltage limit; And the control end of the second resistance-type D/A conversion circuit 32b (being input end) is electrically connected at the 3rd output terminal O3 and controls to receive primary control signal, so that the second resistance-type D/A conversion circuit 32b exports one second aanalogvoltage.
Shown in Fig. 5 A and Fig. 5 B, the second sampling capacitor C2, it has: one the 3rd end points P3; And one the 4th end points P4.The 3rd end points P3 is electrically connected at the output terminal of the second adjustable voltage feeding unit 32a, and the 4th end points P4 then is electrically connected at the second input end I2.In addition; See also shown in Fig. 5 B; The output terminal of the second resistance-type D/A conversion circuit 32b is electrically connected at the 3rd end points P3 by the 4th switch S 4 selectivity equally; And the 3rd end points P3 relends by the 5th switch S 5 selectivity and is electrically connected at one second reference voltage source 13b, to receive one second reference voltage.
Shown in Fig. 5 B, first selected cell 11 comprises: one the 6th switch S 6; And one minion close S7, and second selected cell 12 comprises: an octavo is closed S8; And one the 9th switch S 9.The 6th switch S 6 is serially connected with the first input end I1 of primary voltage comparing unit 61a, and minion is closed S7 and then is serially connected with the 6th switch S 6 and is electrically connected to voltage source 13, and the 6th switch S 6 and minion are closed between the S7 and had a first node N1 in addition.In like manner; Octavo is closed the second input end I2 that S8 is serially connected with primary voltage comparing unit 61a; 9 of the 9th switch S are serially connected with octavo and close S8 and electrically connect (seeing also Fig. 5 A) with voltage source 13; Octavo is closed the same Section Point N2 of formation between S8 and the 9th switch S 9, so an end of testing capacitance 40 is electrically connected at first node N1, and the other end then is electrically connected at Section Point N2.
Moreover, seeing also shown in Fig. 5 C, first selected cell 11 and second selected cell 12 can be respectively a multiplexer, are electrically connected at testing capacitance 40 with selectivity.That is, when a plurality of testing capacitance 40, can desire be measured or the first input end I1 and the second input end I2 of the testing capacitance 40 of detecting and primary voltage comparing unit 61a electrically connect by multiplexer.
Shown in Fig. 5 A, secondary signal processing module 70, it comprises: one second selects module 10 "; A level signal Processing control module 71; And level electric charge shift module 30 ".
The mode that multiplex's electric capacitance measurement circuit is connected in series with at least one secondary signal processing module 70 by primary signal processing module 60 is with the purpose of the capacitance that reaches quick detecting testing capacitance 40.Therefore; Each secondary signal processing module 70 is connected in series in regular turn each other; The secondary signal processing module 70 of the first order is serially connected with primary signal processing module 60 in a plurality of secondary signal processing modules 70; And partial secondary signal processing module 70 is serially connected with the secondary signal processing module 70 of the first order again, and the quantity of serial connection can change according to user's demand.
Shown in Fig. 5 A, second selects module 10 " comprising: one the 3rd selected cell 14 and one the 4th selected cell 15.Wherein, be electrically connected with one between the 3rd selected cell 14 and the 4th selected cell 15 and shift electric capacity 41, and be equally through switching the 3rd selected cell 14 and the 4th selected cell 15 so that electric capacity 41 charges or the action of electric charge transfer to shifting.
Wherein, second select module 10 " input end be electrically connected at the input end (as shown in Figure 6) of secondary signal processing and control module 71 of input end I1, I2 or previous stage of the primary signal processing and control module 61 of previous stage.Explanation more specifically; In the secondary signal processing module 70 of the first order; The 3rd selected cell 14 is electrically connected at an end of first selected cell 11; First input end I1 with primary signal processing and control module 61 electrically connects, and the 4th selected cell 15 then is electrically connected at an end of second selected cell 12, electrically connects with the second input end I2 with primary signal processing and control module 61.In the second level or the above secondary signal processing module 70; The 3rd selected cell 14, the four selected cells 15 that its 3rd selected cell 14 is electrically connected at the secondary signal processing module 70 of previous stage then are electrically connected at the 4th selected cell 15 of the secondary signal processing module 70 of previous stage.
Each secondary signal Processing control module 71 comprises: a secondary voltage comparing unit 71a; The tenth switch S 10; And level control signal generating unit 71b.Wherein, the input end of secondary signal processing and control module 71 and second is selected module 10 " electrically connect, and the exportable level control signal of its output terminal.
Secondary voltage comparing unit 71a, it has: a four-input terminal I4; One the 5th input end I5; And one the 4th output terminal O4.Four-input terminal I4 is series at an end of the 3rd selected cell 14; The 5th input end I5 then is series at the other end of the 4th selected cell 15; Also therefore shifting electric capacity 41 can be by four-input terminal I4 and the 5th input end I5; Electrically connect with secondary voltage comparing unit 71a, and then relatively shift the voltage at electric capacity 41 two ends, export one second voltage comparison signal in view of the above through the 4th output terminal O4 again.
The tenth switch S 10, it is electrically connected between four-input terminal I4 and the 5th input end I5, when the tenth switch S 10 is " ON ", promptly makes four-input terminal I4 and the 5th input end I5 short circuit, to eliminate the drift potential in the circuit whereby.
Secondary control signal generating unit 71b can be a flash type (Flash) analog-digital converter or a successive approximation (SAR) analog-digital converter.Secondary control signal generating unit 71b has: one the 6th input end I6; And one the 5th output terminal O5 and one the 6th output terminal O6.The 6th input end I6 is electrically connected at the 4th output terminal O4 to receive second voltage comparison signal, and then in order to export secondary control signal respectively, this secondary control signal is a digital signal for the 5th output terminal O5 and the 6th output terminal O6.
In like manner; Shown in Fig. 5 C; Secondary signal processing and control module 71 can further comprise at least one second analog signal processing circuit 72 equally; Second analog signal processing circuit 72 can be series between the tenth switch S 10 and the secondary voltage comparing unit 71a, in order to the noise in the filtered signal, shifts the measured voltage accuracy in electric capacity 41 two ends to promote.
Second analog signal processing circuit 72 comprises: one second analog wave filter 72a; And one second adjustable sequencing amplifier 72b, wherein the second analog wave filter 72a and one second adjustable sequencing amplifier 72b be connected in series each other and serial connection sequence unrestricted.For instance; The input end of the second analog wave filter 72a can be serially connected with the tenth switch S 10; Its output terminal then is electrically connected to the input end of the second adjustable sequencing amplifier 72b, that is the second adjustable sequencing amplifier 72b is electrically connected at (figure does not show) between the second analog wave filter 72a and the secondary voltage comparing unit 71a.Or; The input end of the second adjustable sequencing amplifier 72b can be serially connected with the tenth switch S 10; Its output terminal then is electrically connected to the input end of the second analog wave filter 72a; The output terminal of the second analog wave filter 72a is electrically connected to secondary voltage comparing unit 71a more respectively, makes the second analog wave filter 72a be electrically connected between the second adjustable sequencing amplifier 72b and the secondary voltage comparing unit 71a (serial connection sequence is shown in Fig. 5 C).
Secondary electric charge shift module 30 " input end receive the primary control signal (shown in Fig. 5 A) of previous stage output or the secondary control signal (as shown in Figure 6) of previous stage output, secondary electric charge shift module 30 " output terminal be electrically connected at the input end of secondary signal processing and control module 71.
The secondary electric charge shift module 30 of the first order ", it comprises: a tricharged carry circuit 33; And one the 4th charge transfer circuit 34.Tricharged carry circuit 33, it comprises: one the 3rd adjustable voltage feeding unit 33a; And the 3rd sampling capacitor C3, and the 4th charge transfer circuit 34, it also comprises: one the 4th adjustable voltage feeding unit 34a; And one the 4th sampling capacitor C4.
The 3rd adjustable voltage feeding unit 33a, its input end is electrically connected at the second output terminal O2, to receive the primary control signal that primary control signal generation unit 61b is exported.In like manner, the input end of the 4th adjustable voltage feeding unit 34a is electrically connected at the 3rd output terminal O3, equally in order to receive primary control signal.
Please consult simultaneously again shown in Fig. 5 B, the 3rd sampling capacitor C3, it has: a five terminal point P5; And one the 6th end points P6, and the 4th sampling capacitor C4, it has: one the 7th end points P7; And one the 8th end points P8.Wherein, Five terminal point P5 and the 7th end points P7 optionally are electrically connected at the output terminal of the 3rd adjustable voltage feeding unit 33a and the 4th adjustable voltage feeding unit 34a respectively by a switch; And five terminal point P5 and the 7th end points P7 optionally are electrically connected at a reference voltage source 13c through switch equally, and reference voltage source 13c can be required with output reference voltage according to sampling capacitor C3, the C4 of serial connection.In addition, the 6th end points P6 and the 8th end points P8 are electrically connected at four-input terminal I4 and the 5th input end I5 respectively.
As shown in Figure 6, except that the secondary electric charge shift module 30 of the first order ", the secondary charge transfer circuit of each grade comprises: one the 5th charge transfer circuit 35; And one the 6th charge transfer circuit 36.The 5th charge transfer circuit 35, it comprises: one the 5th adjustable voltage feeding unit 35a; And one the 5th sampling capacitor C5, and the 6th charge transfer circuit 36, it comprises: one the 6th adjustable voltage feeding unit 36a; And the 6th sampling capacitor C6.
The 5th adjustable voltage feeding unit 35a, its input end is electrically connected at the 5th output terminal O5 of the secondary control signal generating unit 71b of previous stage, to receive the secondary control signal that the secondary control signal generating unit 71b of previous stage is exported.In like manner, the input end of the 6th adjustable voltage feeding unit 36a is electrically connected at the 6th output terminal O6 of the secondary control signal generating unit 71b of previous stage, to receive secondary control signal.
The 5th sampling capacitor C5, it has: one the 9th end points P9; And 1 the tenth end points P10, and the 6th sampling capacitor C6, it has: 1 the 11 end points P11; And 1 the 12 end points P12.
The 9th end points P9 and the 11 end points P11 optionally are electrically connected at the output terminal of the 5th adjustable voltage feeding unit 35a and the 6th adjustable voltage feeding unit 36a respectively by switch; And the 9th end points P9 and the 11 end points P11 optionally are electrically connected at reference voltage source 13c through switch equally respectively, and reference voltage source 13c can be required with output reference voltage according to sampling capacitor C5, the C6 of serial connection.In addition, the tenth end points P10 and the 12 end points P12 then are electrically connected at four-input terminal I4 ' and the 5th input end I5 ' of secondary voltage comparing unit 71a ' at the corresponding levels equally respectively.
The the 3rd to the 6th adjustable voltage feeding unit 33a, 34a, 35a, 36a can realize through weighting resistor formula digital analog converter or the trapezoidal formula digital analog converter of R-2R; An and same upper voltage limit and the pressure of once rationing the power supply of receiving of its voltage input end; Make output voltage range between upper voltage limit and lower voltage limit; And the control end (being input end) of the 3rd to the 6th adjustable voltage feeding unit 33a, 34a, 35a, 36a receives the control of primary control signal or secondary control signal, so that the 3rd to the 6th adjustable voltage feeding unit 33a, 34a, 35a, 36a export an aanalogvoltage.
As shown in Figure 6; Multiplex's electric capacitance measurement circuit structure can further comprise a control module 50; It selects module 10 in order to control first selected cell 11, second selected cell 12 and each second " in the on off state of one the 3rd selected cell 14 and one the 4th selected cell 15; make testing capacitance 40 or shift electric capacity 41 can be optionally with first, second, the 4th and the 5th input end I1, I2, I4, I4 ', I5, I5 ' electrically connect; and control module 50 can control the switch in the charge transfer circuit equally, so that multiplex's electric capacitance measurement circuit structure can switch between charging stage and charge transfer phase.
Fig. 7 A is the synoptic diagram of second embodiment of the invention at the circuit structure of first charging stage.Fig. 7 B is the synoptic diagram of second embodiment of the invention at the circuit structure of first charge transfer phase.Fig. 7 C is the synoptic diagram of second embodiment of the invention at the circuit structure of second charging stage.Fig. 7 D is the synoptic diagram of second embodiment of the invention at the circuit structure of second charge transfer phase.Fig. 7 E is the synoptic diagram of second embodiment of the invention at the circuit structure of the 3rd charging stage.Fig. 7 F is the synoptic diagram of second embodiment of the invention at the circuit structure of tricharged transition phase.Fig. 7 G is the synoptic diagram of second embodiment of the invention at the circuit structure of the 4th charging stage.Fig. 7 H is the synoptic diagram of second embodiment of the invention at the circuit structure of the 4th charge transfer phase.
Shown in Fig. 7 A; When first charging stage; Control module 50 is switched first switch S 1, the 3rd switch S 3, the 5th switch S 5, minion is closed S7 and the 9th switch S 9; Make it and be in the state of " ON ", close S8 and secondary signal processing module 70,70 ', 70 with time second switch S2, the 4th switch S 4, the 6th switch S 6 and octavo " in all switches all be in the state of " OFF ", thereby make testing capacitance 40 separate with primary signal processing module 60.Wherein, Testing capacitance 40 can be by voltage source (figure does not show) charging; In addition; Because second switch S2 and the 4th switch S 4 are in the state of " OFF ", make the primary signal processing and control module 61 and the first adjustable voltage feeding unit 31a and the second adjustable voltage feeding unit 32a be in the state of electrical isolation, and respectively the first sampling capacitor C1 and the second sampling capacitor C2 are charged by the first reference voltage source 13a and the second reference voltage source 13b.
Please consult shown in Fig. 7 B simultaneously; Continuation is in first charge transfer phase; Control module 50 is switched second switch S2, the 4th switch S 4, the 6th switch S 6 and octavo and is closed the state of S8 to " ON ", otherwise first switch S 1, the 3rd switch S 3, the 5th switch S 5, minion are closed S7 and the 9th switch S 9 and secondary signal processing module 70,70 ', 70 " all switches all be in the state of " OFF ".At this moment; Testing capacitance 40, the first sampling capacitor C1 and the second sampling capacitor C2 form a capacitance partial pressure loop; And the first adjustable voltage feeding unit 31a and the second adjustable voltage feeding unit 32a relend by primary control signal; To adjust the bias voltage on the first sampling capacitor C1 and the second sampling capacitor C2, make the electric charge of testing capacitance 40 be transferred to the first sampling capacitor C1 and the second sampling capacitor C2.
Because primary voltage comparing unit 61a exports one first voltage comparison signal and still representes to have voltage difference between the first input end I1 and the second input end I2; Also representing the electric charge on the testing capacitance 40 not to be transferred to the first sampling capacitor C1 and the second sampling capacitor C2 fully; So primary control signal generation unit 61b produces primary control signal again to adjust the magnitude of voltage that the first adjustable voltage feeding unit 31a and the second adjustable voltage feeding unit 32a produce; With so regulate and control the voltage difference at the first sampling capacitor C1 and the second sampling capacitor C2 two ends, and reach the purpose of detecting testing capacitance 40.Wherein, the computing formula of testing capacitance 40 sees also shown in first embodiment.
Shown in Fig. 7 C; Owing to only be difficult to make the voltage difference convergence particular value of the first input end I1 and the second input end I2 by charge transfer phase once; Therefore need carry out for second charging stage; With the time in order to detect the testing capacitance 40 new capacitance that produces again; So after primary control signal generation unit 61b receives first voltage comparison signal, primary control signal is sent to the 3rd adjustable voltage feeding unit 33a or the 4th adjustable voltage feeding unit 34a, and the voltage difference of the first input end I1 and the second input end I2 is transferred to the transfer electric capacity 41 of secondary signal processing module 70; Secondary signal processing module 70 is further transferred in the action of the feasible adjustment first input end I1 and the second input end I2 voltage difference.
In second charging stage; The 3rd selected cell 14 and the 4th selected cell 15 in the secondary signal processing module 70 of the control module 50 switching first order; The first input end I1 and the second input end I2 are electrically connected to shift electric capacity 41; Thereby make the voltage difference of the first input end I1 and the second input end I2 transfer to the transfer electric capacity 41 in the secondary signal processing module 70 of the first order, also be equal to the first sampling capacitor C1 and the second sampling capacitor C2 and charge shifting electric capacity 41.Also make the 3rd sampling capacitor C3 and the 4th sampling capacitor C4 series connection and be electrically connected at reference voltage source 13c charging with time control module 50, and be that second charge transfer phase is prepared.
Shown in Fig. 7 D; In second charge transfer phase; Control module 50 is switched the 3rd selected cell 14 and the 4th selected cell 15 once more; Make transfer electric capacity 41 be electrically connected to four-input terminal I4 and the 5th input end I5; And control module 50 also makes the 3rd adjustable voltage feeding unit 33a be electrically connected to the 3rd sampling capacitor C3 and the 4th adjustable voltage feeding unit 34a is electrically connected to the 4th sampling capacitor C4, again according to primary control signal to adjust the bias voltage on the 3rd sampling capacitor C3 and the 4th sampling capacitor C4, make the electric charge that shifts electric capacity 41 be able to be transferred to sampling capacitor C3, C4.
Then; The voltage difference that compares four-input terminal I4 and the 5th input end I5 by secondary voltage comparing unit 71a; Relend by the 4th output terminal O4 and export second voltage comparison signal; Though transfer electric capacity 41 two ends in the first order secondary signal processing module 70 still have voltage difference, second voltage comparison signal that first order secondary voltage comparing unit 71a is exported can more level off to a particular value than first voltage comparison signal.
And for example shown in Fig. 7 E; In the 3rd charging stage; The tenth switch S 10 ' is the state of " ON " in the partial secondary signal processing module 70 ' of control module 50 switchings; And the four-input terminal I4 of the secondary signal processing module 70 of the first order and the transfer electric capacity 41 ' of the 5th input end I5 and partial secondary signal processing module 70 ' electrically connected; The 3rd sampling capacitor C3 and the 4th sampling capacitor C4 of secondary signal processing module 70 that makes the first order be again to partial transfer electric capacity 41 ' charging, also makes the 5th sampling capacitor C5 and the 6th sampling capacitor C6 series connection and electrically connect with charging with reference voltage source 13c with time control module 50.
Shown in Fig. 7 F; In the tricharged transition phase; Shifting electric capacity 41 ' and the 5th sampling capacitor C5 and the 6th sampling capacitor C6 electrically connects; And the magnitude of voltage that produces by the 5th adjustable voltage feeding unit 35a and the 6th adjustable voltage feeding unit 36a; Make and shift electric capacity 41 ' electric charge is transferred to the 5th sampling capacitor C5 and the 6th sampling capacitor C6, partial secondary voltage comparing unit 71a ' can produce secondary voltage comparing unit 71a than the first order again and more level off to second voltage comparison signal of particular value.
Shown in Fig. 7 G; Similar in appearance to the above-mentioned charging stage; The 4th charging stage is by the secondary signal processing module 70 with the third level " in transfer electric capacity 41 " electrically connect with the four-input terminal I4 ' of partial secondary signal processing module 70 ' and the 5th input end I5 '; Be sent to voltage difference and shift electric capacity 41 the four-input terminal I4 ' of partial secondary signal processing module 70 ' and the 5th input end I5 ' two ends "; and the tenth switch S 10 " be the state of " ON ", make the 5th sampling capacitor C5 ' and the 6th sampling capacitor C6 ' series connection and electrically connect to charge with reference voltage source 13c.
Shown in Fig. 7 H; The 4th charge transfer phase; Shift electric capacity 41 " electrically connect to carry out electric charge with the 5th sampling capacitor C5 ' and the 6th sampling capacitor C6 ' and shift; again by secondary voltage comparing unit 71a " second voltage comparison signal that produces imports secondary control signal generating unit 71b ", finally by secondary control signal generating unit 71b " signal that produces can more level off to particular value again, and wherein particular value can level off to zero current potential for zero potential or a utmost point.
Fig. 8 is the signal timing diagram of second embodiment of the invention successive approximation simulation digital quantizer.Fig. 9 is the signal timing diagram of second embodiment of the invention flash type analog-digital converter.Figure 10 is the map of the signal sequence of the first embodiment of the invention and second embodiment.
Like Fig. 8 and shown in Figure 9; When successive approximation (SAR) analog-digital converter during as control signal generating unit; Control signal generating unit is adjusted magnitude of voltage one by one; And flash type (Flash) analog-digital converter is as control signal generating unit, and the adjustment of the voltage of each control signal is relatively fast, so successive approximation simulation digital quantizer must expend more chronomere compared to the flash type analog-digital converter.
Shown in figure 10; When using multiplex's electric capacitance measurement circuit structure detecting testing capacitance; Because a plurality of signal processing modules of serial connection make when measuring four testing capacitance 40a, 40b, 40c, 40d, if use successive approximation simulation digital quantizer to need 14 unit interval; And use the flash type analog-digital converter only to need 11 unit interval, the measurement efficient of capacitance when therefore using multiplex's electric capacitance measurement circuit structure can significantly promote a plurality of testing capacitance.
The above only is preferred embodiment of the present invention, is not the present invention is done any pro forma restriction; Though the present invention discloses as above with preferred embodiment; Yet be not in order to limiting the present invention, anyly be familiar with the professional and technical personnel, in not breaking away from technical scheme scope of the present invention; When the technology contents of above-mentioned announcement capable of using is made a little change or is modified to the equivalent embodiment of equivalent variations; In every case be not break away from technical scheme content of the present invention, to any simple modification, equivalent variations and modification that above embodiment did, all still belong in the scope of technical scheme of the present invention according to technical spirit of the present invention.

Claims (31)

1. electric capacitance measurement circuit structure with charge transfer circuit in order to detect at least one testing capacitance, is characterized in that it comprises:
One selects module, and it comprises: one first selected cell and one second selected cell, and wherein this testing capacitance is electrically connected between this first selected cell and this second selected cell;
One signal Processing control module, it comprises:
One voltage comparison unit, it has: a first input end, it is series at an end of this first selected cell; One second input end, it is series at an end of this second selected cell; And one first output terminal, it is in order to export a voltage comparison signal;
One first switch, it is electrically connected between this first input end and this second input end; And
One control signal generating unit, it has: one the 3rd input end, it is electrically connected at this first output terminal to receive this voltage comparison signal; And one second output terminal and one the 3rd output terminal, in order to export a control signal respectively; And
One electric charge shift module, it comprises:
One first charge transfer circuit, it comprises:
One first adjustable voltage feeding unit, its input end are electrically connected at this second output terminal in order to receive this control signal; And
One first sampling capacitor, it has: one first end points, it is electrically connected at the output terminal of this first adjustable voltage feeding unit; And one second end points, it is electrically connected at this first input end; And
One second charge transfer circuit, it comprises:
One second adjustable voltage feeding unit, its input end are electrically connected at the 3rd output terminal in order to receive this control signal; And
One second sampling capacitor, it has: one the 3rd end points, it is electrically connected at the output terminal of this second adjustable voltage feeding unit; And one the 4th end points, it is electrically connected at this second input end;
Wherein, this control signal generating unit reads this voltage comparison signal at N during the cycle, to determine this control signal, makes this voltage comparison signal during cycle more level off to a particular value than this N at N+1 during the cycle whereby, and wherein this N is a positive integer.
2. the electric capacitance measurement circuit structure with charge transfer circuit according to claim 1; It is characterized in that the wherein said first adjustable voltage feeding unit is one first resistance-type D/A conversion circuit; Its voltage input end receives one first upper voltage limit and one first lower voltage limit; And the control end of this first resistance-type D/A conversion circuit is electrically connected at this second output terminal and controls to receive this control signal; So that this first resistance-type D/A conversion circuit is exported one first aanalogvoltage; And this output terminal of this first resistance-type D/A conversion circuit is electrically connected at this first end points by a second switch selectivity, and this first end points is electrically connected at one first reference voltage source by one the 3rd switch selectivity again, to receive one first reference voltage.
3. the electric capacitance measurement circuit structure with charge transfer circuit according to claim 1; It is characterized in that the wherein said second adjustable voltage feeding unit is one second resistance-type D/A conversion circuit; Its voltage input end receives one second upper voltage limit and one second lower voltage limit; And the control end of this second resistance-type D/A conversion circuit is electrically connected at the 3rd output terminal and controls to receive this control signal; So that this second resistance-type D/A conversion circuit is exported one second aanalogvoltage; And this output terminal of this second resistance-type D/A conversion circuit is electrically connected at the 3rd end points by one the 4th switch selectivity, and the 3rd end points is electrically connected at one second reference voltage source by one the 5th switch selectivity again, to receive one second reference voltage.
4. the electric capacitance measurement circuit structure with charge transfer circuit according to claim 1 is characterized in that wherein said first selected cell comprises: one the 6th switch, and it is serially connected with this first input end; And one minion close, it is serially connected with the 6th switch; And this second selected cell comprises: an octavo is closed, and it is serially connected with this second input end; And one the 9th switch; It is serially connected with this octavo and closes; Wherein an end of this testing capacitance is electrically connected at the first node between the 6th switch and this minion pass, and the other end of this testing capacitance is electrically connected at the Section Point between this octavo pass and the 9th switch.
5. the electric capacitance measurement circuit structure with charge transfer circuit according to claim 1 is characterized in that wherein said first selected cell and this second selected cell are respectively a multiplexer, are electrically connected at this testing capacitance with selectivity.
6. the electric capacitance measurement circuit structure with charge transfer circuit according to claim 1; It is characterized in that wherein said signal Processing control module further comprises at least one analog signal processing circuit, it is series between this first switch and this voltage comparison unit.
7. the electric capacitance measurement circuit structure with charge transfer circuit according to claim 6, it is characterized in that wherein said analog signal processing circuit comprises: an analog wave filter, its input end are serially connected with this first switch; And an adjustable sequencing amplifier, its input end is serially connected with the output terminal of this analog wave filter, and the output terminal of this is adjustable sequencing amplifier is serially connected with this voltage comparison unit.
8. the electric capacitance measurement circuit structure with charge transfer circuit according to claim 6 is characterized in that wherein said analog signal processing circuit comprises: an adjustable sequencing amplifier, and its input end is serially connected with this first switch; And an analog wave filter, its input end is serially connected with the output terminal of this adjustable sequencing amplifier, and the output terminal of this analog wave filter is serially connected with this voltage comparison unit.
9. the electric capacitance measurement circuit structure with charge transfer circuit according to claim 1 is characterized in that wherein said control signal generating unit is a flash type analog-digital converter or successive approximation simulation digital quantizer.
10. the electric capacitance measurement circuit structure with charge transfer circuit according to claim 1; It is characterized in that it further comprises a control module; Its this first selected cell of control and this second selected cell optionally electrically connect this testing capacitance with this first input end and this second input end.
11. the multiplex's electric capacitance measurement circuit structure with charge transfer circuit in order to detect at least one testing capacitance, is characterized in that it comprises:
One first selects module, and it comprises: one first selected cell and one second selected cell, and wherein this testing capacitance is electrically connected between this first selected cell and this second selected cell;
One primary signal processing module, it comprises:
One primary signal processing and control module, its input end and this first selected cell and this second selected cell electrically connect, and its output terminal is exported a primary control signal; And
One elementary electric charge shift module, its input end receives this primary control signal, and its output terminal is electrically connected at the input end of this primary signal processing and control module; And
At least one secondary signal processing module; And each this secondary signal processing module is connected in series in regular turn each other; This secondary signal processing module of the first order is serially connected with this primary signal processing module in those secondary signal processing modules, and wherein each this secondary signal processing module comprises:
One second selects module, its input end to be electrically connected at the input end of a level signal Processing control module of this primary signal processing and control module or the previous stage of previous stage;
This secondary signal processing and control module, its input end and this second selection module electrically connect, and level control signal of its output terminal output; And
A level electric charge shift module, its input end receive this primary control signal of previous stage output or this secondary control signal of previous stage output, and the output terminal of this secondary electric charge shift module is electrically connected at the input end of this secondary signal processing and control module.
12. the multiplex's electric capacitance measurement circuit structure with charge transfer circuit according to claim 11 is characterized in that wherein said primary signal processing and control module comprises:
One primary voltage comparing unit, it has: a first input end, it is electrically connected at an end of this first selected cell; One second input end, it is series at an end of this second selected cell; And one first output terminal, it is in order to export one first voltage comparison signal;
One first switch, it is electrically connected between this first input end and this second input end; And
One primary control signal generation unit, it has: one the 3rd input end, it is electrically connected at this first output terminal to receive this first voltage comparison signal; And one second output terminal and one the 3rd output terminal, it is in order to export this primary control signal respectively.
13. the multiplex's electric capacitance measurement circuit structure with charge transfer circuit according to claim 12; It is characterized in that wherein said primary signal processing and control module further comprises at least one first analog signal processing circuit, it is series between this first switch and this primary voltage comparing unit.
14. the multiplex's electric capacitance measurement circuit structure with charge transfer circuit according to claim 13, it is characterized in that wherein said first analog signal processing circuit comprises: one first analog wave filter, its input end are serially connected with this first switch; And one first adjustable sequencing amplifier, its input end is serially connected with the output terminal of this first analog wave filter, and the output terminal of this first adjustable sequencing amplifier is serially connected with this primary voltage comparing unit.
15. the multiplex's electric capacitance measurement circuit structure with charge transfer circuit according to claim 13 is characterized in that wherein said first analog signal processing circuit comprises: one first adjustable sequencing amplifier, its input end is serially connected with this first switch; And one first analog wave filter, its input end is serially connected with the output terminal of this first adjustable sequencing amplifier, and the output terminal of this first analog wave filter is serially connected with this primary voltage comparing unit.
16. the multiplex's electric capacitance measurement circuit structure with charge transfer circuit according to claim 12 is characterized in that wherein said primary control signal generation unit is a flash type analog-digital converter or successive approximation simulation digital quantizer.
17. the multiplex's electric capacitance measurement circuit structure with charge transfer circuit according to claim 12 is characterized in that wherein said elementary electric charge shift module, comprising:
One first charge transfer circuit, it comprises:
One first adjustable voltage feeding unit, its input end are electrically connected at this second output terminal in order to receive this primary control signal; And
One first sampling capacitor, it has: one first end points, it is electrically connected at the output terminal of this first adjustable voltage feeding unit; And one second end points, it is electrically connected at this first input end; And
One second charge transfer circuit, it comprises:
One second adjustable voltage feeding unit, its input end are electrically connected at the 3rd output terminal in order to receive this primary control signal; And
One second sampling capacitor, it has: one the 3rd end points, it is electrically connected at the output terminal of this second adjustable voltage feeding unit; And one the 4th end points, it is electrically connected at this second input end.
18. the multiplex's electric capacitance measurement circuit structure with charge transfer circuit according to claim 17; It is characterized in that the wherein said first adjustable voltage feeding unit is one first resistance-type D/A conversion circuit; Its voltage input end receives one first upper voltage limit and one first lower voltage limit; And the control end of this first resistance-type D/A conversion circuit is electrically connected at this second output terminal and controls to receive this primary control signal; So that this first resistance-type D/A conversion circuit is exported one first aanalogvoltage; Not only this output terminal of this first resistance-type D/A conversion circuit but also be electrically connected at this first end points by a second switch selectivity, and this first end points is electrically connected at one first reference voltage source by one the 3rd switch selectivity again, to receive one first reference voltage; And
This second adjustable voltage feeding unit is one second resistance-type D/A conversion circuit; Its voltage input end receives one second upper voltage limit and one second lower voltage limit; And the control end of this second resistance-type D/A conversion circuit is electrically connected at the 3rd output terminal and controls to receive this primary control signal; So that this second resistance-type D/A conversion circuit is exported one second aanalogvoltage; And this output terminal of this second resistance-type D/A conversion circuit is electrically connected at the 3rd end points by one the 4th switch selectivity; And the 3rd end points is electrically connected at one second reference voltage source by one the 5th switch selectivity again, to receive one second reference voltage.
19. the multiplex's electric capacitance measurement circuit structure with charge transfer circuit according to claim 12 is characterized in that wherein said first selected cell comprises: one the 6th switch, it is serially connected with this first input end; And one minion close, it is serially connected with the 6th switch; And this second selected cell comprises: an octavo is closed, and it is serially connected with this second input end; And one the 9th switch; It is serially connected with this octavo and closes; Wherein an end of this testing capacitance is electrically connected at the first node between the 6th switch and this minion pass, and the other end of this testing capacitance is electrically connected at the Section Point between this octavo pass and the 9th switch.
20. the multiplex's electric capacitance measurement circuit structure with charge transfer circuit according to claim 11; It is characterized in that wherein said second selects module to comprise: one the 3rd selected cell and one the 4th selected cell, and be electrically connected with a transfer electric capacity between the 3rd selected cell and the 4th selected cell.
21. the multiplex's electric capacitance measurement circuit structure with charge transfer circuit according to claim 20; It is characterized in that wherein in this secondary signal processing module of the first order; The 3rd selected cell is electrically connected at an end of this first selected cell, and the 4th selected cell then is electrically connected at an end of this second selected cell.
22. the multiplex's electric capacitance measurement circuit structure with charge transfer circuit according to claim 20; It is characterized in that in the wherein said secondary signal processing module; The 3rd selected cell is electrically connected at the 3rd selected cell of previous stage, and the 4th selected cell then is electrically connected at the 4th selected cell of previous stage.
23., it is characterized in that wherein each this secondary signal processing and control module comprises according to the described multiplex's electric capacitance measurement circuit structure of arbitrary claim in the claim 11 to 22 with charge transfer circuit:
One secondary voltage comparing unit, it has: a four-input terminal, it is series at an end of the 3rd selected cell; One the 5th input end, it is series at an end of the 4th selected cell; And one the 4th output terminal, it is in order to export one second voltage comparison signal;
The tenth switch, it is electrically connected between this four-input terminal and the 5th input end; And
A level control signal generating unit, it has: one the 6th input end, it is electrically connected at the 4th output terminal to receive this second voltage comparison signal; And one the 5th output terminal and one the 6th output terminal, it is in order to this secondary control signal of output respectively.
24. the multiplex's electric capacitance measurement circuit structure with charge transfer circuit according to claim 23; It is characterized in that wherein said secondary signal processing and control module further comprises at least one second analog signal processing circuit, it is series between the tenth switch and this secondary voltage comparing unit.
25. the multiplex's electric capacitance measurement circuit structure with charge transfer circuit according to claim 24 is characterized in that wherein said second analog signal processing circuit comprises: one second analog wave filter, its input end is serially connected with the tenth switch; And one second adjustable sequencing amplifier, its input end is serially connected with the output terminal of this second analog wave filter, and the output terminal of this second adjustable sequencing amplifier is serially connected with this secondary voltage comparing unit.
26. the multiplex's electric capacitance measurement circuit structure with charge transfer circuit according to claim 24 is characterized in that wherein said second analog signal processing circuit comprises: one second adjustable sequencing amplifier, its input end is serially connected with the tenth switch; And one second analog wave filter, its input end is serially connected with the output terminal of this second adjustable sequencing amplifier, and the output terminal of this second analog wave filter is serially connected with this secondary voltage comparing unit.
27. the multiplex's electric capacitance measurement circuit structure with charge transfer circuit according to claim 23 is characterized in that wherein said secondary control signal generating unit is a flash type analog-digital converter or successive approximation simulation digital quantizer.
28. the multiplex's electric capacitance measurement circuit structure with charge transfer circuit according to claim 23 is characterized in that wherein this secondary electric charge shift module of the first order, it comprises:
One tricharged carry circuit, it comprises:
One the 3rd adjustable voltage feeding unit, its input end is electrically connected at this second output terminal, to receive this primary control signal; And
One the 3rd sampling capacitor, it has: a five terminal point, it is electrically connected at the output terminal of the 3rd adjustable voltage feeding unit; And one the 6th end points, it is electrically connected at this four-input terminal; And
One the 4th charge transfer circuit, it comprises:
One the 4th adjustable voltage feeding unit, its input end is electrically connected at the 3rd output terminal, to receive this primary control signal; And
One the 4th sampling capacitor, it has: one the 7th end points, it is electrically connected at the output terminal of the 4th adjustable voltage feeding unit; And one the 8th end points, it is electrically connected at the 5th input end.
29. the multiplex's electric capacitance measurement circuit structure with charge transfer circuit according to claim 23 is characterized in that wherein except that this secondary electric charge shift module of the first order, each this secondary charge transfer circuit of level comprises:
One the 5th charge transfer circuit, it comprises:
One the 5th adjustable voltage feeding unit, its input end is electrically connected at the 5th output terminal of this secondary signal processing and control module of previous stage, to receive this secondary control signal; And
One the 5th sampling capacitor, it has: one the 9th end points, it is electrically connected at the output terminal of the 5th adjustable voltage feeding unit; And 1 the tenth end points, it is electrically connected at this four-input terminal; And
One the 6th charge transfer circuit, it comprises:
One the 6th adjustable voltage feeding unit, its input end is electrically connected at the 6th output terminal of this secondary signal processing and control module of previous stage, to receive this secondary control signal; And
One the 6th sampling capacitor, it has: 1 the 11 end points, it is electrically connected at the output terminal of the 6th adjustable voltage feeding unit; And 1 the 12 end points, it is electrically connected at the 5th input end.
30. the multiplex's electric capacitance measurement circuit structure with charge transfer circuit according to claim 11 is characterized in that wherein said first selected cell and this second selected cell are respectively a multiplexer, are electrically connected at this testing capacitance with selectivity.
31. the multiplex's electric capacitance measurement circuit structure with charge transfer circuit according to claim 11; It is characterized in that it further comprises a control module, the on off state of one the 3rd selected cell and one the 4th selected cell in its this first selected cell of control, this second selected cell and each this second selection module.
CN2011100355626A 2011-02-01 2011-02-01 Capacitor measurement circuit structure with charge transfer circuit Pending CN102621395A (en)

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Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103914190A (en) * 2012-12-31 2014-07-09 比亚迪股份有限公司 Capacitance detection circuit
CN103914190B (en) * 2012-12-31 2017-03-15 比亚迪股份有限公司 Capacitive detection circuit
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CN112710940A (en) * 2020-12-23 2021-04-27 西安交通大学 SiC MOSFET reverse transfer capacitance measuring method
CN112710940B (en) * 2020-12-23 2022-05-20 西安交通大学 SiC MOSFET reverse transfer capacitance measuring method
CN115343515A (en) * 2022-10-17 2022-11-15 基合半导体（宁波）有限公司 Analog front end circuit, capacitance measuring circuit, chip and electronic equipment
CN115343515B (en) * 2022-10-17 2023-03-07 基合半导体（宁波）有限公司 Analog front end circuit, capacitance measuring circuit, chip and electronic equipment

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Application publication date: 20120801