CN102611951A - Method for reducing power consumption of integrated circuit system of Ethernet passive optical network physical layer - Google Patents
Method for reducing power consumption of integrated circuit system of Ethernet passive optical network physical layer Download PDFInfo
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Abstract
The invention relates to a method for reducing power consumption of an integrated circuit system of an Ethernet passive optical network physical layer and designs a device for reducing power consumption of I/O (input/output) unit of an integrated circuit. The device is used as a module capable of being integrated into a physical layer integrated circuit. The method includes: encoding data before parallel binary data are transmitted to an I/O interface, computing the number of binary bits changed in two group data in adjacent clock period, turning and setting a zone bit as 1 if the number of changed bits is large; judging whether the data are turned or not according to the zone bits and turning and decoding according to the bits; dividing binary data into multiple sections for parallel I/O with wider bit width, and encoding and decoding the multiple sections; caching n data with bit width of m, grouping the n data and arranging n zone bits into data with bit width of m, and utilizing m-n binary bits without zone bits for checking, wherein the data are used a key frame.
Description
Technical field
The present invention relates to be used to reduce the method for Ethernet passive optical network Circuits System power consumption; Mainly be through coding/decoding and method that the coding/decoding mode is optimized; Reduce the power consumption of physical layer integrated circuit I/O unit, thereby reduce the peak power of system effectively.
Background technology
Mainly contain the power consumption of three kinds of technical methods reduction IC systems at present:
1. the technical scheme of prior art one
Through improving the manufacturing process of integrated circuit, reduce the power consumption of physical layer integrated circuit, thereby reduce the power consumption of system.
Usually the approach of the characteristic size through reducing the CMOS deep submicron integrated circuit realizes.Adopt more small-feature-size, mean that transistor can adopt shorter grid long, thereby reduce transistorized operating voltage, improve transistorized speed, practice thrift the area that transistor takies.On system level, then be reflected as level of integrated system and improve constantly, power consumption can further reduce under the situation that realizes same treatment efficient, is perhaps guaranteeing to promote treatment effeciency under the constant situation of power consumption
[1] [2]
The shortcoming of prior art one:
1) relevant with the technological innovation speed of whole semicon industry.Under the situation that does not occur manufacturing process of new generation as yet, be difficult to further improve power consumption.
2) for the person of designing and developing, can only contact Front-end Design, can't participate in the exploitation of the manufacturing process of rear end, very flexible.
3) variation of adopting new technology can bring product cost.Usually, introduce the remarkable increase that new technology can cause cost in a short time; Have only the wait long period,, just be expected to reduce the unit cost of product along with the progressively ripe and output increase of technology.
2. the technical scheme of prior art two
According to the size of traffic carrying capacity, the operating voltage of dynamic adjustments integrated circuit and clock frequency, the power consumption of saving Circuits System.
Prior art scheme two adds the function that can regulate dynamic frequency and voltage automatically in Circuits System.Specific monitoring circuit is used for the monitoring traffic amount; When business load is low, reduce the operating frequency and the operating voltage of a part of circuit; When traffic carrying capacity reaches higher load, use the supply voltage and the operating frequency of standard.Thereby practice thrift the power consumption of whole system
[3-6]
The shortcoming of prior art two:
1) this scheme can be practiced thrift Circuits System power consumption at one's leisure, but the power consumption can't reduce running at full capacity the time promptly can not reduce the system peak power consumption;
2) because technology two scheme power consumption can only reduce the spare time time can not reduce the system peak power consumption; And the power-supply system of equipment and cooling system all must design according to the peak load situation, and therefore technology two is helpless to reduce the design difficulty and the manufacturing cost of power-supply system and cooling system.
3. the technical scheme of prior art three
In equipment, add specific monitoring circuit, be used for the surveillance equipment port and whether have physical connection, and whether exist reception/transmission professional.If a part of port does not have physical connection, or there is not business on the link, then this partial circuit module of dormancy; When physical connection is recovered, wake these circuit up.Thereby use the power consumption of the equipment of saving
[1-2] [7-8]
The shortcoming of prior art three
1) with technological two shortcomings 1, this scheme can be practiced thrift Circuits System power consumption at one's leisure, but the power consumption can't reduce the equipment running at full capacity time promptly can not reduce the system peak power consumption.
2), can not reduce the design difficulty and the manufacturing cost of power-supply system and cooling system with technological two shortcomings 2.
3) state conversion process of sleeping/waking needs the time, possibly cause certain delay.
4) for guaranteeing to realize sleeping/waking timely under the prerequisite of lost packets not, need set up certain conversation mechanism, therefore possibly make an amendment the upper strata communications protocol.Operation easier is big, possibly have the compatibility issue between the hardware device.
[1] Zhong Tao, Wang Hao are. and the CMOS power consumption of integrated circuit is optimized and low power design technique [J]. microelectronics, 2000,30 (2): 106-112.
[2] Wei Chunjuan; Lv Jian. IC power consumption optimisation technique summary [J]. Shanghai University Of Electric Power's journal, 2011,27 (2): 187-192.
[3]?Shin?D,?Kim?J,?Lee?S.?Intra-Task?Voltage?Scheduling?for?Low-Energy?Hard?Real-Time?Applications?.IEEE?Design?and?Test?of?Computers,?2001,?18(2):20-30.
[4]?Benini?L,Paleologo?G,Bogliolo?A,et?al.?Policy?optimization?for?dynamic?power?management?.IEEE?Transactions?on?Computer-Aided?Design?of?Integrated?Circuits?and?Systems,?1999,?18?(6)?:813-833
[5]?CHUNG?E,BENINI?L,BOGLIOLO?A,et?al.?Dynamic?powermanagement?for?nonstationary?service?requests[J]?.IEEETrans.on?Computers,?2002,?51(11):1345-1360?.
[6] Jiang Qi, Xi Hongsheng, Yin Baoqun. the switching model at random of dynamic power management and policy optimization [J]. computer-aided design and graphics journal, 2006,18 (05): 680-686
[7] Tang Guangfei. high-performance router Study on energy saving (master thesis). the National University of Defense Technology, 2006.
[8] Wu Qi. embedded OS power managed technical research (doctorate paper). University of Electronic Science and Technology, 2006.
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Summary of the invention
Technical problem:Modern gigabit, 10,000,000,000 and the continuous increase of the ethernet device physical layer circuit system power dissipation of higher rate is one of hindering factor that further promotes business throughput.Simultaneously, manage to reduce its power consumption, especially peak power, also meet the theory of environment-friendly and energy-saving emission-reduction.The technical problem that the present invention mainly solves is, seeks a kind of effective ways, can effectively reduce by 10,000,000,000 and the peak power of the ethernet device physical layer integrated circuit system of higher rate, proposes the some kinds of algorithms that are used to reduce the physical layer integrated circuit system power dissipation.
Technical scheme:The present invention is a kind of method that is used to reduce Ethernet passive optical network physical layer integrated circuit system power dissipation; This method is used to reduce Ethernet passive optical network circuitry system peak power consumption; Be implemented in the physical layer integrated circuit of equipment,, reduce the power consumption of integrated circuit I/O unit through realizing following coding-decoding; Thereby reduce the peak power of whole system, concrete coding-coding/decoding method is:
The method 1 of coding-decoding: before parallel data signal is through the output of integrated circuit I/O unit, these data are encoded, at first read in data to be encoded; With a last number that the more corresponding binary digit of clock cycle coded data changes, half the then if the figure place that changes surpasses, then with data to be encoded step-by-step negate; And to put flag bit be 1; If it is half that the figure place that changes surpasses, then directly export data to be encoded, and to put flag bit be 0; During decoding, read in parallel data to be decoded; According to the value decoding of flag bit, if flag bit is 1, then step-by-step negate decoding, otherwise output initial value;
The method 2 of coding-decoding: before parallel data signal is through the output of integrated circuit I/O unit, these data are encoded; At first one group of parallel binary data is divided multistage; Each section encoded respectively; The coded system of each section is identical with method 1 coded system, merges each sub-coded data at last; During decoding, also data are divided multistage, each section decoding process is identical with method 1 decoding process, merges each son section decoded data at last;
The method 3 of coding-decoding: the numerical value that a counter at first is set is n, reads in parallel data to be encoded then, and establishing bit wide is m, and encodes by the coded system in the method 1, if read in data less than n, then continues to read in data and coding; If read in n data; Then n flag bit is arranged in the data of a m bit wide; M-n the binary digit of wherein not depositing flag bit is as verification, and as a key frame, the key frame that coded data and flag bit are formed is as one group with these data; Export this group data at last, and with counter zero setting; During decoding, after the reception data, at first analyze the grouping key frame, and deposit all flag bits, for the coded data in dividing into groups, by the decoding of the decoding process in the mode 1, last output decoder data.
Wherein, the concrete steps of the method 1 of coding-decoding are:
The flow process of coding method is:
Step 310: at first read in the present clock period data to be encoded;
Step 320: with the data step-by-step negate of reading in;
Step 330: on the one hand, in the direct memory register A of former data of reading in;
Step 331: on the other hand, the storage after the step-by-step negate is advanced among the register B;
Step 340: will go up one-period coded data put into register C;
Step 350: the coded data of last one-period among initial data among the register A and the register C is done the step-by-step XOR;
Step 351: data after the step-by-step negate among the register B and the coded data of last one-period among the register C are done the step-by-step XOR;
Step 360:, must be worth a with step 350 gained data step-by-step addition summation;
Step 361:, must be worth b with step 351 gained data step-by-step addition summation;
Step 370: do once to judge for the magnitude relationship of a and b;
Step 380: if a is not more than b, then the value of register A is final coding result, and putting flag bit is 0;
Step 381: if a greater than b, then the value of register B is final coding result, putting flag bit is 1;
Step 390: export final coding result;
Through above-mentioned judgement and cataloged procedure, during the transmission parallel data, formerly between latter two clock cycle, the number of times that the binary logic level signal that the I/O unit of integrated circuit is exported changes can effectively be reduced;
The flow process of coding/decoding method is:
Step 410: at first read in present clock period data to be decoded;
Step 420: flag bit is done once to judge;
Step 430:, be final decoded data then with the data after the data step-by-step negate to be decoded if flag bit is 1;
Step 431: if flag bit is not 1, then keep initial value, promptly former data to be decoded are final decoded data;
Step 440: export final decoded data.
The concrete steps of the method 2 of coding-decoding are:
The flow process of coding method is:
Step 510: at first read in the present clock period data to be encoded;
Step 520: data are split as many sub-section;
Step 530: each sub-section is wherein encoded by coded system in the method 1 of coding-decoding;
Step 540: merge each sub-section through encoding process;
Step 550: outputting encoded data and flag bit;
The flow process of coding/decoding method is:
Step 610: at first read in present clock period data to be decoded;
Step 620: data are split as many sub-section;
Step 630: each sub-section is wherein decoded by decoding process in the method 1 of coding-decoding;
Step 640: merge each sub-section through decoding processing;
Step 650: output decoder data.
The concrete steps of the method 3 of coding-decoding are:
The flow process of coding method is:
Step 700 a: counter is set and checks the numerical value of counter N;
Step 710: whether the value of judging counter N is N-1;
Step 720:, then read in data to be encoded if N is not N-1;
Step 730: data to be encoded are pressed encoded in the method 1 of coding-decoding;
Step 740: the flag bit of the gained of will encoding is stored among the registers group D;
Step 750: the value of counter N increases progressively 1;
Step 760:, then read in data among the registers group D if the value of N is N-1;
Step 770: calculation check position;
Step 780: flag bit, check digit are made up, play the effect of key frame;
Step 790: export whole coded data;
Step 7110: the value of counter N makes zero;
When decoding, at first read in decoded data, the key frame that the analysis mark position is formed; From key frame, extract flag bit, the value according to flag bit gets final product by the decoding of the decoding process in the method 1 of coding-decoding again.
Beneficial effect:
1) behind employing the present invention's " execution mode one " said method and the device, the number of times that upset takes place the I/O mouth of physical layer of device integrated circuit can effectively be reduced.Simulation result shows, even the upset of flag bit can increase the additional I/O of some expense of overturn, still, the whole I/O number summation of overturning still has obvious reduction, and the reduction amplitude is between 30%～20%.Because it is directly proportional with the upset number that the I/O unit consumes power consumption, use this method after, if I/O unit upset number has reduced by 30%, then the I/O unit consumes power consumption and also can reduce by 30%.Newly-increased in addition coding-decoding circuit may increase some extra power consumption, but the ratio that this newly-increased power consumption accounts for the entire chip power consumption is very low.Therefore, suppose that I/O unit power consumed accounts for 50% of entire chip power consumption, then the power consumption of entire chip can reduce by 15%.Can obtain the effect of considerable reduction peak power.
2) behind employing the present invention's " execution mode two " said method and the device,, can be directed against the particular type segment encoding of the binary data of its transmission, thereby further promote the power consumption optimizing efficiency for the parallel I/O of bit wide broad.
3) adopt the present invention's " execution mode three " said method and device, do not need the outer integrated circuit I/O mouth of occupying volume, do not increase the outer electric connection of extra sheet, being electrically connected etc. between PCB design, the integrated circuit can not change, and realizes simple relatively.
4) adopt the present invention's " execution mode one, two, three " said method and device, can effectively reduce peak power, reduce the design difficulty and the manufacturing cost of power-supply system and cooling system.
5) adopt the present invention's " execution mode one, two, three " said method and device, only change the physical layer circuit of device interior and the design of system, need not change, do not influence compatibility of apparatus existing international standard, communications protocol etc.
6) adopt the present invention's " execution mode one, two, three " said dress method and device, transparent to upper-layer protocol, need not coordinate with the upper strata communications protocol.
7) adopt the present invention's " execution mode one, two, three " said method and device, need not regroup the Control Software of equipment.
Description of drawings
Below in conjunction with accompanying drawing and execution mode the present invention is further specified.
Concern sketch map between the not improved ethernet device physical layer circuit of Fig. 1 internal system integrated circuit,
Fig. 2 uses between the ethernet device physical layer circuit internal system integrated circuit after the present invention improves and concerns sketch map,
Fig. 3 execution mode one coding method flow chart,
Fig. 4 execution mode one coding/decoding method flow chart,
Fig. 5 execution mode two coding method flow charts,
Fig. 6 execution mode two coding/decoding method flow charts,
Fig. 7 execution mode three coding method flow charts.
Embodiment
1. embodiment one of the present invention
Among Fig. 1, " integrated circuit 101 " is meant and is applied to integrated circuit, instantiation such as processor chips, memory chip etc. in the ethernet device physical layer circuit system, that have certain functional unit character, that be encapsulated as certain circuit element form.Its implementation can be field programmable gate array or the full application-specific integrated circuit (ASIC) that customizes etc.
Among Fig. 1, " sheet outer electric connection 102 " is meant that integrated circuit is connected with circuit between the integrated circuit, generally shows as the form of metal connecting line on the printed circuit board (PCB).
Among Fig. 1,, be meant the one group of I/O port that is used to transmit parallel data in the integrated circuit by " input/output interface 103 " of 1-N label.Generally be used for transmission height/low level digital logic signal.Inner function circuit needs the Parallel Digital logical signal of input (or output), will be through these I/O ports, by integrated circuit chip outer be electrically connected input (or outputing to integrated circuit chip being electrically connected on the circuit outward).The data one of parallel I/O integrated circuit have the N position if desired, then in requisition for taking N port.The value of N is generally 2 integer power, as 8,16,32,64 etc.
Relation is as shown in Figure 2 between the improved physical layer integrated circuit of the present invention institute.
The implication of " integrated circuit 201 " among Fig. 2, " the outer electric connection 202 of sheet " respectively with Fig. 1 in " integrated circuit 101 ", " the outer electric connection 102 of sheet " identical.
As shown in Figure 2, inner function circuit needs the Parallel Digital logical signal exporting/import, carry out coding/decoding through coding and decoding circuit 205 after, output/input again.After using decoding method, can practice thrift the power consumption of integrated circuit I/O module, thereby reduce this power consumption of integrated circuit, and then reduce the complete machine peak power of system.
Concrete grammar and workflow in the face of encoding and decoding describes down.
The flow chart of coding method is as shown in Figure 3.
Step 310: at first read in the present clock period data to be encoded;
Step 320: with the data step-by-step negate of reading in;
Step 330: on the one hand, in the direct memory register A of former data of reading in;
Step 331: on the other hand, the storage after the step-by-step negate is advanced among the register B;
Step 340: will go up one-period coded data put into register C;
Step 350: the coded data of last one-period among initial data among the register A and the register C is done the step-by-step XOR;
Step 351: data after the step-by-step negate among the register B and the coded data of last one-period among the register C are done the step-by-step XOR;
Step 360:, must be worth a with step 350 gained data step-by-step addition summation;
Step 361:, must be worth b with step 351 gained data step-by-step addition summation;
Step 370: do once to judge for the magnitude relationship of a and b;
Step 380: if a is not more than b, then the value of register A is final coding result, and putting flag bit is 0;
Step 381: if a greater than b, then the value of register B is final coding result, putting flag bit is 1;
Step 390: export final coding result.
Through above-mentioned judgement and cataloged procedure, during the transmission parallel data, formerly between latter two clock cycle, the number of times that the binary logic level signal that the I/O unit of integrated circuit is exported changes can effectively be reduced.
The flow chart of coding/decoding method is as shown in Figure 4.
Step 410: at first read in present clock period data to be decoded;
Step 420: flag bit is done once to judge;
Step 430:, be final decoded data then with the data after the data step-by-step negate to be decoded if flag bit is 1;
Step 431: if flag bit is not 1, then keep initial value, promptly former data to be decoded are final decoded data;
Step 440: export final decoded data.
Illustrate execution mode one at present, as read in data be 8 11001010, then deposit 11001010 among the register A; Deposit 00110101 among the register B, the coded data of supposing last one-period among the register C is 11111000, and data step-by-step XOR is 00110010 among register A and the C; The step-by-step addition gets a=3, and data step-by-step XOR is 11001101 among register B and the C, and the step-by-step addition gets b=5; A is less than b, so final coding is output as 11001010, flag bit is 0.During decoding, reading in flag bit is 0, so the output of can decoding is exactly 11001010.At this moment, the data behind the coding are exactly initial value, compare with the coded data of last one-period, and 3 needs upsets are arranged.
Suppose that the data of reading in again are 00110100, then deposit 00110100 among the register A, deposit 11001011 among the register B; Be coded data 11001010 of last one-period among the register C, data step-by-step XOR gets 11111110 among register A and the C, and the step-by-step addition gets a=7; Data step-by-step XOR gets 00000001 among register B and the C, and the step-by-step addition gets b=1, and a is greater than b; So final coding is output as 11001011, flag bit is 1.During decoding, reading in flag bit is 1, so with data 11001011 step-by-step negates, decoding back data are 00110100.Coded data had been compared 1 bit flipping with the coded data of last one-period, if initial value has 7 bit flippings without directly output of coding, thus reduced the power consumption of I/O port, thus the system power dissipation of integrated circuit lowered.
2. embodiment two of the present invention
This execution mode two mainly is that the detailed operation flow process of coding and decoding device and decoding method of being adopted etc. are adjusted and improved.
Because in some cases, if adopt the encoding scheme of execution mode one, the effect that reduces the upset of I/O unit may reduce along with the increase of parallel I/O bit wide.Especially transmission during some specific data type (when transmitting that former and later two cycles, only there was the floating data of a small amount of variation in some mantissa).Therefore, this execution mode two proposes to improve one's methods, and data to be encoded are split as multistage.According to the difference of the binary system parallel data type of transmitting, can encode respectively to multistage, or only center molecule section encoded.
The flow chart of coding method is as shown in Figure 5.
Step 510: at first read in the present clock period data to be encoded;
Step 520: data are split as many sub-section;
Step 530: each sub-section is wherein encoded by coded system in the method 1 of coding-decoding;
Step 540: merge each sub-section through encoding process;
Step 550: outputting encoded data and flag bit.
The flow chart of coding/decoding method is as shown in Figure 6.
Step 610: at first read in present clock period data to be decoded;
Step 620: data are split as many sub-section;
Step 630: each sub-section is wherein decoded by decoding process in the method 1 of coding-decoding;
Step 640: merge each sub-section through decoding processing;
Step 650: output decoder data.
The beneficial effect that this method can be brought mainly is, for the parallel I/O of bit wide broad, can further promote the power consumption optimization efficiency to the particular type of the binary data of its transmission.
For example, carry out encoding and decoding, can be divided into 8 sub-section by execution mode two to one 64 bit data, 8 of every sub-section, to the encoding and decoding respectively of 8 sub-section, the decoding method of every sub-section is identical with the method for embodiment one again.
3. embodiment three of the present invention
Execution mode three is with the difference of execution mode one; Because the workflow of coding and decoding device and the decoding method that is adopted etc. are adjusted and are improved; Cataloged procedure can not produce the flag bit that needs extra I/O oral instructions defeated, thereby has practiced thrift the I/O port number.
Because execution mode three does not increase extra integrated circuit I/O mouth; Do not increase the outer electric connection of extra sheet; Therefore when being applied to ethernet device physical layer circuit system, existing printed circuit board (PCB), integrated circuit directly are electrically connected etc. and need make an amendment.
The coding method flow process is as shown in Figure 7.
Existing I/O bus with one 8 bit wide is the example explanation:
Step 700 a: counter is set and checks the numerical value of counter N;
Step 710: whether the value of judging counter N is 7;
Step 720:, then read in data to be encoded if N is not 7;
Step 730: data to be encoded are pressed encoded in the method 1 of coding-decoding;
Step 740: the flag bit of the gained of will encoding is stored among the registers group D;
Step 750: the value of counter N increases progressively 1;
Step 760:, then read in data among the registers group D if the value of N is 7;
Step 770: calculation check position;
Step 780: flag bit, check digit are made up, play the effect of key frame;
Step 790: export whole coded data;
Step 7110: the value of counter N makes zero.
For the I/O bus of 16 bit wides, in like manner available 15 cycles are used to read in data to be encoded, coding output; The 16th cycle is with the flag bit array output in preceding 15 cycles.More the coding method of 32,64,128 of high-bit width buses is similar with it.
In when decoding, the key frame formed of analysis mark position at first; Value according to key frame extracts flag bit, gets final product according to coding/decoding method decoding in the value occupation mode one of flag bit again.
Claims (4)
1. method that is used to reduce Ethernet passive optical network physical layer integrated circuit system power dissipation, its spy
Levy and be; This method is used to reduce Ethernet passive optical network circuitry system peak power consumption; Be implemented in the physical layer integrated circuit of equipment,, reduce the power consumption of integrated circuit I/O unit through realizing following coding-decoding; Thereby reduce the peak power of whole system, concrete coding-coding/decoding method is:
The method 1 of coding-decoding: before parallel data signal is through the output of integrated circuit I/O unit, these data are encoded, at first read in data to be encoded; With a last number that the more corresponding binary digit of clock cycle coded data changes, half the then if the figure place that changes surpasses, then with data to be encoded step-by-step negate; And to put flag bit be 1; If it is half that the figure place that changes surpasses, then directly export data to be encoded, and to put flag bit be 0; During decoding, read in parallel data to be decoded; According to the value decoding of flag bit, if flag bit is 1, then step-by-step negate decoding, otherwise output initial value;
The method 2 of coding-decoding: before parallel data signal is through the output of integrated circuit I/O unit, these data are encoded; At first one group of parallel binary data is divided multistage; Each section encoded respectively; The coded system of each section is identical with method 1 coded system, merges each sub-coded data at last; During decoding, also data are divided multistage, each section decoding process is identical with method 1 decoding process, merges each son section decoded data at last;
The method 3 of coding-decoding: the numerical value that a counter at first is set is n, reads in parallel data to be encoded then, and establishing bit wide is m, and encodes by the coded system in the method 1, if read in data less than n, then continues to read in data and coding; If read in n data; Then n flag bit is arranged in the data of a m bit wide; M-n the binary digit of wherein not depositing flag bit is as verification, and as a key frame, the key frame that coded data and flag bit are formed is as one group with these data; Export this group data at last, and with counter zero setting; During decoding, after the reception data, at first analyze the grouping key frame, and deposit all flag bits, for the coded data in dividing into groups, by the decoding of the decoding process in the mode 1, last output decoder data.
2. according to claim 1ly be used to reduce Ethernet passive optical network physical layer integrated circuit system
The method of power consumption, the concrete steps of the method 1 of coding-decoding are:
The flow process of coding method is:
Step 310: at first read in the present clock period data to be encoded;
Step 320: with the data step-by-step negate of reading in;
Step 330: on the one hand, in the direct memory register A of former data of reading in;
Step 331: on the other hand, the storage after the step-by-step negate is advanced among the register B;
Step 340: will go up one-period coded data put into register C;
Step 350: the coded data of last one-period among initial data among the register A and the register C is done the step-by-step XOR;
Step 351: data after the step-by-step negate among the register B and the coded data of last one-period among the register C are done the step-by-step XOR;
Step 360:, must be worth a with step 350 gained data step-by-step addition summation;
Step 361:, must be worth b with step 351 gained data step-by-step addition summation;
Step 370: do once to judge for the magnitude relationship of a and b;
Step 380: if a is not more than b, then the value of register A is final coding result, and putting flag bit is 0;
Step 381: if a greater than b, then the value of register B is final coding result, putting flag bit is 1;
Step 390: export final coding result;
Through above-mentioned judgement and cataloged procedure, during the transmission parallel data, formerly between latter two clock cycle, the number of times that the binary logic level signal that the I/O unit of integrated circuit is exported changes can effectively be reduced;
The flow process of coding/decoding method is:
Step 410: at first read in present clock period data to be decoded;
Step 420: flag bit is done once to judge;
Step 430:, be final decoded data then with the data after the data step-by-step negate to be decoded if flag bit is 1;
Step 431: if flag bit is not 1, then keep initial value, promptly former data to be decoded are final decoded data;
Step 440: export final decoded data.
3. according to claim 1ly be used to reduce Ethernet passive optical network physical layer integrated circuit system
The method of power consumption, the concrete steps of the method 2 of coding-decoding are:
The flow process of coding method is:
Step 510: at first read in the present clock period data to be encoded;
Step 520: data are split as many sub-section;
Step 530: each sub-section is wherein encoded by coded system in the method 1 of coding-decoding;
Step 540: merge each sub-section through encoding process;
Step 550: outputting encoded data and flag bit;
The flow process of coding/decoding method is:
Step 610: at first read in present clock period data to be decoded;
Step 620: data are split as many sub-section;
Step 630: each sub-section is wherein decoded by decoding process in the method 1 of coding-decoding;
Step 640: merge each sub-section through decoding processing;
Step 650: output decoder data.
4. according to claim 1ly be used to reduce Ethernet passive optical network physical layer integrated circuit system
The method of power consumption, the concrete steps of the method 3 of coding-decoding are:
The flow process of coding method is:
Step 700 a: counter is set and checks the numerical value of counter N;
Step 710: whether the value of judging counter N is N-1;
Step 720:, then read in data to be encoded if N is not N-1;
Step 730: data to be encoded are pressed encoded in the method 1 of coding-decoding;
Step 740: the flag bit of the gained of will encoding is stored among the registers group D;
Step 750: the value of counter N increases progressively 1;
Step 760:, then read in data among the registers group D if the value of N is N-1;
Step 770: calculation check position;
Step 780: flag bit, check digit are made up, play the effect of key frame;
Step 790: export whole coded data;
Step 7110: the value of counter N makes zero;
When decoding, at first read in decoded data, the key frame that the analysis mark position is formed; From key frame, extract flag bit, the value according to flag bit gets final product by the decoding of the decoding process in the method 1 of coding-decoding again.
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