CN102610641B - High-voltage LDMOS (laterally diffused metal oxide semiconductor) device and manufacturing method thereof - Google Patents
High-voltage LDMOS (laterally diffused metal oxide semiconductor) device and manufacturing method thereof Download PDFInfo
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Abstract
The invention discloses a high-voltage LDMOS (laterally diffused metal oxide semiconductor) device. A special-shaped doped ring surrounding the lead-out end of a heavily-doped drain region is led to the drain end of a common high-voltage LDMOS device; and the drift region, body region and source end of the original LDMOS device form a parasitic SCR (silicon controlled rectifier) device through the special-shaped doped ring. On one hand, the current distribution after the LDMOS is turned on can reduce the turn-on voltage of the parasitic SCR device; and on the other hand, after the parasitic SCR device is turned on, the specific on-resistance of the whole device can be reduced due to the high electric conductivity of the SCR. The high-voltage LDMOS device disclosed by the invention is actually a composite device structure of a common LDMOS device and an SCR device, which sufficiently utilizes the advantages of the LDMOS device and the SCR device, realizes high reverse breakdown voltage and reduces the specific on-resistance of the device under a certain working bias condition.
Description
Technical field
The present invention relates to a kind of high-voltage LDMOS (Laterally Diffused Metal OxideSemiconductor, Laterally Diffused Metal Oxide Semiconductor) device.
Background technology
For high-voltage LDMOS device, puncture voltage (Breakdowm Voltage, BV) and conduction resistance (on-resistance, Rsp) are a pair of very important technical indicators that needs balance.Withstand voltage and the conduction resistance of high pressure DMOS device depends on the compromise selection of doping content, thickness and the drift region length of epitaxial loayer.High puncture voltage requires thick light dope epitaxial loayer and long drift region, low conduction resistance requires thin heavy doping epitaxial loayer and short drift region, therefore must select best extension parameter and drift region length, to meeting under the prerequisite of certain source drain breakdown voltage, obtain minimum conduction resistance.
And for SCR (Silicon Controlled Rectifiers, silicon controlled rectifier) device, due to the characteristic of negative differential resistance under specified conditions, after opening, device there is very strong conductive capability, conduction resistance is less, but it is higher that its device is opened required voltage, be relatively difficult to open-minded.
Summary of the invention
Technical problem to be solved by this invention is to provide a kind of high-voltage LDMOS device simultaneously with high-breakdown-voltage and low conduction resistance.For this reason, the present invention also will provide the manufacture method of described high-voltage LDMOS device.
For solving the problems of the technologies described above, the structure of high-voltage LDMOS device of the present invention is: in low-doped substrate, have drift region and tagma, the doping type of drift region is contrary with substrate, and the doping type in tagma is identical with substrate; Have drift region inversion layer on the surface of drift region, the doping type of drift region inversion layer is contrary with drift region; There is isolation structure one on the surface in tagma; Have isolation structure two on the surface of drift region, isolation structure two is also on the inversion layer of drift region; Also there is isolation structure three and isolation structure four on the surface of drift region; On tagma and isolation structure two, there is polysilicon gate and polysilicon field plate; One end of polysilicon gate is on tagma, and the other end is on isolation structure two; Polysilicon field plate is on isolation structure two; Among tagma, have body electrode leads to client and source region exit, body electrode leads to client is between isolation structure one and source region exit, and doping type is contrary with source region exit; Source region exit is between body electrode leads to client and polysilicon gate, and doping type is contrary with tagma; Among drift region, have drain region exit and transoid doping ring, the doping type of drain region exit is identical with the doping type of drift region, and the doping type of transoid doping ring is contrary with drain region exit; Described transoid doping ring is rendered as annular round drain region exit from depression angle, is rendered as the structure of two sections of spaces from analysing and observe angle, and a segment structure is wherein between isolation structure two and isolation structure three; Drain region exit 10 is between isolation structure three and isolation structure four; Source electrode, grid and drain electrode are metal electrode; The bottom of source electrode is contact electrode leads to client and source electrode exit simultaneously; The bottom contact polysilicon gate of grid; The bottom of drain electrode contacts drain terminal polysilicon field plate, transoid doping ring and drain region exit simultaneously.
The method of manufacturing above-mentioned high-voltage LDMOS device comprises the steps:
The 1st step adopts photoetching process and ion implantation technology to form drift region on low-doped substrate, and the doping type of drift region is contrary with substrate;
The 2nd step adopts photoetching process and ion implantation technology to form tagma on low-doped substrate, and the doping type in tagma is identical with substrate;
The 3rd step adopts photoetching process and ion implantation technology to form drift region inversion layer on drift region, and the doping type of drift region inversion layer is contrary with drift region;
The 4th step, forms multiple isolation structures at silicon chip surface, and wherein isolation structure one is on the surface in tagma, and isolation structure two is on the surface of drift region and on the inversion layer of drift region, and isolation structure three, isolation structure four are all on the surface of drift region;
The 5th step, at silicon chip surface one deck gate oxide of first growing, then deposit one deck polysilicon, thereby this layer of polysilicon of etching and gate oxide form polysilicon gate and drain terminal polysilicon field plate; One end of polysilicon gate is on tagma, and the other end is on isolation structure two; Drain terminal polysilicon field plate is on isolation structure two;
The 6th step, carries out heavy doping ion injection formation source region exit and drain region exit in tagma and drift region, and the type of Implantation is identical with the type of drift region; Source region exit is among tagma and near one end of polysilicon gate; Drain region exit is among drift region and between isolation structure three and isolation structure four;
The 7th step, carries out and source electrode, the contrary Implantation of doping type that drains, organizator electrode leads to client and the annular doping district around drain region exit in tagma and drift region; Body electrode leads to client is among tagma and between isolation structure one and source region exit; Annular doping district claims again transoid doping ring or special shaped doped ring, among drift region and round drain region exit, observes and presents annular from depression angle, is rendered as the structure of two sections of spaces from analysing and observe angle; Wherein a segment structure in annular doping district is between isolation structure two and isolation structure three, and drain region exit is between isolation structure three and isolation structure four;
The 8th step, first deposition of dielectric layer, then etches contact hole, and in contact hole, fills metal electrode, forms resulting devices; Metal electrode comprises source electrode, grid and drain electrode; The bottom of source electrode is contact electrode leads to client and source electrode exit simultaneously; The bottom contact polysilicon gate of grid; The bottom of drain electrode contacts drain terminal polysilicon field plate, transoid doping ring and drain region exit simultaneously.
Or the structure of high-voltage LDMOS device of the present invention is: have drift region and tagma in low-doped substrate, the doping type of drift region is contrary with substrate, and the doping type in tagma is identical with substrate; Have drift region inversion layer on the surface of drift region, the doping type of drift region inversion layer is contrary with drift region; There is isolation structure one on the surface in tagma; Have isolation structure two on the surface of drift region, isolation structure two is also on the inversion layer of drift region; Surface in drift region also has isolation structure three; On tagma and isolation structure two, there is polysilicon gate and polysilicon field plate; One end of polysilicon gate is on tagma, and the other end is on isolation structure two; Polysilicon field plate is on isolation structure two; Among tagma, have body electrode leads to client and source region exit, body electrode leads to client is between isolation structure one and source region exit, and doping type is identical with tagma; Source region exit is between body electrode leads to client and polysilicon gate, and doping type is contrary with tagma; Among drift region, have drain region exit and transoid doping ring, the doping type of drain region exit is identical with the doping type of drift region, and the doping type of transoid doping ring is contrary with drain region exit; Described transoid doping ring is rendered as annular round drain region exit from depression angle, is rendered as the structure of two sections of spaces from analysing and observe angle, and a segment structure is wherein between isolation structure two and drain region exit; Drain region exit is between transoid doping ring and isolation structure three c; Source electrode, grid and drain electrode are metal electrode; The bottom of source electrode is contact electrode leads to client and source electrode exit simultaneously; The bottom contact polysilicon gate of grid; The bottom of drain electrode contacts drain terminal polysilicon field plate, transoid doping ring and drain region exit simultaneously.
The method of manufacturing above-mentioned high-voltage LDMOS device comprises the steps:
The 1st step adopts photoetching process and ion implantation technology to form drift region on low-doped substrate, and the doping type of drift region is contrary with substrate;
The 2nd step adopts photoetching process and ion implantation technology to form tagma on low-doped substrate, and the doping type in tagma is identical with substrate;
The 3rd step adopts photoetching process and ion implantation technology to form drift region inversion layer on drift region, and the doping type of drift region inversion layer is contrary with drift region;
The 4th step, forms multiple isolation structures at silicon chip surface, and wherein isolation structure one is on the surface in tagma, and isolation structure two is the surperficial of drift region and on the inversion layer of drift region, isolation structure three is on the surface of drift region;
The 5th step, at silicon chip surface one deck gate oxide of first growing, then deposit one deck polysilicon, thereby this layer of polysilicon of etching and gate oxide form polysilicon gate and drain terminal polysilicon field plate; One end of polysilicon gate is on tagma, and the other end is on isolation structure two; Drain terminal polysilicon field plate is on isolation structure two;
The 6th step, carries out heavy doping ion injection formation source region exit and drain region exit in tagma and drift region, and the type of Implantation is identical with drift region; Source region exit is among tagma and near one end of polysilicon gate; Drain region exit is among drift region and between isolation structure two and isolation structure three;
The 7th step, carries out and source electrode, the contrary Implantation of doping type that drains, organizator electrode leads to client and the annular doping district around drain region exit in tagma and drift region; Body electrode leads to client is among tagma and between isolation structure one and source region exit; Annular doping district claims again transoid doping ring or special shaped doped ring, among drift region and round drain region exit, observe and present annular from depression angle, be rendered as the structure of two sections of spaces from analysing and observe angle, wherein a segment structure is between isolation structure two and drain region exit, and drain region exit is between annular doping district and isolation structure three;
The 8th step, first deposition of dielectric layer, then etches contact hole, and in contact hole, fills metal electrode, forms resulting devices; Metal electrode comprises source electrode, grid and drain electrode; The bottom of source electrode is contact electrode leads to client and source electrode exit simultaneously; The bottom contact polysilicon gate of grid; The bottom of drain electrode contacts drain terminal polysilicon field plate, transoid doping ring and drain region exit simultaneously.
High-voltage LDMOS device of the present invention is introduced the special shaped doped ring around highly doped drain region exit at the drain terminal of common high-voltage LDMOS device, and this special shaped doped ring will form parasitic SCR device with drift region, tagma and the source of former LDMOS device.On the one hand, the CURRENT DISTRIBUTION after LDMOS conducting can reduce the turning-on voltage of parasitic SCR device.On the other hand, after this parasitic SCR device is opened, because the high conductive capability of SCR can reduce the conducting resistance of whole device.Like this, high-voltage LDMOS device of the present invention is actually the multiple device structure of common LDMOS device and SCR device, take full advantage of LDMOS and SCR device advantage separately, realize in meeting high reverse breakdown voltage, under certain working bias voltage condition, reduce the conducting resistance of device.
Accompanying drawing explanation
Fig. 1 is the profile of an embodiment of high-voltage LDMOS device of the present invention;
Fig. 2 is the profile of another embodiment of high-voltage LDMOS device of the present invention;
Fig. 3 is the I-V characteristic curve of high-voltage LDMOS device of the present invention and traditional LDMOS device;
Fig. 4 a～Fig. 4 h is the each step schematic diagram of manufacture method of high-voltage LDMOS device of the present invention.
Description of reference numerals in figure:
1 is source electrode; 2 is grid; 3 is drain electrode; 4 is body electrode leads to client; 5 is source region exit; 6 is tagma; 7 is drift region surface inversion layer; 8 is drift region; 9 is low-doped substrate; 10 is drain region exit; 11 is isolation structure; 12 is dielectric substance layer; 13 is drain terminal transoid doping ring.
Embodiment
Refer to Fig. 1, this is an embodiment of high-voltage LDMOS device of the present invention.In low-doped substrate 9, there is deep high voltage well 8 and low pressure trap 6.The doping type of deep high voltage well 8 is contrary with substrate 9, as drift region.The doping type of low pressure trap 6 is identical with substrate 9, as tagma.Have trap 7 on the surface of drift region 8, the doping type of trap 7 is contrary with drift region 8, as drift region inversion layer.There is isolation structure one 11a on the surface in tagma 6.Have isolation structure two 11b on the surface of drift region 8, isolation structure 11b is also on drift region inversion layer 7.Also have isolation structure three 11c and isolation structure four 11d on the surface of drift region 8, isolation structure three 11c and isolation structure four 11d are not all on drift region inversion layer 7.On tagma 6 and isolation structure two 11b, there is polysilicon gate 20a and polysilicon field plate 20b.One end of polysilicon gate 20a is on tagma 6, and the other end is on isolation structure two 11b.Polysilicon field plate 20b is on isolation structure two 11b.Among tagma 6, there is body electrode leads to client 4 and source region exit 5.Body electrode leads to client 4 is between isolation structure one 11a and source region exit 5, and doping type is contrary with source region exit 5.Source region exit 5 is between body electrode leads to client 4 and polysilicon gate 20a, and its doping type is contrary with tagma 6.Among drift region 8, there is drain region exit 10 and transoid doping ring 13.The doping type of drain region exit 10 is identical with drift region 8, and the doping type of transoid doping ring 13 is contrary with drain region exit 10.Transoid doping ring 13 is wherein rendered as annular round drain region exit 10 from depression angle.From cutaway view, 13, transoid doping ring is rendered as the structure of two sections of spaces, a segment structure is wherein between isolation structure two 11b and isolation structure three 11c, another segment structure not shown (can obtain as center line symmetry by boundary line on the right of Fig. 1 In a particular embodiment).Drain region exit 10 is between isolation structure three 11c and isolation structure four 11d.Source electrode 1, grid 2 and drain electrode 3 are metal electrode.The wherein bottom of source electrode 1 contact electrode leads to client 4 and source electrode exit 5 simultaneously.The bottom contact polysilicon gate 20a of grid 2.The bottom of drain electrode 3 contacts drain terminal polysilicon field plate 20b, transoid doping ring 13 and drain region exit 10 simultaneously.
Refer to Fig. 2, this is another embodiment of high-voltage LDMOS device of the present invention.Compared to Figure 1 difference is that drain region exit 10 encircles 13 relation with the transoid doping around drain region exit 10.In Fig. 1, isolated with an isolation structure 11 between drain region exit 10 and the transoid doping ring 13 around drain region exit 10.In Fig. 2, drain region exit 10 all in active area, has omitted an isolation structure 11 with transoid doping ring 13 between transoid doping ring 13 and drain region exit 10.
Particularly, in the embodiment of Fig. 2, there is isolation structure one 11a on the surface in tagma 6.Have isolation structure two 11b on the surface of drift region 8, isolation structure 11b is also on drift region inversion layer 7.Also have isolation structure three 11c on the surface of drift region 8, isolation structure three 11c are not on drift region inversion layer 7.Transoid doping ring 13 is wherein rendered as annular round drain region exit 10 from depression angle.From cutaway view, 13, transoid doping ring is rendered as the structure of two sections of spaces, a segment structure is wherein between isolation structure two 11b and drain region exit 10, another segment structure not shown (can obtain as center line symmetry by boundary line on the right of Fig. 1 In a particular embodiment).Drain region exit 10 is between transoid doping ring 13 and isolation structure three 11c.
Refer to Fig. 3, this is the relatively schematic diagram of I-V (current-voltage) characteristic of high-voltage LDMOS device of the present invention and common high-voltage LDMOS device.The I-V characteristic that wherein solid line is high-voltage LDMOS device of the present invention, dotted line is common high-voltage LDMOS structure I-V characteristic with same voltage endurance capability, A point is two characteristic crosspoints of I-V.As can be seen from Figure 3, at added drain terminal bias voltage, during lower than A point bias voltage, the electric current of the current ratio high-voltage LDMOS device of the present invention of common high-voltage LDMOS device is slightly large, and this is because the drift region of high-voltage LDMOS device of the present invention is slightly long, causes electric current smaller.When drain terminal bias voltage is greater than after A point bias voltage, the parasitic SCR in high-voltage LDMOS device of the present invention is open-minded, causes electric current to increase.As can be seen from the results, by introducing the transoid doping ring around highly doped drain region exit, in high-voltage LDMOS device, form a parasitic SCR structure, thereby under certain bias condition, can greatly improve the conductive capability of device, reduced the conduction resistance of device.
The manufacture method of high-voltage LDMOS device of the present invention (take Fig. 1 as example) comprises the steps:
The 1st step, refers to Fig. 4 a, adopts photoetching process and ion implantation technology to form drift region 8 on low-doped substrate 9, and the doping type of drift region 8 is contrary with substrate 9.Particularly, first utilize photoresist to open subregion and carry out the Implantation contrary with the doping type of substrate 9, advance (being annealing process) by high temperature, form deep high voltage well 8, as drift region.
The 2nd step, refers to Fig. 4 b, adopts photoetching process and ion implantation technology to form tagma 6 on low-doped substrate 9, and the doping type in tagma 6 is identical with substrate 9.Particularly, first utilize photoresist to open subregion and carry out the Implantation identical with the doping type of substrate 9, advance (being annealing process) by high temperature, form low pressure well region 6, as tagma.
The 3rd step, refers to Fig. 4 c, adopts photoetching process and ion implantation technology to form drift region inversion layer 7 on device drift region 8.Particularly, first utilize photoresist to open subregion and carry out the Implantation contrary with the doping type of drift region 8, the ion implanted region 7 forming is as drift region inversion layer.
The 4th step, refers to Fig. 4 d, forms multiple isolation structures 11 at silicon chip surface.These multiple isolation structures 11 are silica, can be oxygen isolation (LOCOS) or the manufacture of shallow-trench isolation (STI) technique.Wherein isolation structure one 11a is on the surface in tagma 6, and isolation structure two 11b are on the surface of drift region 8 and on drift region inversion layer 7, and isolation structure three 11c, isolation structure four 11d are on the surface of drift region 8 and all not on drift region inversion layer 7.
The 5th step, refers to Fig. 4 e, at the silicon chip surface one deck gate oxide (not shown) of first growing, then deposit one deck polysilicon 20, thereby etching this layer of polysilicon 20 and gate oxide form polysilicon gate 20a and drain terminal polysilicon field plate 20b.One end of polysilicon gate 20a is on tagma 6, and the other end is on isolation structure two 11b.Drain terminal polysilicon field plate 20b is on close isolation structure two 11b of drain terminal.
The 6th step, refers to Fig. 4 f, carries out heavy doping ion injection formation source region exit 5 and drain region exit 10 in source (tagma 6) and drain terminal (drift region 8), and the type of Implantation is identical with drift region.Source region exit 5 is among tagma 6 and near one end of polysilicon gate 20a.Drain region exit 10 is among drift region 8 and between isolation structure three 11c and isolation structure four 11d.
The 7th step, refers to Fig. 4 g, carries out and source electrode, the contrary Implantation of doping type that drains, organizator electrode leads to client 4 and the annular doping district 13 around drain region exit 10 in source (tagma 6) and drain terminal (drift region 8).Body electrode leads to client 4 is among tagma 6 and between isolation structure one 11a and source region exit 5.Annular doping district 13 claims again transoid doping ring or special shaped doped ring, among drift region 8 and round drain region exit 10, observes and presents annular from depression angle, is rendered as the structure of two sections of spaces from cutaway view.Wherein a segment structure in annular doping district 13 is between isolation structure two 11b and isolation structure three 11c, and another segment structure is not shown.Drain region exit 10 is between isolation structure three 11c and isolation structure four 11d.
The 8th step, refers to Fig. 4 h, and postchannel process is standard CMOS postchannel process flow process, and first deposition of dielectric layer 12, then etches contact hole, and in contact hole, fills metal electrode, forms resulting devices.Metal electrode comprises source electrode 1, grid 2 and drain electrode 3.The wherein bottom of source electrode 1 contact electrode leads to client 4 and source electrode exit 5 simultaneously.The bottom contact polysilicon gate 20a of grid 2.The bottom of drain electrode 3 contacts drain terminal polysilicon field plate 20b, transoid doping ring 13 and drain region exit 10 simultaneously.
Before described method the 3rd step can also be placed on the 2nd step, or before being placed on the 5th step.
The manufacture method of above-mentioned high-voltage LDMOS device is also applicable to the high-voltage LDMOS device shown in shop drawings 2, just in the 4th step, form less an isolation structure 11, simultaneously in the 7th step: annular doping district 13 is rendered as the structure of two sections of spaces from cutaway view, wherein a segment structure is between isolation structure two 11b and drain region exit 10, and another segment structure is not shown.Drain region exit 10 is between annular doping district 13 and isolation structure three 11c.
According to the requirement of process conditions and device property, can optimize the structure of special shaped doped ring 13 and drain region exit 10, and increase the method for a dedicated mask plate and regulate the CONCENTRATION DISTRIBUTION (this dedicated mask plate and corresponding processing step thereof also can be adjusted its order in whole technological process and change the CONCENTRATION DISTRIBUTION in opposite sex doping ring 13) in special shaped doped ring 13, realize equally the present invention.
In sum, high-voltage LDMOS device of the present invention is introduced the special shaped doped ring around highly doped drain region exit by the drain terminal at common high-voltage LDMOS device, and this special shaped doped ring will form parasitic SCR device with drift region, tagma and the source of former LDMOS device.On the one hand, the CURRENT DISTRIBUTION after LDMOS conducting can reduce the turning-on voltage of parasitic SCR device.On the other hand, after this parasitic SCR device is opened, because the high conductive capability of SCR can reduce the conducting resistance of whole device.Like this, high-voltage LDMOS device of the present invention is actually the multiple device structure of common LDMOS device and SCR device, take full advantage of LDMOS and SCR device advantage separately, realize in meeting high reverse breakdown voltage, under certain working bias voltage condition, reduce the conducting resistance of device.
Claims (6)
1. a high-voltage LDMOS device, is characterized in that, the structure of described high-voltage LDMOS device is:
In low-doped substrate, have drift region and tagma, the doping type of drift region is contrary with substrate, and the doping type in tagma is identical with substrate;
Have drift region inversion layer on the surface of drift region, the doping type of drift region inversion layer is contrary with drift region;
There is isolation structure one on the surface in tagma; Have isolation structure two on the surface of drift region, isolation structure two is also on the inversion layer of drift region; Also there is isolation structure three and isolation structure four on the surface of drift region;
On tagma and isolation structure two, there is polysilicon gate and polysilicon field plate; One end of polysilicon gate is on tagma, and the other end is on isolation structure two; Polysilicon field plate is on isolation structure two;
Among tagma, have body electrode leads to client and source region exit, body electrode leads to client is between isolation structure one and source region exit, and doping type is identical with tagma doping type; Source region exit is between body electrode leads to client and polysilicon gate, and doping type is contrary with tagma;
Among drift region, have drain region exit and transoid doping ring, the doping type of drain region exit is identical with drift region, and the doping type of transoid doping ring is contrary with drain region exit; Described transoid doping ring is rendered as annular round drain region exit from depression angle, is rendered as the structure of two sections of spaces from analysing and observe angle, and a segment structure is wherein between isolation structure two and isolation structure three; Drain region exit 10 is between isolation structure three and isolation structure four;
Source electrode, grid and drain electrode are metal electrode; The bottom of source electrode is contact electrode leads to client and source electrode exit simultaneously; The bottom contact polysilicon gate of grid; The bottom of drain electrode contacts drain terminal polysilicon field plate, transoid doping ring and drain region exit simultaneously.
2. a high-voltage LDMOS device, is characterized in that, the structure of described high-voltage LDMOS device is:
In low-doped substrate, have drift region and tagma, the doping type of drift region is contrary with substrate, and the doping type in tagma is identical with substrate;
Have drift region inversion layer on the surface of drift region, the doping type of drift region inversion layer is contrary with drift region;
There is isolation structure one on the surface in tagma; Have isolation structure two on the surface of drift region, isolation structure two is also on the inversion layer of drift region; Surface in drift region also has isolation structure three;
On tagma and isolation structure two, there is polysilicon gate and polysilicon field plate; One end of polysilicon gate is on tagma, and the other end is on isolation structure two; Polysilicon field plate is on isolation structure two;
Among tagma, have body electrode leads to client and source region exit, body electrode leads to client is between isolation structure one and source region exit, and doping type is identical with tagma; Source region exit is between body electrode leads to client and polysilicon gate, and doping type is contrary with tagma;
Among drift region, have drain region exit and transoid doping ring, the doping type of drain region exit is identical with drift region, and the doping type of transoid doping ring is contrary with drift region; Described transoid doping ring is rendered as annular round drain region exit from depression angle, is rendered as the structure of two sections of spaces from analysing and observe angle, and a segment structure is wherein between isolation structure two and drain region exit; Drain region exit is between transoid doping ring and isolation structure three;
Source electrode, grid and drain electrode are metal electrode; The bottom of source electrode is contact electrode leads to client and source electrode exit simultaneously; The bottom contact polysilicon gate of grid; The bottom of drain electrode contacts drain terminal polysilicon field plate, transoid doping ring and drain region exit simultaneously.
3. a method of manufacturing the high-voltage LDMOS device described in claim 1, is characterized in that, comprises the steps:
The 1st step adopts photoetching process and ion implantation technology to form drift region on low-doped substrate, and the doping type of drift region is contrary with substrate;
The 2nd step adopts photoetching process and ion implantation technology to form tagma on low-doped substrate, and the doping type in tagma is identical with substrate;
The 3rd step adopts photoetching process and ion implantation technology to form drift region inversion layer on drift region, and the doping type of drift region inversion layer is contrary with drift region;
The 4th step, forms multiple isolation structures at silicon chip surface, and wherein isolation structure one is on the surface in tagma, and isolation structure two is on the surface of drift region and on the inversion layer of drift region, and isolation structure three, isolation structure four are all on the surface of drift region;
The 5th step, at silicon chip surface one deck gate oxide of first growing, then deposit one deck polysilicon, thereby this layer of polysilicon of etching and gate oxide form polysilicon gate and drain terminal polysilicon field plate;
One end of polysilicon gate is on tagma, and the other end is on isolation structure two;
Drain terminal polysilicon field plate is on isolation structure two;
The 6th step, carries out heavy doping ion injection formation source region exit and drain region exit in tagma and drift region, and the type of Implantation is identical with drift region;
Source region exit is among tagma and near one end of polysilicon gate;
Drain region exit is among drift region and between isolation structure three and isolation structure four;
The 7th step, carries out and source electrode, the contrary Implantation of doping type that drains, organizator electrode leads to client and the annular doping district around drain region exit in tagma and drift region;
Body electrode leads to client is among tagma and between isolation structure one and source region exit;
Annular doping district claims again transoid doping ring or special shaped doped ring, among drift region and round drain region exit, observes and presents annular from depression angle, is rendered as the structure of two sections of spaces from analysing and observe angle; Wherein a segment structure in annular doping district is between isolation structure two and isolation structure three, and drain region exit is between isolation structure three and isolation structure four;
The 8th step, first deposition of dielectric layer, then etches contact hole, and in contact hole, fills metal electrode, forms resulting devices; Metal electrode comprises source electrode, grid and drain electrode;
The bottom of source electrode is contact electrode leads to client and source electrode exit simultaneously;
The bottom contact polysilicon gate of grid;
The bottom of drain electrode contacts drain terminal polysilicon field plate, transoid doping ring and drain region exit simultaneously.
4. the method for manufacture high-voltage LDMOS device according to claim 3, is characterized in that, before described method the 3rd step is placed on the 2nd step, or before being placed on the 5th step;
Before described method the 3rd step is placed on the 5th step, in the 4th step, " isolation structure two is on the surface of drift region and on the inversion layer of drift region " changes " isolation structure two is on the surface of drift region " into, increases " drift region inversion layer is under isolation structure two " in the 3rd step after the 4th step.
5. a method of manufacturing the high-voltage LDMOS device described in claim 2, is characterized in that, comprises the steps:
The 1st step adopts photoetching process and ion implantation technology to form drift region on low-doped substrate, and the doping type of drift region is contrary with substrate;
The 2nd step adopts photoetching process and ion implantation technology to form tagma on low-doped substrate, and the doping type in tagma is identical with substrate;
The 3rd step adopts photoetching process and ion implantation technology to form drift region inversion layer on drift region, and the doping type of drift region inversion layer is contrary with drift region;
The 4th step, forms multiple isolation structures at silicon chip surface, and wherein isolation structure one is on the surface in tagma, and isolation structure two is the surperficial of drift region and on the inversion layer of drift region, isolation structure three is on the surface of drift region;
The 5th step, at silicon chip surface one deck gate oxide of first growing, then deposit one deck polysilicon, thereby this layer of polysilicon of etching and gate oxide form polysilicon gate and drain terminal polysilicon field plate;
One end of polysilicon gate is on tagma, and the other end is on isolation structure two;
Drain terminal polysilicon field plate is on isolation structure two;
The 6th step, carries out heavy doping ion injection formation source region exit and drain region exit in tagma and drift region, and the type of Implantation is identical with drift region;
Source region exit is among tagma and near one end of polysilicon gate;
Drain region exit is among drift region and between isolation structure two and isolation structure three;
The 7th step, carries out and source electrode, the contrary Implantation of doping type that drains, organizator electrode leads to client and the annular doping district around drain region exit in tagma and drift region;
Body electrode leads to client is among tagma and between isolation structure one and source region exit;
Annular doping district claims again transoid doping ring or special shaped doped ring, among drift region and round drain region exit, observe and present annular from depression angle, be rendered as the structure of two sections of spaces from analysing and observe angle, wherein a segment structure is between isolation structure two and drain region exit, and drain region exit is between annular doping district and isolation structure three;
The 8th step, first deposition of dielectric layer, then etches contact hole, and in contact hole, fills metal electrode, forms resulting devices; Metal electrode comprises source electrode, grid and drain electrode;
The bottom of source electrode is contact electrode leads to client and source electrode exit simultaneously;
The bottom contact polysilicon gate of grid;
The bottom of drain electrode contacts drain terminal polysilicon field plate, transoid doping ring and drain region exit simultaneously.
6. the method for manufacture high-voltage LDMOS device according to claim 5, is characterized in that, before described method the 3rd step is placed on the 2nd step, or before being placed on the 5th step;
Before described method the 3rd step is placed on the 5th step, in the 4th step, " isolation structure two is on the surface of drift region and on the inversion layer of drift region " changes " isolation structure two is on the surface of drift region " into, increases " drift region inversion layer is under isolation structure two " in the 3rd step after the 4th step.
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| CN103681791B (en) * | 2012-09-05 | 2016-12-21 | 上海华虹宏力半导体制造有限公司 | NLDMOS device and manufacture method |
| CN103681839A (en) * | 2012-09-10 | 2014-03-26 | 上海华虹宏力半导体制造有限公司 | NLDMOS (N-type laterally diffused metal oxide semiconductor) device and manufacture method |
| CN104465645B (en) * | 2013-09-24 | 2017-06-09 | 北大方正集团有限公司 | A kind of semiconductor switch chip and its manufacture method |
| CN104752423B (en) * | 2013-12-31 | 2018-08-21 | 中芯国际集成电路制造(上海)有限公司 | A kind of semiconductor devices and its manufacturing method and electronic device |
| CN104465653B (en) * | 2014-12-31 | 2017-06-06 | 上海华虹宏力半导体制造有限公司 | High-voltage electrostatic protection structure |
| TWI608546B (en) * | 2015-08-14 | 2017-12-11 | 立錡科技股份有限公司 | Lateral double diffused metal oxide semiconductor device and manufacturing method thereof |
| CN107301975B (en) * | 2016-04-14 | 2020-06-26 | 世界先进积体电路股份有限公司 | Semiconductor device and method for manufacturing the same |
| CN109768089B (en) * | 2019-01-23 | 2021-04-13 | 电子科技大学 | Voltage-controlled sampling device based on SenseFET |
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