CN102594369A - Quasi-cyclic low-density parity check code decoder based on FPGA (field-programmable gate array) and decoding method - Google Patents

Quasi-cyclic low-density parity check code decoder based on FPGA (field-programmable gate array) and decoding method Download PDF

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CN102594369A
CN102594369A CN2012100459009A CN201210045900A CN102594369A CN 102594369 A CN102594369 A CN 102594369A CN 2012100459009 A CN2012100459009 A CN 2012100459009A CN 201210045900 A CN201210045900 A CN 201210045900A CN 102594369 A CN102594369 A CN 102594369A
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external information
node
check
ram
frame
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CN102594369B (en
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白宝明
袁瑞佳
林伟
王珏
崔俊云
施玉晨
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Xidian University
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Abstract

The invention discloses a low-storage capacity high-speed QC-LDPC (quasi-cyclic low-density parity check) code decoder based on an FPGA (field-programmable gate array) and a decoding method, which are mainly used for solving the problem of low utilization efficiency of memory resources of a node update processing unit and an RAM (random access memory) of the decoder in the prior art. The decoder can simultaneously process two frames of decoding data, the decoder is used for setting an external information value of the first frame of data as all-zero and setting the second frame of data as a channel for receiving likelihood ratio information in the data initialization phase, so that a variable node processing unit and a check node processing unit can completely alternately process the two data frames in parallel in the whole decoding process, effectively shorten the work clock cycle required for processing the two frames of data and enable the decoding throughput to be about two times as that of a traditional design method. According to the decoder disclosed by the invention, a dynamic address access management method is adopted in external information access, and the parallel access of the two frames of decoding data can be realized in the single RAM; and compared with the existing decoder, the utilization efficiency of BRAM (broadcast recognition access method) resources is doubled in comparison with the existing decoders, and the decoder can be used for error correction in information transmission of a physical layer based on LDPC codes.

Description

Quasi-cyclic low-density check code decoder and interpretation method based on FPGA
Technical field
The invention belongs to communication technical field, relate to the channel error correction encoding decoder, particularly a kind of quasi-cyclic low-density check code decoder and interpretation method based on FPGA can be used for the physical layer information transmission error correction based on the LDPC sign indicating number.
Background technology
Tradition quasi-cyclic low-density verification QC-LDPC code decoder mainly is made up of variable node computing module VNU, check node calculation module CNU, check equations computing module PCU and some memory modules; Wherein memory module comprises three parts; Be channel initial information memory module RAM_F, iteration external information memory module RAM_M and decoding code word memory module RAM_C respectively, as shown in Figure 1.For the basic matrix block count is the QC-LDPC code decoder of m * n, and the VNU module comprises n concrete variable node computing unit VNU j, 1≤j≤n, the CNU module comprises m variable node computing unit CNU i, 1≤i≤m, the RAM_F module comprises n block RAM memory block F j, 1≤j≤n, the RAM_M module comprises m * n block RAM memory block M I, j, 1≤i≤m, 1≤j≤n.Every F jContain one and CNU iA read port that links to each other, every M I, jContain two reading-writing port, two equal and VNU of port jAnd CNU iLink to each other.External information and the channel information among the RAM_F among the RAM_M all use the static address way to manage, and the external information that promptly each node is corresponding and the read/write address of channel information are fixed value.If it is z * z that the submatrix of LDPC verification battle array divides block size, the concrete course of work of QC-LDPC code decoder iterative decoding is following: (1) initialization: the channel information sequence that receives is divided into n piecemeal stores n F among the RAM_F respectively into jIn the memory block, with the external information memory block M among the RAM_M I, j, 1≤i≤m, 1≤j≤n are initialized as complete zero, and initialization iterations iter is changed to 0 time; (2) variable node upgrades: each variable node computing unit VNU jThe M that sequential update is coupled I, jIn z external information, external information of every renewal, VNU jRespectively from F jAnd M I, jRead port in read a channel information and an external information, the judgement of the update calculation of carrying out variable node and this decoding code word writes M respectively with new external information and decoding code word I, jIn RAM_C.Reading, calculate and writing with pipeline system of each nodal information accomplished; (3) check-node upgrades: each check node calculation unit CNU iThe M that sequential update is coupled I, jIn z external information, external information CNU of every renewal iFrom the M that is attached thereto I, jRead port in read an external information, carry out after the update calculation of check-node new external information is returned into to M I, jIn.Reading, calculate and writing with pipeline system of each check-node information accomplished.Simultaneously, PCU takes out the decoding codeword information from RAM_C, code word and check matrix are multiplied each other, and produces the syndrome vector; (4) iterations iter is added up 1.If the syndrome that calculates vector is for complete zero, the decoding code word that expression judgement this time obtains is a legal-code, or iter reached maximum iteration time MAX_ITER, changes step (5) so over to
With decode results output, otherwise, turn back to the iterative computation that step (2) is proceeded next round; (5) the decoding code word in the RAM_C memory module is read as final decode results output.
In the visit of memory, VNU and CNU are a kind of access methods of switched to the read-write of RAM_M, and the access right of RAM_M is by the VNU module controls when VNU works, and the access right of RAM_M is then by the CNU module controls when CNU works.Memory M I, jIn reading and writing data adopt the static address way to manage, promptly the memory address of each extrinsic information data is a fixed value.Z extrinsic information data of the sub-piecemeal of each check matrix is stored in the M corresponding with it I, jIn, z is the dimension of syndrome matrix, i, j are respectively the capable piecemeal sequence number and the row piecemeal sequence number of syndrome matrix.VNU in step (2) jNeed column major order read-write M I, jIn z external information, the external information reference address that this submatrix first is listed as z row is fixed as 0～z, its initial reference address is 0 when reading and writing data, the read/write address of every next external information adds up 1; CNU in step (3) iRead and write M by the row order I, jIn z extrinsic information data, if the cycle offset of the capable j row of i syndrome matrix is α Ij, the reference address of the extrinsic information data that this submatrix x is capable so is (α Ij+ x) modz, initial reference address is α when reading and writing data Ij, every next read/write address is that a last address adds the value of 1 back to the z delivery, the read/write address sketch map of this static address way to manage is as shown in Figure 2.
Because the iterative decoding process of LDPC sign indicating number is the process that a variable node and check-node alternately transmit external information; VNU and CNU input and output each other; VNU and CNU have only a side simultaneously in work in the course of work of traditional ldpc code decoder; Most of treatment circuit in the decoder is in idle condition in half decoding time, therefore cause the utilization ratio of FPGA hardware resource lower, and Fig. 3 has provided both work schedules in iterative decoding process.
To the lower problem of traditional ldpc code decoder hardware resource utilization efficient, the decoder design method that the different external informations of computing unit alternate treatment two frames were deciphered, deciphered to a kind of two frame data simultaneously is suggested.The variable node computing unit VNU of decoder is connected two frame coding data simultaneously with check node calculation unit CNU; RAM_F1 and RAM_F2 store the channel information of two Frames respectively; RAM_M1 and RAM_M2 store the external information of two Frames respectively; RAM_C1 and RAM_C2 then store the judgement code word of two Frames respectively; Its decode procedure is following: (1) initialization: two frame channel information sequences are stored into respectively among RAM_F1 and the RAM_F2, the external information among RAM_M1 and the RAM_M2 is initialized as complete zero, the iterative processing number of times of two Frames is made as 0 time; The variable node of (2) first frames upgrades: at first the VNU processing unit is accomplished the variable node renewal of first frame data, and this moment, the CNU processing unit was temporarily idle; The variable node of the check-node of (3) first frames and second frame is parallel to be upgraded: the check-node that the CNU processing unit is accomplished first frame data upgrades, and while VNU processing unit jumps to the variable node of accomplishing second frame data on second frame and upgrades; (4) exchange two frame data are handled: if in last round of renewal, CNU upgrades first frame data, and VNU upgrades second frame data, and then CNU forwards the renewal of accomplishing check-node on second frame to, and VNU forwards the renewal of accomplishing variable node on first frame to; Otherwise the check-node that CNU accomplishes first frame data upgrades, and the variable node that VNU accomplishes second frame data upgrades; (5) complete zero if the syndrome vector of two frames is, or reached maximum iteration time, then change step (6) over to decode results output, otherwise, change the exchange iterative processing that step (4) is proceeded two frame data over to; (6) the decoding code word of RAM_C1 and RAM_C2 two memory modules is read as final decode results output.
It is as shown in Figure 4 that the VPU of this improved two frame parallel decoding methods and CPU upgrade sequential.Because VPU two Frames different with the CPU alternate treatment; The decoder throughput that this method design obtains is near the twice of traditional design method; But because each ram port can only be read and write the data on the address among the FPGA at every turn; Adopt traditional static address management method, reading with writing of each external information need take two different ports, and the port number of every block RAM resource is 2 at most; Therefore two frame data of decoder must be stored in respectively in the two different block RAMs, and the RAM resource requirement quantity of this decoder is the twice of conventional method.In addition, because decoder has only VNU in running order in the decoding incipient stage, there is idle time slot in CNU, and this method is not accomplished the complete concurrent working of VNU and CNU two processing units.
Summary of the invention
The objective of the invention is to deficiency to above-mentioned prior art; A kind of quasi-cyclic low-density check code decoder and interpretation method based on FPGA is provided; To reduce the quantity that takies of FPGA storage resources; Improve logical resource and RAM efficiency of resource in the decoder, and improve the decoding throughput of decoder.
For realizing above-mentioned purpose, check code decoder of the present invention comprises:
Variable node computing module VNU is used for the variable node external information update calculation to decoding, wherein comprises n variable node computing unit VNU j, 1≤j≤n, n are the row piecemeal quantity of basic matrix;
Check node calculation module CNU is used for the check-node external information update calculation to decoding, wherein comprises m check node calculation unit CNU i, 1≤i≤m, m are the capable piecemeal quantity of basic matrix;
Check equations computing module PCU, whether be used for the verification decode results is legal-code;
Channel initial information memory module RAM_F is used to store the channel likelihood ratio information of reception, wherein comprises n block RAM memory block F j, 1≤j≤n;
Iteration external information memory module RAM_M is used for storing the iteration external information that iterative decoding process variable node and check-node transmit each other, wherein comprises m * n block RAM memory block M I, j, 1≤i≤m, 1≤j≤n;
Decoding code word memory module RAM_C is used to store the code word result that decoding obtains;
It is characterized in that:
Every block RAM in said RAM_F, three modules of RAM_M and RAM_C is all stored two different frame coding data;
Said every memory block F jIn contain two read ports, these two read ports all with check node calculation unit CNU iLink to each other, be responsible for reading of the different channel initial information of two frames respectively;
Said every memory block M I, jIn contain two reading-writing port, its read-write mode is " a write-after-read pattern ", each reading-writing port all with variable node computing unit VNU jWith check node calculation unit CNU iLink to each other, each is responsible for the read-write of a frame iteration external information each port.
For realizing above-mentioned purpose, check code decoding method of the present invention comprises the steps:
1) initialization: the two frame channel likelihood ratio information that will receive deposit each memory block F of channel initial information memory module RAM_F in according to the row piecemeal segmentation of check matrix H iIn, the address realm of two frame data is respectively 0～z-1 and z～2z-1, and z is the dimension of syndrome matrix; The first frame external information among the iteration external information memory module RAM_M is initialized as complete zero, the second frame external information is initialized as channel and receives likelihood ratio information; Iterations iter is initialized as 0 time;
2) variable node of first frame data and the check-node of second frame data are upgraded:
2a) each variable node computing unit VNU in the variable node computing module jUpgrade the M that is attached thereto one by one with listed sequence I, jIn z external information, wherein VNU of first frame jFor carrying out the variable node computing unit of j row variable node update calculation, M among the VNU I, jMemory block for the capable j row of storage i syndrome matrix external information among the RAM_M;
2b) each check node calculation unit CNU in the check node calculation module iUpgrade the M that is attached thereto one by one with the row order I, jIn z external information, wherein CNU of second frame iFor carrying out the check node calculation unit of the capable check-node update calculation of i, M among the CNU I, jMemory block for the capable j row of storage i syndrome matrix external information among the RAM_M;
3) check-node of first frame data and the variable node of second frame data are upgraded:
3a) each check node calculation unit CNU in the check node calculation module iUpgrade the M that is attached thereto one by one with the row order I, jIn z external information of first frame;
3b) each variable node computing unit VNU in the variable node computing module jUpgrade the M that is attached thereto one by one with listed sequence I, jIn z external information of second frame;
4) iterations iter is added 1, calculate the first frame coding result's syndrome vector s 1Syndrome vector s with the second frame coding result 2, if s 1=s 2=0 or iter equal maximum iteration time MAX_ITER, execution in step 5), otherwise forward step 2 to) proceed iterative decoding and calculate;
5) from decoding code word memory module RAM_C, reading two frame coding court verdicts respectively exports as decode results.
The present invention is owing to be changed to complete 0 in data initialization stage of decoder with the external information value of first frame data; The external information value of second frame data is made as channel reception likelihood ratio information; The code check node processing unit just can be walked abreast with the variable node processing unit in the incipient stage of decode procedure carry out the iteration update processing of two frame coding data; Effectively shortened and handled the required work clock cycle of two decoding data frames, thereby improved the decoding throughput of whole decoder; Simultaneously because the present invention has adopted dynamic accessed management method in the visit of external information; Make variable node processing unit and code check node processing unit only need a ram port just can accomplish the read-write of a frame extrinsic information data; Thereby can in monolithic RAM, realize the storage and the visit of two frame coding data simultaneously; With compared with traditional design methods, the BRAM resource utilization of decoder can double.
Realization is the result show, the present invention can be under the constant basically situation of the FPGA hardware resource quantity that the QC-LDPC code decoder uses, and total decoding throughput of conventional decoder is improved nearly one times.
Description of drawings
Fig. 1 is traditional ldpc code decoder structural representation;
Fig. 2 is the read/write address sketch map of existing static address way to manage;
Fig. 3 is the iteration working timing figure of VNU and CNU in the conventional decoder;
Fig. 4 is that the VPU and the CPU of existing improved two frame parallel decodings upgrades sequential chart;
Fig. 5 is a low memory space high speed decoder structure chart provided by the invention;
Fig. 6 is the flow chart of low memory space high speed decoding method provided by the invention;
Fig. 7 is the external information dynamic address visit sketch map in the interpretation method of the present invention;
Fig. 8 is a decoding performance analogous diagram of the present invention.
Embodiment
With reference to Fig. 5; Low memory space high speed decoder structure provided by the invention mainly comprises 6 parts, is respectively variable node computing module VNU, check node calculation module CNU, check equations computing module PCU, channel initial information memory block RAM_F, iteration external information memory block RAM_M and decoding code word memory block RAM_C.Wherein, variable node computing module VNU is used to accomplish the variable node external information update calculation of decoding, and it comprises n variable node computing unit VNU j, 1≤j≤n, n are the row piecemeal quantity of basic matrix; Check node calculation module CNU is used to accomplish the check-node external information update calculation of decoding, and it comprises m check node calculation unit CNU i, 1≤i≤m, m are the capable piecemeal quantity of basic matrix; Check equations computing module PCU, whether be used for the verification decode results is legal-code; Channel initial information memory module RAM_F is used to store the channel likelihood ratio information of reception, and it comprises n block RAM memory block F j, 1≤j≤n; Iteration external information memory module RAM_M is used for storing the iteration external information that iterative decoding process variable node and check-node transmit each other, and it comprises m * n block RAM memory block M I, j, 1≤i≤m, 1≤j≤n; Decoding code word memory module RAM_C is used to store the code word result that decoding obtains.Wherein, all have the decoding data of different two frames in each the RAM memory block among RAM_F, RAM_M and the RAM_C, they are respectively: the decoding data of storing among the RAM_F is that two different frame channels receive likelihood ratio; The decoding data of storing among the RAM_C is two different frame coding court verdicts; The two frame coding data of storing among the RAM_M are the external information initial value; The initial external information of this first frame data storage is the check-node external information; Its value is for complete 0, and the initial external information of this second frame data storage is the variable node external information, and its value is the likelihood ratio of channel reception.
The annexation of each module is following in the decoder:
Every memory block F among the RAM_F jIn contain two read ports, these two read ports all with check node calculation unit CNU iLink to each other, be responsible for reading of the different channel initial information of two frames respectively; Every memory block M among the RAM_M I, jIn contain two reading-writing port, its read-write mode is " a write-after-read pattern ", each reading-writing port all with variable node computing unit VNU jWith check node calculation unit CNU iLink to each other, each is responsible for reading and writing of a frame iteration external information each port.The write port of RAM_C links to each other with PCU with VNU respectively with read port, and VNU will adjudicate code word from write port and deposit in the RAM_C, PCU then from read port will adjudicate code word read the check its whether be legal-code.
With reference to Fig. 6, low memory space high speed decoding method provided by the invention, its step is following:
Step 1, initialization: the two frame channel likelihood ratio information that will receive deposit each memory block F of channel initial information memory module RAM_F in according to the row piecemeal segmentation of check matrix H jIn, the address realm of two frame data is respectively 0～z-1 and z～2z-1, F jBe the memory block of storage j row syndrome matrix channel initial information among the RAM_M, z is the dimension of syndrome matrix; The first frame external information among the iteration external information memory module RAM_M is initialized as complete zero, the second frame external information is initialized as channel and receives likelihood ratio information; Iterations iter is initialized as 0 time;
Step 2, the variable node of first frame data and the check-node of second frame data are upgraded:
Each variable node computing unit VNU in the variable node computing module jUpgrade the M that is attached thereto one by one with listed sequence I, jIn z external information of first frame; Simultaneously, each check node calculation unit CNU in the check node calculation module iUpgrade the M that is attached thereto one by one with the row order I, jIn z external information, wherein VNU of second frame jFor carrying out the variable node computing unit of j row variable node update calculation, CNU among the VNU iFor carrying out the check node calculation unit of the capable check-node update calculation of i, M among the CNU I, jMemory block for the capable j row of storage i syndrome matrix external information among the RAM_M;
Said variable node computing unit VNU jRenewal to each external information is divided into three steps: VNU jEarlier respectively from M I, jAnd F jIn read required external information of update calculation and channel likelihood ratio information; VNU jCarry out the update calculation of variable node according to the external information and the channel likelihood ratio information of reading again, and accomplish the decoding bit decision of this node; VNU jThe extrinsic information data that at last update calculation is obtained writes M respectively with the decoding decision bits I, jIn decoding code word memory module RAM_C.
Said check node calculation unit CNU iRenewal to each external information also is divided into three steps: CNU iEarlier from M I, jIn read the required external information of update calculation; CNU iCarry out the update calculation of variable node again according to the external information of reading; CNU iThe external information that at last update calculation is obtained is written back to M I, jIn;
Said variable node computing unit VNU jWith check node calculation unit CNU iTo the renewal of each external information, need be to M I, jIn extrinsic information data read and write, M wherein I, jIn the read-write of extrinsic information data adopt a kind of dynamic accessed management method, whenever carry out the renewal of an external information, the external information memory address of each variable node and check-node will change, its address distribution method is following:
A) with M I, jIn z external information initial storage address of first frame data be made as 0～z-1 respectively, z external information initial storage address of second frame data is made as z～2z-1 respectively, z is the dimension of syndrome matrix;
B) after each variable node external information update calculation finishes, the memory address of this extrinsic information data will be d if it reads the address from new distribution v, it writes the address will be set as (d v+ L v) modz, L vBe that VNU carries out the streamline computational length that variable node upgrades to an extrinsic information data;
C) after each check-node external information update calculation finishes, the memory address of this extrinsic information data will be d if it reads the address from new distribution h, it writes the address will be set as (d h+ L h) modz, L hBe that CNU carries out the streamline computational length that check-node upgrades to an extrinsic information data.
For example, to a variable node of first frame,, and (l+2L is arranged if the initial storage address of its external information is l v+ L h) modz＜z, the accessed process that its external information iteration is upgraded is following: variable node upgrades for the first time, and the address of reading and write of this external information is respectively l and l+L vCheck-node upgrades for the first time, and the address of reading and write of this external information is respectively l+L vAnd l+L v+ L h, variable node upgrades for the second time, and the address of reading and write of this external information is respectively l+L v+ L hAnd l+2L v+ L h, after, each check-node upgrades writes the address and reads the address for it and add L hThe back is to the result of z delivery, and each variable node upgrades writes the address and read the address for it and add L vThe back is to the result of z delivery, and is as shown in Figure 7.
This address distribution method makes that the address of the node external information that current needs are read is identical with the address of upgrading the node external information that need write of finishing; Read-write mode through reading-writing port is set to " write-after-read pattern ", can on single reading-writing port, accomplish reading and writing of two variable node external informations or two check-node external informations simultaneously.
Step 3, the check-node of first frame data and the variable node of second frame data are upgraded:
Each check node calculation unit CNU in the check node calculation module iUpgrade the M that is attached thereto one by one with the row order I, jIn z external information of first frame, each variable node computing unit VNU in the variable node computing module simultaneously jUpgrade the M that is attached thereto one by one with listed sequence I, jIn z external information of second frame;
Step 4, iter adds 1 with iterations, calculates the first frame coding result's syndrome vector s 1Syndrome vector s with the second frame coding result 2, if s 1=s 2=0 or iter equal maximum iteration time MAX_ITER, execution in step 5 is proceeded iterative decoding and is calculated otherwise forward step 2 to;
Step 5 is read two frame coding court verdicts respectively and is exported as decode results from decoding code word memory module RAM_C.
Decoder effect of the present invention can further specify with the realization result through following theory analysis:
1. the two frame start node extrinsic information data of storing in the iteration external information memory module of the present invention are respectively variable node external information and check-node external information; Make variable node processing unit and code check node processing unit alternate treatment two Frames that in whole decode procedure, can walk abreast fully; Under the identical situation of decoder work clock; The throughput of its decoding is the twice of conventional decoder, and is higher than the decoding throughput of improved two frame parallel decoders.The present invention has adopted dynamic accessed management method in the visit of external information; Can in monolithic RAM, realize the storage and the visit of two frame coding data simultaneously; Compare with improved two frame parallel decoders, the required BRAM resource of decoder can reduce half the.
2. decoder of the present invention and interpretation method realize on the XC4VLX80FPGA of Xilinx company.This decoder is 5/6 based on code check, and code length is 2304 QC-LDPC sign indicating number, and decoding algorithm is the normalization minimum-sum algorithm, and Fig. 8 is the decoding performance of this QC-LDPC sign indicating number under awgn channel, BPSK modulation condition.
Traditional decoder, improved two frame parallel decoders and the realization result data of low memory space high speed decoder of the present invention on the ISE10.1 platform are as shown in the table.
Realization result statistics on the table 1Xilinx FPGAXC4VLX80
Figure BDA0000138732570000091
Visible from table 1; The decoding throughput of low memory space high speed decoder of the present invention is 190Mbps; Twice near the conventional decoder throughput; The throughput of more improved two frame parallel decoders is slightly high, and decoder for decoding throughput of the present invention does not reach the twice of conventional decoder fully, is because the operation clock frequency of this decoder is lower slightly than conventional decoder.On the usage quantity of hardware resource; The required Slice resource of decoder of the present invention is omited high than conventional decoder; Suitable basically with improved two frame parallel decoders; The required RAM resource of decoder of the present invention is identical with conventional decoder, half the for the RAM resource of improved two frame parallel decoders.
The present invention not detailed description is the known technology of this area.

Claims (9)

1. low memory space high speed QC-LDPC code decoder based on FPGA comprises:
Variable node computing module VNU is used for the variable node external information update calculation to decoding, wherein comprises n variable node computing unit VNU j, 1≤j≤n, n are the row piecemeal quantity of basic matrix;
Check node calculation module CNU is used for the check-node external information update calculation to decoding, wherein comprises m check node calculation unit CNU i, 1≤i≤m, m are the capable piecemeal quantity of basic matrix;
Check equations computing module PCU, whether be used for the verification decode results is legal-code;
Channel initial information memory module RAM_F is used to store the channel likelihood ratio information of reception, wherein comprises n block RAM memory block F j, 1≤j≤n;
Iteration external information memory module RAM_M is used for storing the iteration external information that iterative decoding process variable node and check-node transmit each other, wherein comprises m * n block RAM memory block M I, j, 1≤i≤m, 1≤j≤n;
Decoding code word memory module RAM_C is used to store the code word result that decoding obtains;
It is characterized in that:
Every block RAM in said RAM_F, three modules of RAM_M and RAM_C is all stored two different frame coding data;
Said every memory block F jIn contain two read ports, these two read ports all with check node calculation unit CNU iLink to each other, be responsible for reading of the different channel initial information of two frames respectively;
Said every memory block M I, jIn contain two reading-writing port, its read-write mode is " a write-after-read pattern ", each reading-writing port all with variable node computing unit VNU jWith check node calculation unit CNU iLink to each other, each is responsible for the read-write of a frame iteration external information each port.
2. decoder according to claim 1; It is characterized in that; The two frame coding data of storing among the iteration external information memory module RAM_M are the external information initial value, and wherein the initial external information of first frame data storage is the check-node external information, and its value is for complete 0; The initial external information of second frame data storage is the variable node external information, the likelihood ratio that its value receives for channel.
3. decoder according to claim 1 is characterized in that, the decoding data of storing among the channel initial information memory module RAM_F is that two different frame channels receive likelihood ratio.
4. decoder according to claim 1 is characterized in that, the decoding data of storing among the decoding code word memory module RAM_C is two different frame coding court verdicts.
5. the low memory space high speed QC-LDPC code coding method based on FPGA comprises the steps:
1) initialization: the two frame channel likelihood ratio information that will receive deposit each memory block F of channel initial information memory module RAM_F in according to the row piecemeal segmentation of check matrix H jIn, the address realm of two frame data is respectively 0～z-1 and z～2z-1, F jBe the memory block of storage j row syndrome matrix channel initial information among the RAM_M, z is the dimension of syndrome matrix; The first frame external information among the iteration external information memory module RAM_M is initialized as complete zero, the second frame external information is initialized as channel and receives likelihood ratio information; Iterations iter is initialized as 0 time;
2) variable node of first frame data and the check-node of second frame data are upgraded:
2a) each variable node computing unit VNU in the variable node computing module jUpgrade the M that is attached thereto one by one with listed sequence I, jIn z external information, wherein VNU of first frame jFor carrying out the variable node computing unit of j row variable node update calculation, M among the VNU I, jMemory block for the capable j row of storage i syndrome matrix external information among the RAM_M;
2b) each check node calculation unit CNU in the check node calculation module iUpgrade the M that is attached thereto one by one with the row order I, jIn z external information, wherein CNU of second frame iFor carrying out the check node calculation unit of the capable check-node update calculation of i, M among the CNU I, jMemory block for the capable j row of storage i syndrome matrix external information among the RAM_M;
3) check-node of first frame data and the variable node of second frame data are upgraded:
3a) each check node calculation unit CNU in the check node calculation module iUpgrade the M that is attached thereto one by one with the row order I, jIn z external information of first frame;
3b) each variable node computing unit VNU in the variable node computing module jUpgrade the M that is attached thereto one by one with listed sequence I, jIn z external information of second frame;
4) iterations iter is added 1, calculate the first frame coding result's syndrome vector s 1Syndrome vector s with the second frame coding result 2, if s 1=s 2=0 or iter equal maximum iteration time MAX_ITER, execution in step 5), otherwise forward step 2 to) proceed iterative decoding and calculate;
5) from decoding code word memory module RAM_C, reading two frame coding court verdicts respectively exports as decode results.
6. interpretation method according to claim 5, wherein step 2a) each variable node computing unit VNU in the described variable node computing module jUpgrade the M that is attached thereto one by one with listed sequence I, jIn z external information of first frame, carry out as follows:
At first, by VNU jRespectively from M I, jAnd F jIn read required external information of update calculation and channel likelihood ratio information; M I, jIn z external information initial storage address of first frame data be respectively 0～z-1, each external information is upgraded its memory address of back that finishes and will be changed;
Once more, by VNU jCarry out the update calculation of variable node according to external information of reading and channel likelihood ratio information, and accomplish the decoding bit decision of this node;
At last, by VNU jThe extrinsic information data that update calculation is obtained writes M respectively with the decoding decision bits I, jIn decoding code word memory module RAM_C, if the external information of this variable node is at M I, jIn the address of reading be d v, then will write address setting and be (d v+ L v) modz, L vBe VNU jAn extrinsic information data is carried out the streamline length of variable node update calculation, and symbol mod represents modulo operation.
7. interpretation method according to claim 5, wherein step 2b) each check node calculation unit CNU in the described check node calculation module iUpgrade the M that is attached thereto one by one with the row order I, jIn z external information of second frame, carry out as follows:
At first, by CNU iFrom M I, jIn read the required external information of update calculation; The z of second frame data external information initial storage address is respectively z～2z-1, and each external information is upgraded its memory address of back that finishes and will be changed;
Once more, by CNU iCarry out the update calculation of variable node according to the external information of reading;
At last, by CNU iThe external information that update calculation is obtained is written back to M I, jIn; If the address of reading of check-node external information is d h, then will write address setting and be (d h+ L h) modz, L hBe CNU carries out the check-node update calculation to an extrinsic information data streamline length.
8. interpretation method according to claim 5, wherein step 3a) each check node calculation unit CNU in the described check node calculation module iUpgrade the M that is attached thereto one by one with the row order I, jIn z external information of first frame, carry out as follows:
At first, by CNU iFrom M I, jIn read the required external information of update calculation;
Once more, by CNU iCarry out the update calculation of variable node according to the external information of reading;
At last, by CNU iThe external information that update calculation is obtained is written back to M I, jIn; If the address of reading of check-node external information is d h, then will write address setting and be (d h+ L h) modz, L hBe CNU carries out the check-node update calculation to an extrinsic information data streamline length.
9. interpretation method according to claim 5, wherein step 3b) each variable node computing unit VNU in the described variable node computing module jUpgrade the M that is attached thereto one by one with listed sequence I, jIn z external information of second frame, carry out as follows:
At first, by VNU jRespectively from M I, jAnd F jIn read required external information of update calculation and channel likelihood ratio information;
Once more, by VNU jCarry out the update calculation of variable node according to external information of reading and channel likelihood ratio information, and accomplish the decoding bit decision of this node;
At last, by VNU jThe extrinsic information data that update calculation is obtained writes M respectively with the decoding decision bits I, jIn RAM_C, if the external information of this variable node is at M I, jIn the address of reading be d v, then will write address setting and be (d v+ L v) modz, L vBe VNU carries out the variable node update calculation to an extrinsic information data streamline length.
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