CN102592064A - Dynamic crypto chip - Google Patents
Dynamic crypto chip Download PDFInfo
- Publication number
- CN102592064A CN102592064A CN2011100031415A CN201110003141A CN102592064A CN 102592064 A CN102592064 A CN 102592064A CN 2011100031415 A CN2011100031415 A CN 2011100031415A CN 201110003141 A CN201110003141 A CN 201110003141A CN 102592064 A CN102592064 A CN 102592064A
- Authority
- CN
- China
- Prior art keywords
- chip
- dynamic password
- real
- cryptographic algorithm
- microprocessor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Images
Landscapes
- Storage Device Security (AREA)
Abstract
The invention discloses a dynamic crypto chip, which comprises a microprocessor, a cryptographic algorithm accelerating engine, an on-chip memory and a real-time clock module, wherein a preset secret key is stored in the on-chip memory. The microprocessor, the cryptographic algorithm accelerating engine, the on-chip memory and the real-time clock module are connected with one another through an on-chip bus. The microprocessor is used for coordinating work of each unit, and the cryptographic algorithm accelerating engine is used for finishing crypto-operation according to the preset secret key in the on-chip memory and real-time time of the real-time clock module. The dynamic crypto chip is high in performance and safety.
Description
Technical field
The present invention relates to the cryptosecurity field, specifically, relate to a kind of dynamic password chip.
Background technology
The electronic commerce network infosystem is being played a greater and greater role at aspects such as finance, commerce, telecommunications, culture and education, and society strengthens the dependence of network information system day by day, and computer network has become the important assurance of social development.The great advantage of computer network is its opening, yet, to bring greatly easily simultaneously to people's life, this opening has also proposed great challenge to the safeguard protection of information on the network.Identity, protection information security how to identify a people exactly are the critical social concerns that current informationized society must solve as early as possible.
Authentication is used to solve visitor's the physical identity and the consistency problem of digital identity, the foundation of rights management is provided for other safety techniques.In early days, a kind of common mode of authentication is to verify through static password, but because static password is general long-time constant, these characteristics have increased its possibility that is cracked.Along with the development of Ciphor safety technology, dynamic password has appearred at present, and this dynamic password can produce a new disposal password automatically, thereby improve security performance when accessing to your password activities such as carrying out authentication at every turn.
Yet existing dynamic password product generally based on comparatively general cryptographic algorithm, adopts 8 or 16 chip microcontroller, defectives such as ubiquity arithmetic capability deficiency, poor safety performance, and its security and aspect of performance still have much room for improvement.
Summary of the invention
In view of this, the invention provides the dynamic password chip of a kind of high-performance, high security.
For solving the problems of the technologies described above, the present invention has adopted following technical scheme:
A kind of dynamic password chip; Comprise microprocessor, cryptographic algorithm accelerating engine, store on-chip memory and the real-time clock module of presetting key, said microprocessor, cryptographic algorithm accelerating engine, on-chip memory and real-time clock module interconnect through on-chip bus; Said microprocessor is used to coordinate the work of each unit, and said cryptographic algorithm accelerating engine is used for accomplishing crypto-operation according to the real-time time of the preset key of said on-chip memory and real-time clock module.
In an embodiment of the present invention; Said cryptographic algorithm accelerating engine comprises the arithmetic logical operation special circuit; Store the algorithm configuration microcode of said cryptographic algorithm accelerating engine in the said on-chip memory, said arithmetic logical operation special circuit is used under said algorithm configuration microcode guiding, accomplishing arithmetic logical operation.
In an embodiment of the present invention; Said arithmetic logical operation special circuit is 32 arithmetic logical operation special circuits, and said 32 arithmetic logical operations comprise that 32 logical ands, 32 logical ORs, 32 logic XORs, 32 logical inverse, 32 logical shift lefts, 32 bit data additions and 32 bit data move.
In an embodiment of the present invention, said on-chip memory comprises the Flash that is with read-write protection, and said configuration microcode is stored among the Flash of said band read-write protection.
In an embodiment of the present invention, said real-time clock module comprises that the corrected value according to configuration carries out the correcting register that timing is proofreaied and correct automatically.
In an embodiment of the present invention, chip can be configured to the dormancy mode of operation of low-power consumption according to application need under idle condition.
In an embodiment of the present invention, said chip also comprises voltage and temperature-measuring module.
In an embodiment of the present invention, said chip also comprises the LCD driver module, and said LCD driver module is provided with SEG mouth that is exclusively used in second point of scintillation and the SEG mouth that is exclusively used in the progress bar demonstration.
In an embodiment of the present invention, said chip is provided with the hardware watchdog module.
In an embodiment of the present invention, said chip also comprises communications component, the JTAG mouth that said communications component comprises the real-time debug that is used for microprocessor be used for key and write the serial ports with data communication.
The invention has the beneficial effects as follows:, can realize the dynamic password computing of high-performance, high security through the cryptographic algorithm accelerating engine is set.
Description of drawings
Fig. 1 is the logic diagram of the dynamic password chip of the embodiment of the invention;
Fig. 2 is the logic diagram that the MCU of the dynamic password chip of the embodiment of the invention examines;
Fig. 3 is the logic diagram of cryptographic algorithm accelerating engine of the dynamic password chip of the embodiment of the invention
Fig. 4 is the logic diagram of crypto-operation special circuit of the cryptographic algorithm accelerating engine of the embodiment of the invention;
Fig. 5 is the system construction drawing of the power management of the embodiment of the invention;
Fig. 6 is the schematic diagram of the WDT of the embodiment of the invention;
Fig. 7 is the chip initiation flow process of the embodiment of the invention;
Fig. 8 is the chip operation flow process of the embodiment of the invention;
Fig. 9 is the work slice arrangement of the embodiment of the invention.
Embodiment
Combine accompanying drawing that the present invention is done further explain through embodiment below.
As shown in Figure 1, the dynamic password chip of the embodiment of the invention mainly comprises microprocessor, cryptographic algorithm accelerating engine, on-chip memory (storage unit), RTC (Real-Time Clock, real-time clock module), and each several part links to each other through on-chip bus.Respectively each module is described below.
Microprocessor mainly comprises microprocessor core (MCU nuclear), program storage area and data storage area.It is optimized through the machine cycle sequential to microprocessor on the basis of original instruction set based on 8052 instruction set, makes that accomplishing an instruction cycle only needs four clock period, has improved the performance of microprocessor greatly.Microprocessor is responsible for coordinating each cell operation in the sheet, accomplishes functions such as RTC correction, is the core of entire chip.
As shown in Figure 2, MCU nuclear comprises control module, arithmetic logical unit, Bus Interface Unit, command decoder and register file.Control module links to each other with arithmetic logical unit, Bus Interface Unit, command decoder and register file respectively, respectively arithmetic logical unit, Bus Interface Unit, command decoder and register file are controlled.Arithmetic logical unit, Bus Interface Unit, command decoder then provide functions such as arithmetic logical operation, EBI, instruction decode respectively; Register file then comprises multiple register, for example SFR (Special Function Register, special function register).
Comprise with the on-chip memory of MCU caryogamy cover: 32k byte Fla sh program storage, the internal data memory of 256 bytes, the external data memory of 1024 bytes.Wherein, the Flash program storage is mapped to program storage area.The peripheral hardware register mappings of external data memory and MCU nuclear is to the data storage area.The special function register of internal data memory and MCU nuclear is mapped to same address space.
The Flash storer of the 32K byte that on-chip memory comprised is divided into two: geocoding has read-write protection mechanism at the storage space of 0～24K; Be used to deposit the configuration microcode of cryptographic algorithm accelerating engine; In case the read-write protection position is effective; Just can't outside sheet, visit this storage space, also can't change the data of this storage space the inside, the unique way that changes the read-write protection state is all to wipe the total data of this storage space and read-write protection position; Geocoding is used for depositing user program at the storage space of 24K～32K, can random access, rewriting.
The MCU nuclear of the embodiment of the invention is 8 embedded microprocessor nuclears, and it is the operation platform of application software, be responsible for deal with data and control other functional part and bus on the sheet, and be the core of entire chip.Through adopting the instruction set compatible with 8052 single-chip microcomputers; And the machine cycle sequential to microprocessor is optimized on the basis of original instruction set; Simplified SOC (System on Chip to a great extent; SOC(system on a chip), or system level chip) chip design, promoted chip performance, reduced the power consumption of system and reduced area of chip and cost.
Be to improve the security of microprocessor, microprocessor core has also increased the read-write protection control module of storer, and is provided with sensitive data district mechanism such as automatic clear when illegally being read.
The dynamic password chip of the embodiment of the invention, to the characteristics of crypto-operation integrated the cryptographic algorithm accelerating engine.The logic diagram of cryptographic algorithm accelerating engine is as shown in Figure 3; It is the core component of crypto-operation; It is a special circuit with 32 crypto-operation abilities; Can in a clock period, accomplish 32 common arithmetic logical operations in crypto-operation, comprise that 32 logical ands, 32 logical ORs, 32 logic XORs, 32 logical inverse, 32 logical shift lefts, 32 bit data additions, 32 bit data operation such as move.32 crypto-operation special circuits of crypto-operation needs configuration according to reality can make cryptographic algorithm hardwareization.The configuration microcode of control crypto-operation special circuit then is solidificated in the preceding 24K space that program storage area is Flash, and uses Flash read-write protection position to realize the function that this program segment is carried out read-write protection.In a single day Flash read-write protection position writes, and just can't outside sheet, visit this storage space, also can't change the data of this storage space the inside, and the unique way that changes the read-write protection state is all to wipe the total data of this storage space and read-write protection position.The configuration code of cryptographic algorithm accelerating engine and corresponding read-write protection can just be provided with when chip dispatches from the factory, thereby guarantee the security of this chip in operational phase, have satisfied the demand of crypto-operation to the algorithm routine security.
The user key conservation zone is arranged in SRAM, and the cryptographic algorithm accelerating engine can directly be visited, and the ephemeral data that accelerating engine produces when computing also is kept among the SRAM.When chip got into user program and upgrades, these two parts data can be by the hardware automatic clear, and these two parts data also can Lock-out during the battery power down.This mechanism can prevent the possibility that key is stolen after inserting with user program, satisfied the demand of crypto-operation to cipher safety.
The structure that the computing special circuit that accesses to your password adds microcode control had both had dirigibility, had protected algorithm itself again.Simultaneously, as previously mentioned, the ephemeral data that produces in key that crypto-operation is required and the calculating process is kept at also has strict protection mechanism among the SRAM.This cryptographic algorithm accelerating engine can carry out different initialization according to demand, to support the different kind of cipher algorithm, comprises comparatively general MD5 and SHA-1 algorithm at present, and " the SM3 cryptographic hash algorithm " of national Password Management office or the like.Wherein, MD5 and SHA-1 algorithm are the cryptographic hash algorithms that belongs to the maturation of RSA company, and SM3 then is the cryptographic hash algorithm of China's independent development.The principal character of cryptographic hash algorithm is that ciphering process is irreversible; Can't be deciphered through ciphered data, have only the identical clear data (promptly aforementioned " key " adds the combination of real-time time) of input just can obtain identical ciphertext through identical cryptographic hash algorithm.
The design of cryptographic algorithm accelerating engine is the problem of a software-hardware synergism design, and its design object mainly is high security and high-performance.
Consider from safety perspective; The cryptographic algorithm accelerating engine of the embodiment of the invention, through with main calculation function hardwareization, remaining uses microcode to realize; And be kept at and be difficult for being reversed in the Flash memory block that has the read-write protection function that obtains, thereby the security of boosting algorithm itself; Simultaneously, the configurability of microcode has strengthened the dirigibility that algorithm is realized again, through the different microcode configuration information of one-time write, chip can be set when dispatching from the factory realize specific algorithm, satisfies different clients' demand.
From the chip performance angle, because the cryptographic hash algorithm will carry out a large amount of 32 arithmetic logical operations and shifting function, and 8 MCU can't satisfy the requirement on time and the power consumption.The cryptographic algorithm special circuit that has 32 bit arithmetic abilities through use is accomplished cryptographic calculation, and disposes this special circuit with microcode, thereby has realized the computing to the cryptographic hash algorithm.
The crypto-operation special circuit is the cryptographic algorithm accelerating engine; It mainly is used for accomplishing to the characteristic of the close algorithm of SM3 state analyzes the atomic operation with reusability (32 bit arithmetic) that extracts afterwards; These atomic operations comprise that 32 logical ands, 32 logical ORs, 32 logic XORs, 32 logical inverse, 32 logical shift lefts, 32 bit data additions, 32 bit data move etc., and the cryptographic algorithm accelerating engine is accomplished the SM3 hash algorithm through the combination of these atomic operations.The logic diagram of crypto-operation special circuit is as shown in Figure 4.
The algorithm accelerating engine according to the order that the configuration microcode decides these atomic operations to carry out, is accomplished crypto-operation in work.Configuration microcode itself is through encryption, and is kept to be difficult for being reversed and cracks, among the Flash of high security, do like this than the hardware of simple use standard or the software of standard and accomplish, and security is much higher.
General single chip is generally 8 or 16 MCU, and its processing power is limited on the one hand, and cryptographic hash algorithm itself has 32 computation performance on the other hand, requires MCU to have 32 processing power.From this demand,, improved the efficient and the performance of crypto-operation greatly through integrated cryptographic algorithm accelerating engine with 32 processing poweies.
Other parts of facing the dynamic password chip of the embodiment of the invention are down done an explanation.The dynamic password chip of the embodiment of the invention except MCU and cryptographic algorithm accelerating engine, also comprises artificial circuit part, MCU perimeter component, communications component.Its artificial circuit part mainly comprises power management module, OSC (crystal oscillator), LCD driver module, powers on/under-voltage reset module, voltage and temperature-measuring module.The MCU perimeter component mainly comprises RTC, hardware watchdog (WDT), system's control, PLL (Phase Locked Loop, phaselocked loop) and sequence generation module etc.Communications component mainly comprises UART (Universal Asynchronous Receiver/Transmitter, universal asynchronous reception/transmission) and JTAG (the international standard test protocol is mainly used in the chip internal test) module etc.
When the chip clock generated, sheet had only the crystal of a 32768Hz outward, added the crystal oscillating circuit in the sheet, produced the OSC clock of 32768Hz.This clock is imported PLL as reference clock, and PLL produces some clocks with its frequency multiplication and supplies MCU and ADC (analog digital conversion) to use.The OSC circuit is worked all the time, is a low-power consumption module.Under the default conditions behind the chip reset, this circuitry consumes electric current is 1 μ A, can current sinking be reduced to 0.5 μ A through the MCU configuration.Usually under low temperature and high temperature, crystal output frequency deviation is bigger, so for some occasions high to the RTC accuracy requirement, need proofread and correct the RTC clock.
Chip is by the outer 3V powered battery of sheet, and power management module can be when battery be imported 2.0V～3.0V, for microprocessor and other modules provide stable WV, and stable 3.3V driving voltage is provided for the outer LCD display of sheet.Its principal feature comprises: adopt external power 3V single power supply; Chip internal LCD mu balanced circuit can produce multiple voltage such as 3.0/3.1/3.2/3.3V, is the external LCD power supply; Chip internal mimic channel, IO, digital circuit and PLL etc. use the inner 2.5V power supply that produces; Support the under-voltage reset function, increase system reliability; The monitoring of support low-voltage can be monitored cell voltage in real time.The system architecture of power management is as shown in Figure 5.Wherein, the output voltage of LCD mu balanced circuit is produced by LDO15 and boosted charge pump circuit on the sheet.This output voltage can be adjusted through configuration control corresponding register, and one has four kinds of different output voltage (3.0V/3.1V/3.2V/3.3V) can supply external LCD to use, to support the LCD screen of different model.When externally the cell voltage of input was greater than 2V, charge pump can keep constant output voltage.When external power was lower than 2V, charge pump output can automatically switch to the pattern of following external battery voltage to reduce power consumption.
Mimic channel, IO, digital circuit and PLL in the chip etc. use the 2.5V power supply, and this voltage is produced by the LDO25 circuit.The LDO25 output voltage can be configured to 2.2V, 2.3V, 2.4V or 2.5V.Low-power consumption being required to reduce the LDO25 output voltage,, satisfy different power consumption demand to reduce the power consumption of digital circuit than under the condition with higher.
Chip internal is integrated with the 1.2V reference voltage source, 20ppm/ ℃ of representative temperature drift.The unlatching of this reference voltage and closure are controlled by PLL, and reference voltage source is opened when PLL opens, and reference voltage source is closed when PLL closes.
Reference voltage source circuit is that ADC, PLL and under-voltage reset circuit provide reference voltage and electric current, before opening circuit such as ADC, PLL and under-voltage reset circuit, should open reference voltage source circuit earlier.Reference voltage source is exported one with power consumption, the less reference voltage of temperature variation, and size is about 1.2V.
PLL needs MCU to open, the OSC clock of PLL output 32768Hz before opening.PLL exports 2 clocks, gives MCU and ADC respectively.Configurable to the clock of MCU is 819.2kHz, 1638.4kHz, 3276.8kHz and 6553.6kHz, and the ADC clock is configurable to be 204.8kHz, 409.6kHz, 819.2kHz and 1638.4kHz, and both frequencies automatically keep 4 times of relations all the time.
Power on/the under-voltage reset module during powering on, provide 2 reset source to reset reliably guaranteeing.Power on/level of under-voltage reset module monitors 2.5V LDO25, when the output voltage of LDO25 during greater than 1.8V, reset signal discharges, and before this, chip can be in reset mode always.In the power supply power-fail process, in case the LDO25 level is lower than 1.8V (representative value), the under-voltage reset circuit can provide the reset enable signal chip and be in reset mode.Power on/the under-voltage reset module adjusts duty automatically according to the situation of power supply, do not need MCU to participate in control.
The RTC module functions is for system provides real-time clock and calendar, and have the leap year leap month with adjustment function automatically of big solar month of 30 days.In order to guarantee the accuracy of clock, on the sheet RTC module in indoor design correcting register, can carry out timing automatically according to the corrected value of configuration and proofread and correct.RTC also can export pulse per second (PPS), mentions a second interruption to MCU simultaneously; When system got into Sleep (dormancy) or Deep Sleep (deep dormancy) state, the RTC module is operate as normal still, and can provide day/time/minute/second/waking up of 500ms/250ms/125ms/62.5ms interval to reset.
RTC uses independently, and the OSC clock of 32768Hz carries out timing.RTC can provide real-time clock and calendar, and have the leap year leap month with adjustment function automatically of big solar month of 30 days.RTC inside has correcting register, can carry out timing automatically according to the corrected value of configuration and proofread and correct.RTC can export pulse per second (PPS), mentions a second interruption to MCU simultaneously; When system got into Sleep or Deep Sleep state, RTC is operate as normal still, and can provide day/time/minute/second/waking up of 500ms/250ms/125ms/62.5ms interval to reset.The influence that each mask register of RTC is not resetted.
Voltage and temperature-measuring module are used for measuring cell voltage and temperature.The measurement of cell voltage is used to produce the under-voltage reset signal, and the temperature value that records is used to realize temperature compensation and the correction of the RTC of system.Voltage and temperature-measuring module adopt the M channel arrangement, and the configurable one-tenth of M passage is measured ground, measures temperature, surveyed voltage.In this example, the M passage only disposes an ADC, and then cell voltage, temperature and external signal can only alternately be measured.
Communications component comprises JTAG and serial ports.Wherein JTAG is used for the real-time debug of microprocessor and writing of Flash data.Serial ports is used for writing of user key and data communication.Simultaneously, 2 UART have been realized on the sheet altogether, promptly as the UART0 and the UART1 of the special function register peripheral hardware of MCU.
Chip is provided with hardware watchdog module (WDT), uses independently 32kHz clock.Its schematic diagram is as shown in Figure 6.The outer input of electrification reset/under-voltage reset, sheet resets and system hibernates is waken up to reset etc. and can be removed the WDT counting.Reset after the end, WDT brings into operation automatically, after 1.5 seconds, if software is not removed the WDT counting operation, then produces reset pulse one time.After this, if still do not empty the WDT counting, reset pulse of generation in then per 2 seconds.Duration maintenance 20ms resets.After getting into park mode, WDT quits work automatically; After dormancy resetted and wakes up, WDT restarted operation automatically.
According to the employed clock type of each functional unit of chip, the output of clock control circuit can be divided into following clock.
Clock 1: supply CPU, RAM, FLASH, expansion to interrupt, expand timer/UART and IO use;
Clock 2: system keeps clock output, is in closed condition forever;
Clock 3: supply LCD to use;
Clock 4: supply WDT to use;
Clock 5: supply RTC to use.
Clock control circuit is being controlled the frequency of each clock, and the opening and closing of these clocks.
Clock 1 can use the output of OSC clock also can use pll clock output.Clock 1, clock 3 and clock 4 can be closed, and after clock is closed, use the related circuit unit of this clock to quit work.
Can realize switching and shutoff operation through carrying out the MCU instruction to above-mentioned clock.
124 sections (31SEG*4COM) are supported in the LCD scanning and the driving of LCD driver module at most; In order to reduce the CPU wakeup frequency to reduce power consumption; Demonstration key elements such as LCD driver module support point of scintillation second, progress bar regularly hardware refresh automatically; Be exclusively used in the timing hardware of supporting a second point of scintillation, two SEG to be exclusively used in demonstration key element such as progress bar by a SEG and refresh automatically, reduced the number of times that microprocessor wakes up significantly, further reduced the power consumption of system.
LCD sequential and driving circuit (being the digital circuit part of LCD driver module) use independently 32kHzOSC clock.Outer LCD sequential and the driving circuit of all can resetting that reset of importing of electrification reset, under-voltage reset and sheet.Can close LCD scanning sequence circuit and driving circuit through demonstration control register and Clock management register, make it get into low power consumpting state.
Introduce the principle of work of dynamic password chip below.
In typical dynamic puzzle-lock was used, the user terminal of having authorized has identical plaintext with server end to be imported as computing, adopts identical digest algorithm, and the operation result of finally agreeing is realized authentication.
In order to guarantee security; In dynamic password, cryptographic algorithm, for example the input of the plaintext of the close SM3 algorithm of state is made up of two parts usually; A part is the fixed character string that when the product initialization, is preset to the chip the inside, and this part is changeless in the product use; Another part then is RTC (real-time clock) time on the chip, and this part is time dependent.Fixed character string and RTC time have just constituted the required plaintext of SM3 computing after making up according to certain rule (user decides in its sole discretion by chip).Certainly, for guaranteeing the consistance of user terminal and server end computing, need guarantee both RTC time synchronized, and the fixed character string is identical with the rule of combination of RTC time.
In the application of reality; The user toward chip is disposable insert fixed character string (user key) and carry out the RTC initialization after; Can according to user's requirement periodically (normally per minute once) operate as follows: obtain expressly after the rule reorganization of setting user key and current RTC time according to the user; According to the SM3 algorithm this is expressly carried out computing then and obtain the result later on, and be shown to operation result on the LCD screen with certain rule.
The initialization flow process of chip is as shown in Figure 7: when the user uses chip, at first carries out initialization, comprises writing the fixed character string, i.e. and user key, and carry out the initialization of RTC time.Then carry out normal operating conditions, RTC picks up counting, and per minute is done a SM3 computing, and computing finishes the back and gets into dormant state.
The workflow of chip crypto-operation is as shown in Figure 8: chip is waken up from dormant state; Obtain user key and current RTC time; Combination obtains the SM3 algorithm expressly, starts the computing of making a summary of SM3 cryptographic algorithm accelerating engine, obtains summary result's (being dynamic password); Then output to LCD, get into dormant state again.
In the typical application occasion, chip is configured to dormancy and wakes low power mode of operation alternately up, and only system just can be waken up when carrying out crypto-operation; And after accomplishing crypto-operation fast; System gets into the low-power consumption dormant state immediately, is waken up once more up to system, and its work slice is arranged (the supposing the system work clock is 3.2768MHz) as shown in Figure 9; Can see that the crypto-operation time is no more than 4% in that whole work slice is shared.
After system's completion initialization and key write, chip carried out the dynamic password computing with regard to the starting algorithm accelerating engine.Owing to adopted special-purpose cryptographic algorithm accelerating engine, make to have arithmetic capability at a high speed, the situation that is operated in the 3MHz clock frequency with total system is calculated, and operations such as crypto-operation and LCD demonstration can be accomplished in 40 milliseconds.After this sequence of operations is accomplished fast; System just gets into the low-power consumption dormant state; Dynamic password is locked in whole life with regard to the sd so dormancy with wake low-power consumption duty alternately up, and through product test, its average working current approximately is 7 microamperes; That is to say and use common button cell power supply, system can work for 3～3.5 years.The power consumption index relatively has bigger advantage with currently marketed like product, and visible dynamic password chip of the present invention is a low-power consumption, high performance chip.
The autonomous comprehensive seriation of property right password special chip, hardware and software platform and industrialization are the inexorable trend that improves the national information security level, and the current development of the national economy presses for especially.The invention provides special chip to the low-power consumption of dynamic password ID authentication, high-performance, high security; To realizing the industrialization of password special chip; Improve the development of national information security level, promote the current development of the national economy etc. all to have profound significance.
Above content is to combine concrete embodiment to the further explain that the present invention did, and can not assert that practical implementation of the present invention is confined to these explanations.For the those of ordinary skill of technical field under the present invention, under the prerequisite that does not break away from the present invention's design, can also make some simple deduction or replace, all should be regarded as belonging to protection scope of the present invention.
Claims (10)
1. dynamic password chip; It is characterized in that; Comprise microprocessor, cryptographic algorithm accelerating engine, store on-chip memory and the real-time clock module of presetting key, said microprocessor, cryptographic algorithm accelerating engine, on-chip memory and real-time clock module interconnect through on-chip bus; Said microprocessor is used to coordinate the work of each unit, and said cryptographic algorithm accelerating engine is used for accomplishing crypto-operation according to the real-time time of the preset key of said on-chip memory and real-time clock module.
2. dynamic password chip as claimed in claim 1; It is characterized in that; Said cryptographic algorithm accelerating engine comprises the arithmetic logical operation special circuit; Store the algorithm configuration microcode of said cryptographic algorithm accelerating engine in the said on-chip memory, said arithmetic logical operation special circuit is used under said algorithm configuration microcode guiding, accomplishing arithmetic logical operation.
3. dynamic password chip as claimed in claim 2; It is characterized in that; Said arithmetic logical operation special circuit is 32 arithmetic logical operation special circuits, and said 32 arithmetic logical operations comprise that 32 logical ands, 32 logical ORs, 32 logic XORs, 32 logical inverse, 32 logical shift lefts, 32 bit data additions and 32 bit data move.
4. dynamic password chip as claimed in claim 2 is characterized in that said on-chip memory comprises the Flash that is with read-write protection, and said configuration microcode is stored among the Flash of said band read-write protection.
5. dynamic password chip as claimed in claim 1 is characterized in that, said real-time clock module comprises that the corrected value according to configuration carries out the correcting register that timing is proofreaied and correct automatically.
6. dynamic password chip as claimed in claim 1 is characterized in that, chip is configured to the dormancy mode of operation of low-power consumption under idle condition.
7. dynamic password chip as claimed in claim 1 is characterized in that said chip also comprises voltage and temperature-measuring module.
8. dynamic password chip as claimed in claim 1 is characterized in that said chip also comprises the LCD driver module, and said LCD driver module is provided with SEG mouth that is exclusively used in second point of scintillation and the SEG mouth that is exclusively used in the progress bar demonstration.
9. dynamic password chip as claimed in claim 1 is characterized in that said chip is provided with the hardware watchdog module.
10. dynamic password chip as claimed in claim 1 is characterized in that said chip also comprises communications component, the JTAG mouth that said communications component comprises the real-time debug that is used for microprocessor be used for key and write the serial ports with data communication.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2011100031415A CN102592064A (en) | 2011-01-07 | 2011-01-07 | Dynamic crypto chip |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2011100031415A CN102592064A (en) | 2011-01-07 | 2011-01-07 | Dynamic crypto chip |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN102592064A true CN102592064A (en) | 2012-07-18 |
Family
ID=46480694
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN2011100031415A Pending CN102592064A (en) | 2011-01-07 | 2011-01-07 | Dynamic crypto chip |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN102592064A (en) |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103577736A (en) * | 2013-11-07 | 2014-02-12 | 上海动联信息技术股份有限公司 | Low-power-consumption dynamic token and dynamic password generation method |
| CN104777761A (en) * | 2014-01-15 | 2015-07-15 | 上海华虹集成电路有限责任公司 | Method and circuit for realizing safety of MCU (micro controller unit) |
| CN107105045A (en) * | 2017-05-05 | 2017-08-29 | 恒鸿达科技有限公司 | A kind of convenient packaging process of Wired Security terminal firmware and system |
| CN107483178A (en) * | 2017-07-25 | 2017-12-15 | 深圳华视微电子有限公司 | A kind of device and smart card for realizing Secure Hash Algorithm SHA3 |
| CN108460296A (en) * | 2016-12-09 | 2018-08-28 | 上海新微技术研发中心有限公司 | SOC chip with debugging interface security mechanism and method |
| CN110321725A (en) * | 2019-07-12 | 2019-10-11 | 中孚信息股份有限公司 | A kind of method and device for preventing from distorting system data and clock |
Citations (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1342007A (en) * | 2000-09-05 | 2002-03-27 | 深圳市中兴集成电路设计有限责任公司 | New scrambler |
| CN1517858A (en) * | 2003-01-16 | 2004-08-04 | 威达电股份有限公司 | Method and system for protecting software on additional card of peripheral equipment |
| CN1547353A (en) * | 2003-12-05 | 2004-11-17 | 浩 李 | A high-performance multi-service network security processing equipment |
| CN1831834A (en) * | 2006-04-20 | 2006-09-13 | 成都昊芯科技有限公司 | Dynamic enciphering method and circuit for information |
| US20080201577A1 (en) * | 2007-02-20 | 2008-08-21 | Jonathan Roshan Tuliani | Authentication device and method |
| CN101308529A (en) * | 2007-05-16 | 2008-11-19 | 许丰 | Control method and apparatus for mononuclear safety |
| CN201302731Y (en) * | 2008-11-28 | 2009-09-02 | 东莞市建邦计算机软件有限公司 | Attendance checking access control machine |
| CN101923660A (en) * | 2010-09-07 | 2010-12-22 | 谈剑锋 | Dynamic password identity authorization system and method based on RFID |
| CN101930553A (en) * | 2009-06-23 | 2010-12-29 | 成都昊芯科技有限公司 | Encryption chip system |
-
2011
- 2011-01-07 CN CN2011100031415A patent/CN102592064A/en active Pending
Patent Citations (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1342007A (en) * | 2000-09-05 | 2002-03-27 | 深圳市中兴集成电路设计有限责任公司 | New scrambler |
| CN1517858A (en) * | 2003-01-16 | 2004-08-04 | 威达电股份有限公司 | Method and system for protecting software on additional card of peripheral equipment |
| CN1547353A (en) * | 2003-12-05 | 2004-11-17 | 浩 李 | A high-performance multi-service network security processing equipment |
| CN1831834A (en) * | 2006-04-20 | 2006-09-13 | 成都昊芯科技有限公司 | Dynamic enciphering method and circuit for information |
| US20080201577A1 (en) * | 2007-02-20 | 2008-08-21 | Jonathan Roshan Tuliani | Authentication device and method |
| CN101308529A (en) * | 2007-05-16 | 2008-11-19 | 许丰 | Control method and apparatus for mononuclear safety |
| CN201302731Y (en) * | 2008-11-28 | 2009-09-02 | 东莞市建邦计算机软件有限公司 | Attendance checking access control machine |
| CN101930553A (en) * | 2009-06-23 | 2010-12-29 | 成都昊芯科技有限公司 | Encryption chip system |
| CN101923660A (en) * | 2010-09-07 | 2010-12-22 | 谈剑锋 | Dynamic password identity authorization system and method based on RFID |
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103577736A (en) * | 2013-11-07 | 2014-02-12 | 上海动联信息技术股份有限公司 | Low-power-consumption dynamic token and dynamic password generation method |
| CN104777761A (en) * | 2014-01-15 | 2015-07-15 | 上海华虹集成电路有限责任公司 | Method and circuit for realizing safety of MCU (micro controller unit) |
| CN104777761B (en) * | 2014-01-15 | 2018-04-27 | 上海华虹集成电路有限责任公司 | Realize the method and circuit of MCU securities |
| CN108460296A (en) * | 2016-12-09 | 2018-08-28 | 上海新微技术研发中心有限公司 | SOC chip with debugging interface security mechanism and method |
| CN107105045A (en) * | 2017-05-05 | 2017-08-29 | 恒鸿达科技有限公司 | A kind of convenient packaging process of Wired Security terminal firmware and system |
| CN107483178A (en) * | 2017-07-25 | 2017-12-15 | 深圳华视微电子有限公司 | A kind of device and smart card for realizing Secure Hash Algorithm SHA3 |
| CN107483178B (en) * | 2017-07-25 | 2020-08-28 | 深圳华视微电子有限公司 | Device for realizing secure Hash Algorithm SHA3 and smart card |
| CN110321725A (en) * | 2019-07-12 | 2019-10-11 | 中孚信息股份有限公司 | A kind of method and device for preventing from distorting system data and clock |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN102592064A (en) | Dynamic crypto chip | |
| CN201974474U (en) | State grid three-phase intelligent electric energy meter | |
| JP5410109B2 (en) | Power control system and power control method | |
| CN201607626U (en) | High stability real-time clock circuit | |
| CN102037428A (en) | Integrated circuit with secondary-memory controller for providing a sleep state for reduced power consumption and method therefor | |
| CN106648025A (en) | Always on display method and terminal | |
| CN101581963B (en) | Method for reducing CPU power consumption and CPU | |
| CN102821446B (en) | Synchronous awaking mechanism of long-term and deep dormant wireless sensor network | |
| Kate et al. | ZIGBEE based monitoring theft detection and automatic electricity meter reading | |
| CN103186218A (en) | Computer start-up system and computer start-up method | |
| CN111323626A (en) | Uncovering detection circuit integrated in MCU and uncovering detection method based on MCU | |
| CN103150828A (en) | Local carrier single-phase fee-controlled intelligent electric energy meter | |
| CN203101893U (en) | Anti-electricity stealing controller | |
| CN202372571U (en) | Remote carrier wave single-phase cost control intelligent electric energy meter | |
| CN202110793U (en) | Nixie tube driving chip and household electrical appliance using same | |
| CN108717173A (en) | A kind of method that intelligent electric energy meter data are traced to the source | |
| TWI649666B (en) | Automatic scheduling backup system and method thereof | |
| CN103150827A (en) | Local single-phase fee-controlled intelligent electric energy meter | |
| CN201378835Y (en) | Hardware token | |
| CN202339602U (en) | Local single-phase cost control smart electric energy meter | |
| CN108375896A (en) | A kind of content display method of smartwatch, device and smartwatch | |
| CN105183432B (en) | A kind of SoC systems towards health control | |
| CN103149400A (en) | Intelligent ammeter in remote single phase cost control | |
| CN202339600U (en) | Local-carrier single-phase cost-control intelligent watt-hour meter | |
| US20080094246A1 (en) | Auto turn-on module and player apparatus and method for turning on a system automatically |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C12 | Rejection of a patent application after its publication | ||
| RJ01 | Rejection of invention patent application after publication |
Application publication date: 20120718 |