CN102565684A - Security-based scan chain control circuit, scan chain testing circuit and use method - Google Patents
Security-based scan chain control circuit, scan chain testing circuit and use method Download PDFInfo
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- CN102565684A CN102565684A CN2010105848979A CN201010584897A CN102565684A CN 102565684 A CN102565684 A CN 102565684A CN 2010105848979 A CN2010105848979 A CN 2010105848979A CN 201010584897 A CN201010584897 A CN 201010584897A CN 102565684 A CN102565684 A CN 102565684A
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Abstract
The invention discloses a security-based scan chain control circuit. The scan chain control circuit comprises a primary programmable device unit and a combinational logic unit, wherein the primary programmable device unit is connected with the combinational logic unit; the combinational logic unit is connected with all scan chains; two control signals of scan mode and scan shift enable signals in the scan chains are provided to all scan chains by the primary programmable device through the combinational logic; and other control signals in the scan chains are provided by external pins. The invention also discloses a scan chain testing circuit, and a scan chain testing circuit use method.
Description
Technical field
The present invention relates to a kind of testing scanning chain circuit, the control circuit in particularly a kind of testing scanning chain circuit.
Background technology
Because the consideration of testing cost, the testing scanning chain method is widely accepted, such as testing scanning chain.But because the security classes chip based on security consideration, if use the most original function test method, makes testing cost to reduce.And if employing testing scanning chain method can't be protected safely.Because in existing testing scanning chain method; The control signal clock CLK of all registers in the testing scanning chain circuit, the RST that resets, scan pattern TEST_MODE and scan shift enable SCAN_EN and all directly control (see figure 1) by external pin; The user can read the numerical value of any register at any time, makes entire chip have no secret to say.
For social security class chip, safety is the first element, and the partial logic that safety itself comprises in the chip is invisible.Obviously, traditional testing scanning chain method has been run counter to this demand.
Summary of the invention
The technical matters that the present invention will solve provides a kind of testing scanning chain circuit based on safety, and it can security protection.
For solving the problems of the technologies described above, the testing scanning chain circuit based on safety of the present invention, it comprises control circuit, this control circuit comprises disposable programmable device cell and combinatorial logic unit; The disposable programmable device cell is connected to combinatorial logic unit, and combinatorial logic unit is connected to all scan chains; Scan pattern in the said scan chain and scan shift enable these two control signals and offer all scan chains by the disposable programmable device through combinational logic, and other control signals in the said scan chain are provided by external pin.
The present invention also discloses a kind of method of using the testing scanning chain circuit, and for before dispatching from the factory, scan pattern that employing disposable programmable device cell provides and scan shift enable these two control signals and test; After test finishes, revise the disposable programmable device value in the disposable programmable device cell, control signal was lost efficacy.
Scan chain control circuit of the present invention, the form that adopts the OTP parts unit to add combinational logic replace external pin to be provided scan pattern TEST_MODE and scan shift to enable the SCAN_EN control signal to test to scan chain.And after test is accomplished, revise OTP value and make the control signal inefficacy, make the user advance not the scan chain pattern, thereby solved the security information of chip internal is spied upon by domestic consumer through scan chain problem.And employed OTP parts can be OTP parts existing in the chip in the control circuit of the present invention, does not need extra increase.The present invention moves on to the part control signal of scan chain the OTP parts from pin, solve safety problem, and the OTP parts that is adopted can be OTP parts unnecessary in the chip, the expense of the input and output pin that also reduces simultaneously.
Description of drawings
Below in conjunction with accompanying drawing and embodiment the present invention is done further detailed explanation:
Fig. 1 provides synoptic diagram for existing scan chain control signal;
Fig. 2 provides synoptic diagram for scan chain control signal of the present invention.
Embodiment
Control circuit (see figure 2) of the present invention comprises OTP (disposable programmable device) unit and combinatorial logic unit; The output of disposable programmable device cell is connected to combinatorial logic unit, and combinatorial logic unit is connected to all scan chains; Scan pattern TEST_MODE in the scan chain and scan shift enable these two control signals of SCAN_EN and offer all scan chains by the disposable programmable device through combinational logic.And other control signals of scan chain still provide through external pin.
Concrete TEST_MODE and the SCAN_EN control signal of output after the output process specific combined logical block of OTP unit.Not having strict restriction in the combinatorial logic unit here, make up according to demand, can be the simplest directly connection, also can be comparatively complex mathematical computing, and purpose is TEST_MODE to all scan chains to be provided, these two control signals of SCAN_EN.As under the situation of two OTP signals of output, can be direct connection, these two OTP signals are exported to scan chain.And when being output as under the situation of plural OTP signal; Just can do a little mathematical operations through combinational logic; What make final output is two useful signals, exports to scan chain, can better guarantee like this security (even the user more difficulty obtain security information).
Testing scanning chain circuit of the present invention is to comprise above-mentioned control circuit, is used for providing the scan pattern TEST_MODE of testing scanning chain and scan shift to enable these two control signals of SCAN_EN.
The method of application of scan test circuit of the present invention is: before dispatching from the factory, initial configuration (being initial value) the entering scan chain state according to OTP carries out the volume production test; After all tests finish, revise the OTP value, make the scan chain control signal lose efficacy.Employed OTP parts among the present invention can adopt the OTP parts of having more than needed in original design of chip, can reduce the expenditure of input and output pin simultaneously, has therefore lowered testing cost.
Because the characteristic of OTP is for can only revise once, therefore after modification OTP value, the user has just advanced not the scan chain pattern, thereby has solved the user spies upon the chip internal security information through scan chain problem.
Claims (4)
1. scan chain control circuit based on safety, it is characterized in that: said control circuit comprises disposable programmable device cell and combinatorial logic unit; Said disposable programmable device cell is connected to said combinatorial logic unit, and said combinatorial logic unit is connected to all scan chains; Scan pattern in the said scan chain and scan shift enable these two control signals and offer all scan chains by the disposable programmable device through combinational logic, and other control signals in the said scan chain are provided by external pin.
2. according to the described scan chain control circuit of claim 1, it is characterized in that: the disposable programmable device in the said disposable programmable device cell adopts disposable programmable device more than needed in the chip.
3. testing scanning chain circuit based on safety, it is characterized in that: said testing scanning chain circuit comprises control circuit, and said control circuit comprises disposable programmable device cell and combinatorial logic unit; Said disposable programmable device cell is connected to said combinatorial logic unit, and said combinatorial logic unit is connected to all scan chains; Control signal TEST_MODE in the said scan chain and SCAN_EN provide all scan chains by the disposable programmable device through combinational logic, and other control signals in the said scan chain are provided by external pin.
4. method of using the testing scanning chain circuit is characterized in that:
Before dispatching from the factory, scan pattern that employing disposable programmable device cell provides and scan shift enable these two control signals and test;
After test finishes, revise the disposable programmable device value in the said disposable programmable device cell, said control signal was lost efficacy.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2010105848979A CN102565684A (en) | 2010-12-13 | 2010-12-13 | Security-based scan chain control circuit, scan chain testing circuit and use method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2010105848979A CN102565684A (en) | 2010-12-13 | 2010-12-13 | Security-based scan chain control circuit, scan chain testing circuit and use method |
Publications (1)
| Publication Number | Publication Date |
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| CN102565684A true CN102565684A (en) | 2012-07-11 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN2010105848979A Pending CN102565684A (en) | 2010-12-13 | 2010-12-13 | Security-based scan chain control circuit, scan chain testing circuit and use method |
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Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102967824A (en) * | 2011-08-31 | 2013-03-13 | 上海华虹集成电路有限责任公司 | Scan chain control circuit and implementation method thereof |
| CN104134466A (en) * | 2014-07-23 | 2014-11-05 | 大唐微电子技术有限公司 | Chip and test state entering method thereof |
| CN104808519A (en) * | 2015-02-25 | 2015-07-29 | 浪潮电子信息产业股份有限公司 | Chip embedded OTP (One Time Programmable) module control method |
| CN106324463A (en) * | 2015-06-19 | 2017-01-11 | 上海华虹集成电路有限责任公司 | Scan chain control circuit design method and scan chain circuit |
| CN112462244A (en) * | 2020-10-28 | 2021-03-09 | 苏州浪潮智能科技有限公司 | Clock control device for scan chain test |
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| CN1650183A (en) * | 2002-04-30 | 2005-08-03 | 飞思卡尔半导体公司 | Method and apparatus for secure scan testing |
| US7228440B1 (en) * | 2002-02-13 | 2007-06-05 | Lsi Corporation | Scan and boundary scan disable mechanism on secure device |
| CN101169755A (en) * | 2006-10-27 | 2008-04-30 | 北京中电华大电子设计有限责任公司 | Test pin free contact type CPU card test method |
| US20080143373A1 (en) * | 2004-12-17 | 2008-06-19 | Bonaccio Anthony R | Using electrically programmable fuses to hide architecture, prevent reverse engineering, and make a device inoperable |
| CN101238382A (en) * | 2005-08-10 | 2008-08-06 | Nxp股份有限公司 | Testing of an integrated circuit that contains secret information |
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2010
- 2010-12-13 CN CN2010105848979A patent/CN102565684A/en active Pending
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
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| US7228440B1 (en) * | 2002-02-13 | 2007-06-05 | Lsi Corporation | Scan and boundary scan disable mechanism on secure device |
| CN1650183A (en) * | 2002-04-30 | 2005-08-03 | 飞思卡尔半导体公司 | Method and apparatus for secure scan testing |
| US20080143373A1 (en) * | 2004-12-17 | 2008-06-19 | Bonaccio Anthony R | Using electrically programmable fuses to hide architecture, prevent reverse engineering, and make a device inoperable |
| CN101238382A (en) * | 2005-08-10 | 2008-08-06 | Nxp股份有限公司 | Testing of an integrated circuit that contains secret information |
| CN101169755A (en) * | 2006-10-27 | 2008-04-30 | 北京中电华大电子设计有限责任公司 | Test pin free contact type CPU card test method |
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102967824A (en) * | 2011-08-31 | 2013-03-13 | 上海华虹集成电路有限责任公司 | Scan chain control circuit and implementation method thereof |
| CN102967824B (en) * | 2011-08-31 | 2016-05-25 | 上海华虹集成电路有限责任公司 | A kind of scan chain control circuit and its implementation |
| CN104134466A (en) * | 2014-07-23 | 2014-11-05 | 大唐微电子技术有限公司 | Chip and test state entering method thereof |
| CN104134466B (en) * | 2014-07-23 | 2017-05-10 | 大唐微电子技术有限公司 | Chip and test state entering method thereof |
| CN104808519A (en) * | 2015-02-25 | 2015-07-29 | 浪潮电子信息产业股份有限公司 | Chip embedded OTP (One Time Programmable) module control method |
| CN106324463A (en) * | 2015-06-19 | 2017-01-11 | 上海华虹集成电路有限责任公司 | Scan chain control circuit design method and scan chain circuit |
| CN112462244A (en) * | 2020-10-28 | 2021-03-09 | 苏州浪潮智能科技有限公司 | Clock control device for scan chain test |
| CN112462244B (en) * | 2020-10-28 | 2022-07-01 | 苏州浪潮智能科技有限公司 | Clock control device for scan chain test |
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Application publication date: 20120711 |