CN102545868A - ORing Fet blocking circuit and power system - Google Patents
ORing Fet blocking circuit and power system Download PDFInfo
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- CN102545868A CN102545868A CN2011104484819A CN201110448481A CN102545868A CN 102545868 A CN102545868 A CN 102545868A CN 2011104484819 A CN2011104484819 A CN 2011104484819A CN 201110448481 A CN201110448481 A CN 201110448481A CN 102545868 A CN102545868 A CN 102545868A
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Abstract
An embodiment of the invention discloses an ORing Fet blocking circuit, which is connected between a single power module and an output bus. The ORing Fet blocking circuit comprises a field-effect tube, a first transistor and a second transistor; a source electrode of the field-effect tube is connected with the output of the power module while a drain electrode of the field-effect tube is connected with the output bus; an emitting electrode of the first transistor is connected with the source electrode of the field-effect tube while a collector electrode of the first transistor is connected with a gate electrode of the field-effect tube; a first end of the second transistor is connected with the drain electrode of the field-effect tube while a second end of the second transistor is connected with a base electrode of the first transistor, and the second end and a third end of the second transistor are in short connection; and the collector electrode of the first transistor and the third end of the second transistor are connected with a working power source. The embodiment of the invention further discloses a power system. In the embodiment of the invention, ORing control efficiency can be improved, and further, the circuit is simple in structure and easy to be realized.
Description
Technical field
The present invention relates to the power-supply system technical field, particularly relate to a kind of ORing Fet blocking circuit and power-supply system.
Background technology
In a power-supply system that outputs to an output bus by a lot of power supply product parallel connections; The ORing circuit generally can be placed between individual module and the output bus, and it is unusual that its purpose is to prevent to cause whole power-supply system to take place because certain power supply product in the power-supply system takes place unusual.
ORing circuit commonly used now can comprise one or more FET (Field-Effect Transistor, field-effect transistor) and their comparison circuit of control usually.With reference to Fig. 1, be a kind of ORing circuit structure diagram commonly used now.Shown in Figure 1 is that example describes with the ORing circuit that comprises a FET.
Said ORing circuit comprises: FET manages M1, comparator U1 and resistance R 1 and resistance R 2.The output INPUT of the source electrode of said FET pipe M1 and drain electrode difference connection module and output bus OUTPUT; The normal phase input end of said comparator U1 meets the output INPUT of said module, and its inverting input meets said output bus OUTPUT, and its output connects the gate pole of said FET pipe M1 through resistance R 2.
Said comparator U1 controls turning on and off of said FET pipe M1 through detecting busbar voltage and inside modules voltage.
When certain threshold voltage that the pressure reduction of said busbar voltage and inside modules voltage is provided with greater than said comparator U1, said FET pipe M1 is switched on.At this moment, the electric current of module is just flowed through FET pipe M1 to the output bus, and its voltage drop is exactly the output current that the conducting resistance of FET pipe M1 multiply by module.
When certain threshold voltage that the pressure reduction of busbar voltage and inside modules voltage is provided with less than said comparator U1, said FET pipe M1 is ended.
Existing ORing circuit commonly used adopts comparator control FET pipe, and sort circuit has following defective: can there be side-play amount in the input of said comparator, and these side-play amounts can influence the control to FET pipe break-make point; When skew is forward; The FET pipe is not opened in the time of can causing output current smaller; So generally need be, but like this, just inevitably make when busbar voltage is higher than module voltage with the comparison of opening threshold design of comparator near negative pressure; Have reverse current to irritate back module from bus, and reverse current when not reaching certain threshold value the FET pipe can't turn-off.Simultaneously, existing ORing circuit need be provided with comparator, makes circuit cost higher.
Summary of the invention
In view of this, the object of the present invention is to provide a kind of ORing Fet blocking circuit and power-supply system, this circuit can improve the efficient of ORing control, and circuit structure simple, be easy to realize.
The embodiment of the invention provides a kind of ORing Fet blocking circuit, and said circuit is connected between single power module and the output bus; Said circuit comprises: a FET, the first transistor and transistor seconds;
The source electrode of said FET connects the output of power module, and the drain electrode of said FET connects the output bus;
The emitter of said the first transistor connects the source electrode of said FET, and the collector electrode of said the first transistor connects the gate pole of said FET;
The drain electrode of the said FET of first termination of said transistor seconds, the base stage of the said the first transistor of second termination of said transistor seconds, second end of said transistor seconds and the 3rd end short circuit;
The 3rd termination working power of the collector electrode of said the first transistor and said transistor seconds.
The embodiment of the invention also provides a kind of power-supply system, and said power-supply system comprises: at least one power module, each power module connect the output bus through a described ORing Fet blocking circuit respectively.
According to specific embodiment provided by the invention, the invention discloses following technique effect:
The said ORing Fet of embodiment of the invention blocking circuit; Adopt two transistors to come optionally to control opening or turn-offing of said FET; Compare with the ORing circuit of the employing comparator of routine; Can avoid effectively improving the efficient of ORing control because of the influence that control causes to ORing of the Input Offset Value of comparator, and circuit structure simple, be easy to realize.
Description of drawings
Fig. 1 is a kind of ORing circuit structure diagram commonly used now;
Fig. 2 is the ORing Fet blocking circuit structure chart of the embodiment of the invention one;
Fig. 3 is the ORing Fet blocking circuit structure chart of the embodiment of the invention two;
Fig. 4 is the power system structure figure of the embodiment of the invention.
Embodiment
For make above-mentioned purpose of the present invention, feature and advantage can be more obviously understandable, below in conjunction with accompanying drawing and embodiment the present invention done further detailed explanation.
In view of this, the object of the present invention is to provide a kind of ORing Fet blocking circuit and power-supply system, this circuit can improve the efficient of ORing control, and circuit structure simple, be easy to realize.
The said ORing Fet of embodiment of the invention blocking circuit is used for power-supply system, is arranged between single power module and the output bus.
Said ORing Fet blocking circuit comprises: a FET, the first transistor and transistor seconds.
Said FET is connected between power module and the output bus; Concrete, the source electrode of said FET connects the output of power module, and the drain electrode of said FET connects the output bus.
The emitter of said the first transistor connects the source electrode of said FET, and the collector electrode of said the first transistor connects the gate pole of said FET.
The drain electrode of the said FET of first termination of said transistor seconds, the base stage of the said the first transistor of second termination of said transistor seconds, second end of said transistor seconds and the 3rd end short circuit.
The 3rd termination working power of the collector electrode of said the first transistor and said transistor seconds.
The said ORing Fet of embodiment of the invention blocking circuit; Adopt two transistors to come optionally to control opening or turn-offing of said FET; Compare with the ORing circuit of the employing comparator of routine; Can avoid effectively improving the efficient of ORing control because of the influence that control causes to ORing of the Input Offset Value of comparator, and circuit structure simple, be easy to realize.
With reference to Fig. 2, be the ORing Fet blocking circuit structure chart of the embodiment of the invention one.As shown in Figure 2, said ORing Fet blocking circuit comprises: a FET, the first transistor and transistor seconds.
Concrete, as shown in Figure 2, said FET is a FET pipe 102; Said the first transistor can be triode, shown in first triode 104 among Fig. 2; Said transistor seconds also can be specially a triode, shown in second triode 106 among Fig. 2.
First end of the very said transistor seconds of the emission of said second triode 106; The base stage of said second triode 106 is second end of said transistor seconds; The 3rd end of the very said transistor seconds of the current collection of said second triode 106.
The source electrode of said FET pipe 102 links to each other with power module as the input node Vout IN of said ORing Fet circuit, is used to receive the voltage of coming from said power module; The drain electrode of said FET pipe 102 connects the output bus as the output node Vout local of said ORing Fet circuit, is used to the output bussed supply.
The emitter of said first triode 104 links to each other with the source electrode of said FET pipe 102, and the collector electrode of said first triode 104 links to each other with the gate pole of said FET pipe 102, and the base stage of said first triode 104 links to each other with the base stage of said second triode 106.
The emitter of said second triode 106 links to each other the base stage of said second triode 106 and collector electrode short circuit with the drain electrode of said FET pipe 102.
The collector electrode of the collector electrode of said first triode 104 and second triode 106 connects working power.
As shown in Figure 2; The source electrode of said FET pipe 102 links to each other with input node Vout IN; Its drain electrode links to each other with output node Vout local, and in this case, the electric current between input node Vout IN and the output node Vout local changes with the state of FET pipe 102.For example, when the base stage of FET pipe 102 is in following time of state of conducting, electric current can flow to output node Vout local from input node Vout IN; And when the base stage of FET pipe 102 was in not on-state, electric current will be ended.
Operation principle in the face of the said ORing Fet of embodiment of the invention circuit describes in detail down:
In the said ORing Fet of the embodiment of the invention circuit, adopt the first transistor and transistor seconds to come optionally to control opening or turn-offing of said FET pipe 102.Concrete, in conjunction with Fig. 2, utilize first triode 104 and second triode 106 to control the break-make of FET pipe 102.
Said ORing Fet circuit is when work, and the opening state of said FET pipe 102 is mainly still decided by the input voltage (being the voltage of input node Vout IN) and the difference of output busbar voltage (being the voltage of output node Vout local).
When said output busbar voltage was higher than input voltage, said FET pipe 102 kept off state, breaks off input node Vout IN and output node Vout local; When said output busbar voltage was lower than output voltage, said FET pipe 102 possibly get into the state of active conducting or complete conducting, and this moment, electric current flowed to output node Vout local from input node Vout IN.
When said output busbar voltage was higher than input voltage suddenly, the body diode of said FET pipe 102 will stop reverse charging.Said transistor seconds (second triode 106 among Fig. 2) also can raise and not conducting because of the voltage of output busbar voltage; At this moment; Transistor seconds voltage raises; Because its base stage and emitter short circuit can cause the base voltage rising of coupled the first transistor (first triode 104 among Fig. 2) thus and make said the first transistor get into saturation condition.Will cause the gate pole of FET pipe 102 always to be in the state that is dragged down like this, FET pipe 102 is in off state.
When said input voltage begins to rise to the output busbar voltage; The body diode of said FET pipe 102 begins forward conduction; Said transistor seconds conducting also begins to extract the electric current of being come by the first transistor; May make the first transistor withdraw from saturation condition like this, reduce the electric current of collector electrode and increase the voltage of collector electrode.At this moment, the collector voltage of the first transistor rises, and the gate voltage of FET pipe 102 begins to rise.When the gate voltage of FET pipe 102 reached threshold value VghTH, said FET pipe 102 was operated in conducting state.
Preferably, in the said ORing Fet of the embodiment of the invention circuit, said working power can be the accessory power supply of outside, and said the first transistor and transistor seconds are supplied power by said accessory power supply.Concrete, the collector electrode of the collector electrode of said first triode 104 and said second triode 106 connects accessory power supply through a resistance respectively.
As shown in Figure 2, said accessory power supply is in figure shown in the BIAS, and said ORing Fet circuit can also comprise first resistance 114, second resistance 116, the 3rd resistance 118.One end of said first resistance 114 of the output termination of said accessory power supply BIAS; The other end of said first resistance 114 connects the collector electrode of said first triode 104 through second resistance 116, and the other end of said first resistance 114 connects the collector electrode of said second triode 106 through the 3rd resistance 118.
In the ordinary course of things, the gate pole of FET pipe 102 can have very little electric current to flow through or conducting during very little body diode pressure drop at output node Vout local, can adjust the conducting of MOSFET pipe 102 and the speed of shutoff through the value of adjusting second resistance 116 thus.
Preferably, said ORing Fet circuit can also comprise: voltage stabilizing didoe 120.The negative electrode of said voltage stabilizing didoe 120 connects the common port of said first resistance 114, second resistance 116 and the 3rd resistance 118, and the anode of said voltage stabilizing didoe 120 connects the source electrode of said FET pipe 102, is input node Vout IN.
At this moment, said first triode 104 and second triode 106 are by the accessory power supply power supply after said voltage stabilizing didoe 120 and 114 voltage stabilizings of said first resistance.
In the embodiment of the invention one described ORing Fet blocking circuit, said transistor seconds is specially a triode, and this triode adopts diode connected mode, its base stage and collector electrode short circuit.In other embodiment of the present invention, said transistor seconds also can directly adopt a diode.
With reference to Fig. 3, be the ORing Fet blocking circuit structure chart of the embodiment of the invention two.Embodiment illustrated in fig. 3 two and embodiment illustrated in fig. 2 one difference is: said transistor seconds is a diode 108.
The negative electrode of said diode 108 is as first end of said transistor seconds; The anode of said diode 108 is as second end and the 3rd end of said transistor seconds.
The negative electrode of said diode 108 links to each other with the drain electrode of said FET pipe 102, and the anode of said diode 108 links to each other with the base stage of said first triode 104
The collector electrode of the anode of said diode 108 and said first triode 104 connects working power.
The operation principle of the embodiment of the invention two said ORing Fet circuit is identical with embodiment one, repeats no more at this.
Preferably, in the embodiment two said ORing Fet circuit, said working power also can be the accessory power supply of outside, is said the first transistor and transistor seconds and is supplied power by said accessory power supply.Concrete, as shown in Figure 3, the anode of the collector electrode of said first triode 104 and said diode 108 connects accessory power supply through a resistance respectively.
As shown in Figure 3, said accessory power supply is in figure shown in the BIAS, and said ORing Fet circuit can also comprise first resistance 114, second resistance 116, the 4th resistance 112.One end of said first resistance 114 of the output termination of said accessory power supply BIAS; The other end of said first resistance 114 connects the collector electrode of said first triode 104 through second resistance 116, and the other end of said first resistance 114 connects the anode of said diode 108 through the 4th resistance 112.
Same, among the embodiment two, said ORing Fet circuit can also comprise: voltage stabilizing didoe 120.The negative electrode of said voltage stabilizing didoe 120 connects the common port of said first resistance 114, second resistance 116 and the 4th resistance 112, and the anode of said voltage stabilizing didoe 120 connects the source electrode of said MOSFET pipe 102, is input node Vout IN.
At this moment, said first triode 104 and diode 108 are by the accessory power supply power supply after said voltage stabilizing didoe 120 and 114 voltage stabilizings of said first resistance.
Preferably, in the embodiment of the invention one and the embodiment two described ORing Fet circuit, said the first transistor and transistor seconds can be arranged on an encapsulation the inside.
Further, said encapsulation can be the SOT323 encapsulation of one 6 pin.
Corresponding to the ORing Fet blocking circuit that the above embodiment of the present invention provides, the embodiment of the invention also provides a kind of power-supply system.With reference to Fig. 4, be the power system structure figure of the embodiment of the invention.
As shown in Figure 4, said power-supply system comprises: at least one power module 202, each power module 202 connect common output bus 204 through an ORing Fet blocking circuit 100 respectively.
Said ORing Fet blocking circuit 100 can be arbitrary ORing Fet blocking circuit in the previous embodiment.
Each said power module 202 is connected with the input node Vout IN of each self-corresponding ORing Fet blocking circuit 100 respectively, and the output node Vout local of said ORing Fet blocking circuit 100 connects said output bus 204.
When said power-supply system was worked, all power modules 202 all can be good at work, and the input node Vout IN that each power module 202 is respectively ORing Fet blocking circuit 100 separately provides the voltage a little more than output bus 204.At this moment, the FET in the said ORing Fet blocking circuit 100 (FET pipe 102) will be operated in saturated or amplification region, and power module 202 is 204 chargings of output bus.
When one of them power module 202 broke down, the power module 202 of this fault can make its corresponding ORing Fet blocking circuit 100 close, and at this moment, the FET in this ORing Fet blocking circuit 100 (FET pipe 102) is in off state.Can effectively avoid in the power-supply system thus,, help improving the reliability of whole power-supply system work because of the voltage of individual module fault with whole power-supply system drags down.
More than to a kind of ORing Fet blocking circuit provided by the present invention and power-supply system; Carried out detailed introduction; Used concrete example among this paper principle of the present invention and execution mode are set forth, the explanation of above embodiment just is used for helping to understand method of the present invention and core concept thereof; Simultaneously, for one of ordinary skill in the art, according to thought of the present invention, part all can change on embodiment and range of application.In sum, this description should not be construed as limitation of the present invention.
Claims (9)
1. an ORing Fet blocking circuit is characterized in that, said circuit is connected between single power module and the output bus; Said circuit comprises: a FET, the first transistor and transistor seconds;
The source electrode of said FET connects the output of power module, and the drain electrode of said FET connects the output bus;
The emitter of said the first transistor connects the source electrode of said FET, and the collector electrode of said the first transistor connects the gate pole of said FET;
The drain electrode of the said FET of first termination of said transistor seconds, the base stage of the said the first transistor of second termination of said transistor seconds, second end of said transistor seconds and the 3rd end short circuit;
The 3rd termination working power of the collector electrode of said the first transistor and said transistor seconds.
2. ORing Fet blocking circuit according to claim 1 is characterized in that said transistor seconds is a triode;
First end of the very said transistor seconds of the emission of said triode; The base stage of said triode is second end of said transistor seconds; The 3rd end of the very said transistor seconds of the current collection of said triode.
3. ORing Fet blocking circuit according to claim 1 is characterized in that said transistor seconds is a diode;
The negative electrode of said diode is as first end of said transistor seconds; The anode of said diode is as second end and the 3rd end of said transistor seconds.
4. according to each described ORing Fet blocking circuit of claim 1 to 3, it is characterized in that working power is an accessory power supply, said the first transistor and transistor seconds are supplied power by said accessory power supply.
5. ORing Fet blocking circuit according to claim 4 is characterized in that said circuit also comprises: first resistance, second resistance and the 3rd resistance;
One end of said first resistance of output termination of said accessory power supply;
The other end of said first resistance connects the collector electrode of said the first transistor through said second resistance;
The other end of said first resistance connects the 3rd end of said transistor seconds through said the 3rd resistance.
6. ORing Fet blocking circuit according to claim 5 is characterized in that said circuit also comprises: voltage stabilizing didoe;
The negative electrode of said voltage stabilizing didoe connects the common port of said first resistance, second resistance and the 3rd resistance, and the anode of said voltage stabilizing didoe connects the source electrode of said FET.
7. according to claim 1 to 3,5,6 each described ORing Fet blocking circuits, it is characterized in that said the first transistor and transistor seconds are arranged on an encapsulation the inside.
8. ORing Fet blocking circuit according to claim 7 is characterized in that, the said SOT323 encapsulation that is encapsulated as one 6 pin.
9. a power-supply system is characterized in that, said power-supply system comprises: at least one power module, each power module connect the output bus through one like each described ORing Fet blocking circuit of claim 1 to 8 respectively.
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| CN2011104484819A CN102545868A (en) | 2011-12-28 | 2011-12-28 | ORing Fet blocking circuit and power system |
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| CN2011104484819A CN102545868A (en) | 2011-12-28 | 2011-12-28 | ORing Fet blocking circuit and power system |
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| CN2011104484819A Pending CN102545868A (en) | 2011-12-28 | 2011-12-28 | ORing Fet blocking circuit and power system |
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Cited By (7)
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| WO2016197500A1 (en) * | 2015-06-11 | 2016-12-15 | 中兴通讯股份有限公司 | Oring control circuit and electricity power system |
| CN106300321A (en) * | 2016-08-31 | 2017-01-04 | 四川升华电源科技有限公司 | Power supply anti-back flow circuit |
| CN109921385A (en) * | 2017-12-13 | 2019-06-21 | 泰达电子股份有限公司 | ORING circuit |
| WO2019143594A1 (en) * | 2018-01-17 | 2019-07-25 | Appleton Grp Llc | Self-driving control circuit for power switches as synchronous rectifier |
| CN112968429A (en) * | 2021-02-04 | 2021-06-15 | 高新兴物联科技有限公司 | Switch short-circuit protection circuit based on P-channel MOS tube |
| CN113659818A (en) * | 2021-08-06 | 2021-11-16 | 深圳信息职业技术学院 | Ideal diode circuit |
| CN116054791A (en) * | 2023-01-17 | 2023-05-02 | 上海军陶科技股份有限公司 | OringFET control circuit based on hysteresis comparator |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| WO2016197500A1 (en) * | 2015-06-11 | 2016-12-15 | 中兴通讯股份有限公司 | Oring control circuit and electricity power system |
| CN106300321A (en) * | 2016-08-31 | 2017-01-04 | 四川升华电源科技有限公司 | Power supply anti-back flow circuit |
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| CN112968429A (en) * | 2021-02-04 | 2021-06-15 | 高新兴物联科技有限公司 | Switch short-circuit protection circuit based on P-channel MOS tube |
| CN112968429B (en) * | 2021-02-04 | 2023-02-28 | 高新兴物联科技股份有限公司 | Switch short-circuit protection circuit based on P-channel MOS tube |
| CN113659818A (en) * | 2021-08-06 | 2021-11-16 | 深圳信息职业技术学院 | Ideal diode circuit |
| CN116054791A (en) * | 2023-01-17 | 2023-05-02 | 上海军陶科技股份有限公司 | OringFET control circuit based on hysteresis comparator |
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Application publication date: 20120704 |