CN102543209B - The error correction device of multi-channel flash memory controller, method and multi-channel flash memory controller - Google Patents
The error correction device of multi-channel flash memory controller, method and multi-channel flash memory controller Download PDFInfo
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Abstract
The invention provides the error correction device of multi-channel flash memory controller, method and multi-channel flash memory controller, described error correction device comprises coding/decoding module and miscount module, described coding/decoding module specifically comprises a combinational logic circuit and the multichannel multiple sequential logical circuit of correspondence, described coding/decoding module also comprises: MUX, for each channel data validity according to current period, the data of effective for correspondence passage and sequential logic register information are selected in described combinational logic circuit; Load module, for inputting the operation result of described combinational logic circuit in the sequential logic register of the effective passage of described correspondence.Adopt error correction device, error correction method and multi-channel flash memory controller disclosed in the embodiment of the present invention, error correction method of the prior art can be solved and all independently can take correction module because of each passage, and make cost extremely expensive and the problem of waste ample resources.
Description
Technical field
The present invention relates to data processing field, particularly relate to a kind of error correction device of multi-channel flash memory controller, method and multi-channel flash memory controller.
Background technology
The process produced along with flash memory constantly declines, and the information of single cell stores constantly increases, and the probability that flash memory is made mistakes is also increasing, needs the error correcting capability of correction module to improve constantly.Storage unit can be divided into two classes: SLC (Single Level Cell, single layer cell) and MLC (Multi-Level Cell, multilevel-cell).SLC requires that every 256 bytes (Byte) correct 1 bit (bit) mistake, and MLC requires that every 512Byte corrects 4-8bit mistake, and the flash memory of most up-to-date techniques at least requires that every 1024Byte corrects 24bit, even 72bit now.Correction module comprises coding/decoding module and miscount module, and the encoding and decoding that 72bit BCH correction module comprises and miscount module generally can reach 10-20 ten thousand gate logic, and wherein encoding and decoding logic takies tens thousand of gate logic.Thus the area that takies of correction module or cost also constantly increase, especially multichannel flash controller.
The each channel data of traditional multichannel flash controller is independent, such as adopt SSD (the solid state disk of SATA interface, solid state hard disc) generally adopt 2, 4 or 8 passages, even can adopt 10 passages, each passage independently takies a correction module, although also only can independently take respective coding/decoding module, but also need to share miscount module and (time because only make mistakes, just can call miscount module, and flash memory can not be made mistakes each sector (sector), the probability of makeing mistakes is still lower), therefore correction module just occupies a big chunk of flash controller cost.
In the prior art, the error correction method of current application in multi-channel flash memory controller mainly contains the error correction method based on RS code or BCH code, and RS code generally carries out error correction according to Byte, and BCH code carries out error correction according to bit.But for multi-channel flash memory controller, these two kinds of error correction methods all independently can take correction module because of each passage, and make cost extremely expensive and waste ample resources.
Summary of the invention
Technical matters to be solved by this invention is to provide a kind of error correction method of multi-channel flash memory controller, all independently can take correction module because of each passage in order to solve error correction method of the prior art, and make cost extremely expensive and the problem of waste ample resources.
Another object of the present invention is applied in concrete applied environment above-mentioned design, provides a kind of error correction device and multi-channel flash memory controller of multi-channel flash memory controller, thus ensure realization and the application of the method.
For solving the problems of the technologies described above, embodiments provide a kind of error correction device of multi-channel flash memory controller, described error correction device comprises coding/decoding module and miscount module, described coding/decoding module specifically comprises a combinational logic circuit and the multichannel multiple sequential logical circuit of correspondence, and described coding/decoding module also comprises:
The data of effective for correspondence passage and sequential logic register information, for each channel data validity according to current period, are selected in described combinational logic circuit by MUX;
Load module, for inputting the operation result of described combinational logic circuit in the sequential logic register of the effective passage of described correspondence.
Preferably, when current period only has the data of a passage effective, described MUX is selected in described combinational logic circuit specifically for the direct sequential logic register information by the valid data of this passage and this passage.
Preferably, multichannel data described in current period all effectively time, described MUX specifically for: at current period, the valid data of corresponding first passage and sequential logic register information are selected in described combinational logic circuit; Described coding/decoding module also comprises register, and described register is for latching the valid data of other passages except described first passage.
Preferably, described in current period, multichannel data are all invalid, and multichannel data described in upper one-period all effectively time, described MUX also for:
Successively when each cycle follow-up arrives, the valid data of other passages latched and the sequential logic register of correspondence are selected in described combinational logic circuit.
Preferably, described load module specifically for: at the rising edge of clock or negative edge, the operation result of described combinational logic circuit is inputted in the sequential logic register of the effective passage of described correspondence.
The embodiment of the present invention additionally provides a kind of error correction method of error correction device of multi-channel flash memory controller, described error correction device comprises coding/decoding module and miscount module, described coding/decoding module specifically comprises a combinational logic circuit and the multichannel multiple sequential logical circuit of correspondence, and described method comprises:
According to each channel data validity of current period, the data of effective for correspondence passage and sequential logic register information are selected in described combinational logic circuit;
The operation result of described combinational logic circuit is inputted in the sequential logic register of the effective passage of described correspondence.
Preferably, when current period only has the data of a passage effective, described the data of effective for correspondence passage and sequential logic register information to be selected in described combinational logic circuit, specifically to comprise:
Directly the sequential logic register information of the valid data of this passage and this passage is selected in described combinational logic circuit.
Preferably, multichannel data described in current period all effectively time, described the data of effective for correspondence passage and sequential logic register information to be selected in described combinational logic circuit, specifically to comprise:
At current period, the valid data of corresponding first passage and sequential logic register information are selected in described combinational logic circuit;
Latch the valid data of other passages except described first passage.
Preferably, described in current period, multichannel data are all invalid, and when multichannel data described in upper one-period are all effective, described method also comprises:
Successively when each cycle follow-up arrives, the valid data of other passages latched and the sequential logic register of correspondence are selected in described combinational logic circuit.
Preferably, the described operation result by described combinational logic circuit inputs in the sequential logic register of the effective passage of described correspondence, is specially:
At the rising edge of clock or negative edge, the operation result of described combinational logic circuit is inputted in the sequential logic register of the effective passage of described correspondence.
The embodiment of the present invention additionally provides a kind of multi-channel flash memory controller, comprises aforementioned any one error correction device.
Compared with prior art, the present invention has the following advantages:
In the present embodiment, disclosed error correction device comprises coding/decoding module and miscount module, described coding/decoding module specifically comprises a combinational logic circuit and the multichannel multiple sequential logical circuit of correspondence, this combinational logic circuit is shared in order to realize hyperchannel, described coding/decoding module also comprises: MUX, for each channel data validity according to current period, the data of effective for correspondence passage and sequential logic register information are selected in described combinational logic circuit; Load module, for inputting the operation result of described combinational logic circuit in the sequential logic register of the effective passage of described correspondence.Adopt error correction device or error correction method disclosed in the embodiment of the present invention, can solve in prior art and all independently can take correction module because of each passage, and make cost extremely expensive and the problem of waste ample resources, save resource and saved cost.
Accompanying drawing explanation
In order to be illustrated more clearly in the embodiment of the present invention or technical scheme of the prior art, be briefly described to the accompanying drawing used required in embodiment or description of the prior art below, apparently, accompanying drawing in the following describes is only some embodiments of the present invention, for those of ordinary skill in the art, under the prerequisite not paying creative work, other accompanying drawing can also be obtained according to these accompanying drawings.
Fig. 1 is the structural representation of the error correction device embodiment of a kind of multi-channel flash memory controller of the present invention;
Fig. 2 and Fig. 3 is the schematic diagram of two MUX in the present embodiment;
Fig. 4 is the sequential chart selected when passage 0 is effective in device embodiment;
Fig. 5 is the sequential chart selected when passage 1 is effective in device embodiment;
Fig. 6 be in device embodiment passage 0 and passage 1 effectively time the sequential chart selected;
Fig. 7 is the process flow diagram of the error correction method embodiment of a kind of multi-channel flash memory controller of the present invention.
Embodiment
For enabling above-mentioned purpose of the present invention, feature and advantage become apparent more, and below in conjunction with the drawings and specific embodiments, the present invention is further detailed explanation.
For the BCH algorithm in error correction method, its implementation procedure comprises: coding generates Parity check code (writing NAND Flash synchronously to carry out), generate the search of syndrome Syndrome (reading NANDFlash synchronously to carry out), miscount position polynomial expression and money locates errors position.
For the RS algorithm in error correction method, its implementation procedure comprises: encode and generate Parity check code (writing NAND Flash synchronously to carry out), generate syndrome Syndrome (reading NANDFlash synchronously to carry out), miscount position polynomial expression and improper value polynomial expression, money search locates errors position and Forney algorithm miscount value.
As can be seen from said process, the first two step of these two kinds of algorithms is identical, all carry out reading and writing NAND Flash while, and subsequent step run through a sector (sector) find that there is mistake just call, therefore adopt a coding/decoding module to realize the first two step of these two kinds of algorithms, and adopt miscount module to realize other step.
With reference to figure 1, show the structural representation of the error correction device embodiment of a kind of multi-channel flash memory controller of the present invention, described error correction device can comprise coding/decoding module 110 and miscount module 120, with coding/decoding module of the prior art comprise multiple combinational logic circuit and multiple sequential logical circuit unlike, of the present inventionly focus on described coding/decoding module 110 and specifically can comprise: a combinational logic circuit 111 and the multichannel multiple sequential logical circuit 112 of correspondence, namely be each passage sequential logical circuit 112 or separately independently of described multi-channel flash memory controller, but this multiple channels share combinational logic circuit 111.Described miscount module 120 can the result miscount position polynomial expression of coding/decoding module 110 and/or improper value polynomial expression, and adopt money search to locate errors position, Forney algorithm miscount value can also be adopted, thus the error correcting to multi-channel flash memory can be realized.Because the implementation of described miscount module 120 can be same as the prior art, so will the realization of coding/decoding module 110 be introduced in the embodiment of the present invention.
It should be noted that, the maximum bandwidth of coding/decoding module 110 is at least 2 times of single-channel data bandwidth, and adopt the prerequisite of identical error correction method at each passage under, coding/decoding module 110 disclosed in the present invention could be adopted, thus save considerable resource and reduce costs.Wherein, the account form of maximum bandwidth is: the clock speed of operation is multiplied by parallel figure place.Concrete, when more than 2 times or 2 times that the maximum bandwidth of encoding and decoding mould 110 pieces is the data bandwidth of single-channel flash memory, and when in multi-channel flash memory controller, each passage uses identical error correction method, just the coding/decoding module of two passages can be combined, be namely that the sequential logical circuit of two passages is independent but can shared group combinational logic circuit 111.In like manner, when more than 4 times or 4 times that the maximum bandwidth of coding/decoding module 110 is the data bandwidth of single-channel flash memory, and when in multi-channel flash memory controller, each passage uses identical error correction method, just the coding/decoding module 110 of four passages can be combined, namely the respective sequential logical circuit 112 being four passages is independent, but can share same combinational logic circuit 111.
Be understandable that, channel number in error correction device application multi-channel flash memory controller disclosed in the embodiment of the present invention is different, so the present invention does not limit the channel number of a shared combinational logic circuit, only need apply the multi-channel flash memory controller of error correction device disclosed in the embodiment of the present invention meets above-mentioned condition.
In order to realize said apparatus, with reference to figure 1, described coding/decoding module 110 can also comprise:
The data of effective for correspondence passage and sequential logic register information, for each channel data validity according to current period, are selected in described combinational logic circuit by MUX 113.
Described MUX 113 can according to the data validity of each passage under present clock period, select and need to be selected into the data in combinational logic circuit and sequential logic register information, these data are the valid data of corresponding effectively passage, and this sequential logic register information represents that sequential logic register of corresponding effectively passage.
Because add the sequential logic register of MUX to multichannel data and correspondence in the embodiment of the present invention to select, so can ensure to enter the data in the data of combinational logic circuit or a passage under current period, this makes it possible to realize multi-channel flash memory controller sharing about combinational logic circuit.
Load module 114, for inputting the operation result of described combinational logic circuit in the sequential logic register of the effective passage of described correspondence.
After combinational logic circuit calculates for the data of the effective passage of correspondence and sequential logic register information, the operation result of described combinational logic circuit inputs in the sequential logic register of the effective passage of described correspondence by load module 114 again.
Error correction device disclosed in the embodiment of the present invention and coding/decoding module wherein 110, can be applied in multi-channel flash memory controller, although add MUX and load module, but for the combinational logic circuit of the error correction coding/decoding circuit of a passage, MUX and load module are almost negligible, therefore, it is possible to economize on resources and reduce costs.Such as, for the error correcting system of the BCH code of highest correction 24bit, and under the condition of coding/decoding module 11016bit parallel input data, the coding/decoding module of two passages can combine by the embodiment of the present invention, this array mode than two independently error correction coding/decoding module save the logic (logics more than 10,000) of about 30%; If the coding/decoding module of combination four passages, the logic of saving will be more considerable, therefore adopt the embodiment of the present invention can save a large amount of resources and reduce costs.
Conveniently those skilled in the art can better understand for the present invention and realize, and enumerate the present invention object lesson in actual applications below to describe the present invention in detail.But those skilled in the art also it should be understood that the data of this example are a kind of specific implementation of the embodiment of the present invention, and data wherein can not limit the present invention.
To combine the coding/decoding module of two passages, if data_val0 and data_val1 represents the data validity of the current period of passage 0 and passage 1 respectively, wherein, data_val0 and data_val1 can have correlativity, but assuming that do not consider correlativity between data_val0 and data_val1, also cover the condition of correlativity like this.And data1_d is register, data1_d latches data1 when data_val0 and data_val1 is effective; Adopt R and data to represent the register item after MUX and data item respectively, R0 and R1 is respectively the sequential logic register of passage 0 and passage 1, data0 and data1 is respectively the data of passage 0 and passage 1.It should be noted that, because the data transmission of flash memory has periodically usually, when encoding and decoding bandwidth is more than 2 times or 2 times of single-channel flash memory transmission bandwidth, data_val0 and data_val1 separately can discontinuous two cycles all effective, this is a precondition of embodiment of the present invention application.
MUX in the present embodiment can select two in actual applications, please refer to shown in Fig. 2 and Fig. 3, is the schematic diagram of the MUX of two in the present embodiment.In fig. 2, MUX 1 can select in data0, data1 and data1_d data to be sent in a shared combinational logic circuit according to data_val0 and data_val1, in figure 3, in R0 and R1 sequential logic register information can be selected to be sent in a shared combinational logic circuit according to data_val0 and data_val1.
For this example, when current period only has the data of a passage effective, such as: data_val0 is effective and data_val1 is invalid, described MUX is selected in described combinational logic circuit specifically for the direct sequential logic register information by the valid data of this passage and this passage, namely be by MUX 1, data data0 is selected in combinational logic circuit, and R0 information is selected in combinational logic circuit by MUX 2, and by load module 114, the operation result of combinational logic circuit is input in the sequential logic register R0 of passage 0, concrete, the operation result of combinational logic circuit can be input in the sequential logic register R0 of passage 0 at clock edge (rising edge or negative edge) by load module 114.Shown in figure 4, Fig. 4 be passage 0 effectively time the sequential chart selected.
Again such as, the invalid data_val1 of current period data_val0 is effective, described MUX is selected in described combinational logic circuit specifically for the direct sequential logic register information by the valid data of this passage and this passage, namely be by MUX 1, data data1 is selected in combinational logic circuit, and R1 information is selected in combinational logic circuit by MUX 2, and by load module 114, the operation result of combinational logic circuit is sent in the sequential logic register R1 of passage 1 at clock edge (rising edge or negative edge).Concrete, the operation result of combinational logic circuit can be input in the sequential logic register R0 of passage 0 at clock edge (rising edge or negative edge) by load module 114.Shown in figure 5, Fig. 5 be passage 1 effectively time the sequential chart selected.
In addition, if when the described multichannel data of current period are all effective, such as, current period data_val0 is effective and data_val1 is effective, and described MUX is specifically for being selected in described combinational logic circuit at current period by the valid data of corresponding first passage and sequential logic register information; Namely be first by MUX 1, data data0 is selected in combinational logic circuit, to be selected in combinational logic circuit with R0 information by MUX 2 again, now described coding/decoding module also comprises register data1_d, described register is for latching the valid data of other passages except described first passage, and data1_d is for latching the data data1 of passage 1 in the present example; And by load module 114, the operation result of combinational logic circuit is sent in the sequential logic register R0 of passage 0 at clock edge (rising edge or negative edge).Shown in figure 6, Fig. 6 be passage 0 and passage 1 effectively time the sequential chart selected.
Simultaneously with reference to shown in figure 6, also has a kind of situation, described in current period, multichannel data are all invalid, and multichannel data described in upper one-period all effectively time, described MUX 113 can also be used for: successively when each cycle follow-up arrives, the valid data of other passages latched and the sequential logic register of correspondence are selected in described combinational logic circuit.Such as, current period data_val0 is invalid and data_val1 is invalid, but upper clock period data_val0 and data_val1 is effective, now data data1_d is selected in combinational logic circuit by MUX 1, R1 is selected in combinational logic circuit by MUX 2, and is sent in the sequential logic register R1 of passage 1 at clock edge (rising edge or negative edge) by the operation result of combinational logic circuit by load module 114.
Meanwhile, in actual applications, the embodiment of the invention also discloses a kind of multi-channel flash memory controller comprising above-mentioned error correction device, the flash memory applying this multi-channel flash memory controller can be saved ample resources than flash memory of the prior art and save cost of manufacture.
With reference to figure 7, show the process flow diagram of the error correction method embodiment of the error correction device of a kind of multi-channel flash memory controller of the present invention, described error correction device comprises coding/decoding module and miscount module, described coding/decoding module specifically comprises a combinational logic circuit and the multichannel multiple sequential logical circuit of correspondence, and described method specifically can comprise:
Step 701: according to each channel data validity of current period, the data of effective for correspondence passage and sequential logic register information are selected in described combinational logic circuit.
This step has different implementations according to data validity difference in practical application, when current period only has the data of a passage effective, then the direct sequential logic register information by the valid data of this passage and this passage is selected in described combinational logic circuit.
And multichannel data described in current period all effectively time, then when the valid data of corresponding first passage and sequential logic register information are selected in described combinational logic circuit by current period, also need the valid data latching other passages except described first passage in addition.
And multichannel data are all invalid described in current period, and in all effective situation of multichannel data described in upper one-period, then this step needs, successively when each cycle follow-up arrives, the valid data of other passages latched and the sequential logic register of correspondence to be selected in described combinational logic circuit.
Step 702: the operation result of described combinational logic circuit is inputted in the sequential logic register of the effective passage of described correspondence.
At the rising edge of clock or negative edge, the operation result of described combinational logic circuit is inputted in the sequential logic register of the effective passage of described correspondence.
Adopt the error correction method of multi-channel flash memory controller disclosed in the embodiment of the present invention, a large amount of resources can be saved and cost-saving.
It should be noted that, for aforesaid embodiment of the method, in order to simple description, therefore it is all expressed as a series of combination of actions, but those skilled in the art should know, the present invention is not by the restriction of described sequence of movement, because according to the present invention, some step can adopt other orders or carry out simultaneously.Secondly, those skilled in the art also should know, the embodiment described in instructions all belongs to preferred embodiment, and involved action and module might not be that the present invention is necessary.
It should be noted that, each embodiment in this instructions all adopts the mode of going forward one by one to describe, and what each embodiment stressed is the difference with other embodiments, between each embodiment identical similar part mutually see.For method class embodiment, due to itself and device embodiment basic simlarity, so description is fairly simple, relevant part illustrates see the part of device embodiment.
It should be noted that, term " comprises ", " comprising " or its any other variant are intended to contain comprising of nonexcludability, thus make to comprise the process of a series of key element, method, article or equipment and not only comprise those key elements, but also comprise other key elements clearly do not listed, or also comprise by the intrinsic key element of this process, method, article or equipment.When not more restrictions, the key element limited by statement " comprising ... ", and be not precluded within process, method, article or the equipment comprising described key element and also there is other identical element.
Above the error correction device of multi-channel flash memory controller provided by the present invention, method and multi-channel flash memory controller are described in detail, apply specific case herein to set forth principle of the present invention and embodiment, the explanation of above embodiment just understands method of the present invention and core concept thereof for helping; Meanwhile, for one of ordinary skill in the art, according to thought of the present invention, all will change in specific embodiments and applications, in sum, this description should not be construed as limitation of the present invention.
Claims (9)
1. the error correction device of a multi-channel flash memory controller, described error correction device comprises coding/decoding module and miscount module, it is characterized in that, described coding/decoding module specifically comprises a combinational logic circuit and the multichannel multiple sequential logical circuit of correspondence, and described coding/decoding module also comprises:
The data of effective for correspondence passage and sequential logic register information, for each channel data validity according to current period, are selected in described combinational logic circuit by MUX; Multichannel data described in current period all effectively time, described MUX specifically for: at current period, the valid data of corresponding first passage and sequential logic register information are selected in described combinational logic circuit; Described coding/decoding module also comprises register, and described register is for latching the valid data of other passages except described first passage;
Load module, for inputting the operation result of described combinational logic circuit in the sequential logic register of the effective passage of described correspondence.
2. device as claimed in claim 1, it is characterized in that, when current period only has the data of a passage effective, described MUX is selected in described combinational logic circuit specifically for the direct sequential logic register information by the valid data of this passage and this passage.
3. device as claimed in claim 1, it is characterized in that, described in current period, multichannel data are all invalid, and multichannel data described in upper one-period all effectively time, described MUX also for:
Successively when each cycle follow-up arrives, the valid data of other passages latched and the sequential logic register of correspondence are selected in described combinational logic circuit.
4. device as claimed in claim 1, is characterized in that, described load module specifically for: at the rising edge of clock or negative edge, the operation result of described combinational logic circuit is inputted in the sequential logic register of the effective passage of described correspondence.
5. the error correction method of the error correction device of a multi-channel flash memory controller, described error correction device comprises coding/decoding module and miscount module, it is characterized in that, described coding/decoding module specifically comprises a combinational logic circuit and the multichannel multiple sequential logical circuit of correspondence, and described method comprises:
According to each channel data validity of current period, the data of effective for correspondence passage and sequential logic register information are selected in described combinational logic circuit; When multichannel data described in current period are all effective, described the data of effective for correspondence passage and sequential logic register information to be selected in described combinational logic circuit, specifically to comprise: at current period, the valid data of corresponding first passage and sequential logic register information are selected in described combinational logic circuit; Latch the valid data of other passages except described first passage;
The operation result of described combinational logic circuit is inputted in the sequential logic register of the effective passage of described correspondence.
6. method as claimed in claim 5, is characterized in that, when current period only has the data of a passage effective, describedly the data of effective for correspondence passage and sequential logic register information to be selected in described combinational logic circuit, specifically to comprise:
Directly the sequential logic register information of the valid data of this passage and this passage is selected in described combinational logic circuit.
7. method as claimed in claim 5, it is characterized in that, described in current period, multichannel data are all invalid, and when multichannel data described in upper one-period are all effective, described method also comprises:
Successively when each cycle follow-up arrives, the valid data of other passages latched and the sequential logic register of correspondence are selected in described combinational logic circuit.
8. method as claimed in claim 5, it is characterized in that, the described operation result by described combinational logic circuit inputs in the sequential logic register of the effective passage of described correspondence, is specially:
At the rising edge of clock or negative edge, the operation result of described combinational logic circuit is inputted in the sequential logic register of the effective passage of described correspondence.
9. a multi-channel flash memory controller, is characterized in that, comprises the error correction device as described in any one of claim 1-4.
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| CN201010619730.1A CN102543209B (en) | 2010-12-31 | 2010-12-31 | The error correction device of multi-channel flash memory controller, method and multi-channel flash memory controller |
| HK12112011.6A HK1171283A1 (en) | 2010-12-31 | 2012-11-23 | Multi-channel flash memory controller, and error correction device and method thereof |
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| CN103824598B (en) * | 2012-11-19 | 2017-02-22 | 联芸科技（杭州）有限公司 | Error checking and correcting method and error checking and correcting circuit |
| CN104298572B (en) * | 2013-07-19 | 2018-01-26 | 杨凤兰 | A kind of error correction method, error correction device, master controller and error correction system |
| CN110968449A (en) * | 2018-09-28 | 2020-04-07 | 方一信息科技（上海）有限公司 | BCH ECC error correction resource sharing system and method for multichannel flash memory controller |
| CN111078602B (en) * | 2019-12-27 | 2021-03-19 | 深圳大普微电子科技有限公司 | Flash memory master control chip, control method and test method thereof, and storage device |
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| HK1171283A1 (en) | 2013-03-22 |
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