CN102508636B - Program stream control method for vector processor and system - Google Patents
Program stream control method for vector processor and system Download PDFInfo
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- CN102508636B CN102508636B CN2011103404094A CN201110340409A CN102508636B CN 102508636 B CN102508636 B CN 102508636B CN 2011103404094 A CN2011103404094 A CN 2011103404094A CN 201110340409 A CN201110340409 A CN 201110340409A CN 102508636 B CN102508636 B CN 102508636B
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Abstract
The invention discloses a program stream control method for a vector processor and a system. The method includes steps of outputting a vector data processing state when a vector data processing unit executes a vector data operation instruction outputted by a fetch unit; acquiring a the vector data processing state by the aid of a program stream control unit; generating a program stream changing mark according to the vector data processing state; starting to sequentially obtain instructions from program stream changing addresses by the aid of the fetch unit according to the program steam changing mark; and outputting acquired instructions to the vector data processing unit. The system comprises the fetch unit, the vector data processing unit and the program stream control unit, the vector data processing unit consists of a state generating unit used for generating the vector data processing state, and an output end of the state generating unit is connected with the program stream control unit. The program stream control method for the vector process and the system have the advantages that a program stream can be changed during processing, vector data processing time is saved, data processing volume is reduced, and data processing efficiency is high.
Description
Technical field
The present invention relates to field of microprocessors, be specifically related to a kind of control method of the program flow for vector processor and system.
Background technology
The application algorithms such as radio communication, image/video processing comprise a large amount of vector operations, such as the addition of carrying out 16 pairs of data etc.Vector processor is a kind of processor of support vector data manipulation, by a vector instruction of vector processor, just can carry out the add operation of above-mentioned 16 pairs of data.In prior art, the program flow of vector processor is controlled general by scalar program current control (comprise branch, redirect or the invocation of procedure/return etc.) realization.But the program flow control method of this scalar program current control is difficult to process complicated algorithm.The algorithm of searching character in vector data of for example take is example, during a certain Match of elemental composition searching character in vector data, just can stop search.Due to the treatment state of scalar program method of flow control and each vector element, without any associated, this program flow control method can not stop search after searching character, but need to compare after complete and just can stop search all vector datas.
As shown in Figure 1, the program flow control system of prior art comprises fetching unit, vector data processing unit and program flow control module, and the fetching unit is connected with vector data processing unit, program flow control module respectively.The fetching unit is for obtaining the program flow address of program flow control module output, and the vector data operational order is provided, provides the program flow steering order for the program flow control module for the vector data processing unit; The arithmetic element that one or more can the execute vector instruction, the vector data operational order provided for carrying out the fetching unit are provided the vector data processing unit; The program flow control module carries out decoding to the program flow steering order of carrying out, and generating routine flow control flag and program flow address also send to the fetching unit.But, independent each other during due to each arithmetic element execute vector data manipulation instruction of vector data processing unit, for example, when carrying out above-mentioned searching character, must be after all arithmetic element computings be complete, the program flow control module just can be carried out new program flow, the scalar program current control can not effectively be processed the algorithm relevant with the vector data treatment state, can not in processing procedure, flow by reprogramming, have the problem that the vector data processing time is long, the deal with data amount is large, data-handling efficiency is low.
Summary of the invention
The technical problem to be solved in the present invention is for the problems referred to above, provide a kind of can be in processing procedure reprogramming stream, save the vector data processing time, reduce the deal with data amount, the control method of the program flow for vector processor and system that data-handling efficiency is high.
In order to solve the problems of the technologies described above, the technical solution used in the present invention is: a kind of control method of the program flow for vector processor, and implementation step is as follows: the vector data processing unit of vector processor is output vector data treatment state when executing any vector instruction sequence; The program flow control module of vector processor obtains described vector data treatment state, according to described vector data treatment state generator program stream, changes address and program flow change sign; The fetching unit of vector processor changes sign according to program flow and starts sequentially to obtain instruction from program flow change address, and the instruction got is exported to the vector data processing unit.
Further improvement as the present invention for the program flow control method of vector processor: the detailed step that described program flow control module changes address and program flow change sign according to vector data treatment state generator program stream comprises: at first current program flow steering order is carried out to decoding, the triggering state of the present procedure flow control instructions that described vector data treatment state and described decoding are obtained compares, if mate program flow control module generator program stream changes address and program flow changes sign.
The present invention also provides a kind of control system of the program flow for vector processor, comprise the fetching unit, vector data processing unit and program flow control module, described vector data processing unit comprises for generating the state generation unit of vector data treatment state, the output terminal of described state generation unit is connected with described program flow control module, described state generation unit when the vector data processing unit executes any vector instruction sequence output vector data treatment state to the program flow control module, described program flow control module changes address and program flow according to described vector data treatment state generator program stream and changes and indicate and export the fetching unit to, described fetching unit changes sign according to described program flow and starts sequentially to obtain instruction from program flow change address, and the instruction got is exported to the vector data processing unit.
Further improvement as the present invention for the program flow control system of vector processor: described program flow control module comprises for the program flow steering order being carried out to the program flow steering order processing unit of decoding, for change in real time the Vector Processing state processing unit of address and program flow change sign according to decode results generating routine stream, described program flow steering order processing unit is connected with the fetching unit, the input end of described Vector Processing state processing unit respectively with program flow steering order processing unit, the state generation unit is connected, the output terminal of described Vector Processing state processing unit is connected with the fetching unit, the triggering state of the present procedure flow control instructions that the vector data treatment state that described Vector Processing state processing unit is exported the state generation unit and the decoding of described program flow steering order processing unit obtain compares, if coupling described program flow control module generator program stream change address and program flow and change and indicate and export the fetching unit to.
The present invention has following advantage for the program flow control method of vector processor: the real-time output vector data of vector data processing unit of the present invention treatment state; The program flow control module obtains described vector data treatment state, change sign according to described vector data treatment state generator program stream, the fetching unit changes sign according to program flow, change address from program flow and start sequentially to obtain instruction, and the instruction got is exported to the vector data processing unit, therefore the present invention can be in processing procedure reprogramming stream, there is the vector data processing time of saving, reduce the deal with data amount, data-handling efficiency is high.
The present invention is used for the program flow control system of vector processor owing to having the structure corresponding for the program flow control method of vector processor with the present invention, therefore also should have advantages of that the present invention is corresponding for the program flow control method of vector processor.
The accompanying drawing explanation
The program flow control method schematic diagram that Fig. 1 is prior art.
The framed structure schematic diagram that Fig. 2 is the embodiment of the present invention.
Fig. 3 carries out a vector data treatment state schematic diagram of BRVNZ instruction in the embodiment of the present invention.
Fig. 4 carries out another vector data treatment state schematic diagram of BRVNZ instruction in the embodiment of the present invention.
Fig. 5 carries out a vector data treatment state schematic diagram of BRVZ instruction in the embodiment of the present invention.
Fig. 6 carries out another vector data treatment state schematic diagram of BRVZ instruction in the embodiment of the present invention.
Marginal data: 1, fetching unit; 2, vector data processing unit; 21, state generation unit; 3, program flow control module; 31, program flow steering order processing unit; 32, Vector Processing state processing unit.
Embodiment
As shown in Figure 2, the present embodiment is as follows for the implementation step of the program flow control method of vector processor: the vector data processing unit of vector processor is output vector data treatment state when executing any vector instruction sequence; The program flow control module of vector processor obtains the vector data treatment state, according to vector data treatment state generator program stream, changes address and program flow change sign; The fetching unit of vector processor changes sign according to program flow and starts sequentially to obtain instruction from program flow change address, and the instruction got is exported to the vector data processing unit.
In the present embodiment, the detailed step that the program flow control module changes address and program flow change sign according to vector data treatment state generator program stream comprises: at first current program flow steering order is carried out to decoding, the triggering state of the present procedure flow control instructions that vector data treatment state and decoding are obtained compares, if mate program flow control module generator program stream changes address and program flow changes sign.
As shown in Figure 2, the present embodiment comprises fetching unit 1 for the program flow control system of vector processor, vector data processing unit 2 and program flow control module 3, vector data processing unit 2 comprises for generating the state generation unit 21 of vector data treatment state, the output terminal of state generation unit 21 is connected with program flow control module 3, when state generation unit 21 executes any vector instruction sequence at vector data processing unit 2, output vector data treatment state is to program flow control module 3, program flow control module 3 changes address and program flow according to vector data treatment state generator program stream and changes and indicate and export fetching unit 1 to, fetching unit 1 changes sign according to program flow and starts sequentially to obtain instruction from program flow change address, and the instruction got is exported to vector data processing unit 2.When the complete a certain vector instruction sequence of vector data processing unit 2, state generation unit 21 can produce the vector data treatment state, 3 of program flow control modules carry out decoding to the program flow steering order, generating routine flow control instructions type information and program flow address, then produce according to program flow steering order type information and vector data state the information whether sign carries out the program flow change, program flow address and program flow that reception program current control unit 3 is drawn together in fetching unit 1 change information, if program flow changes sign and changes, from program flow, change address and start sequentially to obtain instruction, and the instruction got is exported to vector data processing unit 2.
In the present embodiment, program flow control module 3 comprises for the program flow steering order being carried out to the program flow steering order processing unit 31 of decoding, for change in real time the Vector Processing state processing unit 32 of address and program flow change sign according to decode results generating routine stream, program flow steering order processing unit 31 is connected with fetching unit 1, the input end of Vector Processing state processing unit 32 respectively with program flow steering order processing unit 31, state generation unit 21 is connected, the output terminal of Vector Processing state processing unit 32 is connected with fetching unit 1, the triggering state of the present procedure flow control instructions that the vector data treatment state that Vector Processing state processing unit 32 is exported state generation unit 21 and 31 decodings of program flow steering order processing unit obtain compares, if mate program flow control module 3 generator programs streams change addresses and program flow changes and indicate and export fetching unit 1 to.In the present embodiment, program flow changes sign and realizes control program stream by generating effective status and disarmed state, if program flow changes sign effectively, fetching unit 1 changes address switchover to new program flow according to program flow, thereby realize the real-time control of program flow, reduce the deal with data of microprocessor, the efficiency of raising processor.
The vector data operational order of below take illustrates the program flow controlling mechanism of the present embodiment as the BRVNZ instruction.The semanteme of BRVNZ instruction is that the triggering state is that branch occurs in 1 o'clock entirely, branch occurs when the vector data treatment state is 1 entirely and carry out redirect, otherwise redirect does not occur.As shown in Figure 3, vector data processing unit 2 is in carrying out the BRVNZ instruction process, all zone bits in the vector data treatment state are all 1, because the triggering state is 1 entirely, vector data treatment state and triggering state are complementary, the program flow of Vector Processing state processing unit 32 outputs changes sign effectively, fetching unit 1 has obtained before cancelling and untapped vector data operational order still, and changes address according to the program flow of program flow steering order processing unit 31 outputs and carry out new program flow.As shown in Figure 4, all zone bits in the vector data treatment state are not all 1, wherein the 5th is 0, vector data treatment state and triggering state do not mate, it is invalid that the program flow of Vector Processing state processing unit 32 output changes sign, and fetching unit 1 continues to carry out and obtained and untapped vector data operational order still.
The vector data operational order of below take illustrates the program flow controlling mechanism of the present embodiment as the BRVZ instruction.The semanteme of BRVZ instruction is that the triggering state is that branch occurs in 0 o'clock entirely, branch occurs when the vector data treatment state is 0 entirely and carry out redirect, otherwise redirect does not occur.As shown in Figure 5, vector data processing unit 2 is in carrying out the BRVZ instruction process, all zone bits in the vector data treatment state are all 0, because the triggering state is 0 entirely, vector data treatment state and triggering state are complementary, the program flow of Vector Processing state processing unit 32 outputs changes sign effectively, fetching unit 1 has obtained before cancelling and untapped vector data operational order still, and changes address according to the program flow of program flow steering order processing unit 31 outputs and carry out new program flow.As shown in Figure 6, all zone bits in the vector data treatment state are not all 0, wherein the 4th is 1, vector data treatment state and triggering state do not mate, it is invalid that the program flow of Vector Processing state processing unit 32 output changes sign, and fetching unit 1 continues to carry out and obtained and untapped vector data operational order still.
The above is only the preferred embodiment of the present invention, and protection scope of the present invention also not only is confined to above-described embodiment, and all technical schemes belonged under thinking of the present invention all belong to protection scope of the present invention.It should be pointed out that for those skilled in the art, some improvements and modifications without departing from the principles of the present invention, these improvements and modifications also should be considered as protection scope of the present invention.
Claims (2)
1. the control method of the program flow for vector processor, it is characterized in that implementation step is as follows: the vector data processing unit of vector processor is output vector data treatment state when executing any vector instruction sequence; The program flow control module of vector processor obtains described vector data treatment state, according to described vector data treatment state generator program stream, changes address and program flow change sign; The fetching unit of vector processor changes sign according to program flow and starts sequentially to obtain instruction from program flow change address, and the instruction got is exported to the vector data processing unit; The detailed step that described program flow control module changes address and program flow change sign according to vector data treatment state generator program stream comprises: at first current program flow steering order is carried out to decoding, the triggering state of the present procedure flow control instructions that described vector data treatment state and described decoding are obtained compares, if mate program flow control module generator program stream changes address and program flow changes sign.
2. the control system of the program flow for vector processor, comprise fetching unit (1), vector data processing unit (2) and program flow control module (3), it is characterized in that: described vector data processing unit (2) comprises for generating the state generation unit (21) of vector data treatment state, the output terminal of described state generation unit (21) is connected with described program flow control module (3), when described state generation unit (21) executes any vector instruction sequence at vector data processing unit (2), output vector data treatment state is to program flow control module (3), described program flow control module (3) changes address and program flow according to described vector data treatment state generator program stream and changes and indicate and export fetching unit (1) to, described fetching unit (1) changes sign according to described program flow and starts sequentially to obtain instruction from program flow change address, and the instruction got is exported to vector data processing unit (2), described program flow control module (3) comprises for the program flow steering order being carried out to the program flow steering order processing unit (31) of decoding, for change in real time the Vector Processing state processing unit (32) of address and program flow change sign according to decode results generating routine stream, described program flow steering order processing unit (31) is connected with fetching unit (1), the input end of described Vector Processing state processing unit (32) respectively with program flow steering order processing unit (31), state generation unit (21) is connected, the output terminal of described Vector Processing state processing unit (32) is connected with fetching unit (1), the triggering state of the present procedure flow control instructions that the vector data treatment state that described Vector Processing state processing unit (32) is exported state generation unit (21) and described program flow steering order processing unit (31) decoding obtain compares, if coupling described program flow control module (3) generator program stream change address and program flow and change and indicate and export fetching unit (1) to.
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| EP0333365A2 (en) * | 1988-03-18 | 1989-09-20 | Digital Equipment Corporation | Method and apparatus for handling asynchronous memory management exceptions by a vector processor |
| US5418973A (en) * | 1992-06-22 | 1995-05-23 | Digital Equipment Corporation | Digital computer system with cache controller coordinating both vector and scalar operations |
| CN1973260A (en) * | 2004-03-31 | 2007-05-30 | 艾色拉公司 | Apparatus and method for asymmetric dual path processing |
| CN101986263A (en) * | 2010-11-25 | 2011-03-16 | 中国人民解放军国防科学技术大学 | Method and microprocessor for supporting single instruction stream and multi-instruction stream dynamic switching execution |
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Patent Citations (4)
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|---|---|---|---|---|
| EP0333365A2 (en) * | 1988-03-18 | 1989-09-20 | Digital Equipment Corporation | Method and apparatus for handling asynchronous memory management exceptions by a vector processor |
| US5418973A (en) * | 1992-06-22 | 1995-05-23 | Digital Equipment Corporation | Digital computer system with cache controller coordinating both vector and scalar operations |
| CN1973260A (en) * | 2004-03-31 | 2007-05-30 | 艾色拉公司 | Apparatus and method for asymmetric dual path processing |
| CN101986263A (en) * | 2010-11-25 | 2011-03-16 | 中国人民解放军国防科学技术大学 | Method and microprocessor for supporting single instruction stream and multi-instruction stream dynamic switching execution |
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