CN102495770B - Method and system for computer memory error analysis - Google Patents
Method and system for computer memory error analysis Download PDFInfo
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- CN102495770B CN102495770B CN201110377814.3A CN201110377814A CN102495770B CN 102495770 B CN102495770 B CN 102495770B CN 201110377814 A CN201110377814 A CN 201110377814A CN 102495770 B CN102495770 B CN 102495770B
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Abstract
The invention discloses a method for computer memory error analysis. The method comprises the steps of: identifying the model number information of a switching element, which is connected with the current CPU (Central Processing Unit) and at least one other CPU, and the base address information of a system management bus (SMBus); switching from the current CPU to another CPU according to the identified model number information of the switching element and the base address information of the SMBus; and acquiring the SPD (Serial Presence Detect) information of a memory connected with the another CPU, and displaying through a display interface so as to carry out memory error analysis. Correspondingly, the invention also discloses a system for computer memory error analysis. According to the invention, the memory error analysis speed is greatly increased, the detection speed of engineers is increased and the device can be used easily by non-professional BIOS (Basic Input Output System) engineers.
Description
Technical field
The present invention relates to the technology about the computer motherboard memory module, relate in particular to a kind of method for computer memory error analysis and a kind of system for computer memory error analysis.
Background technology
In the development and application of active computer mainboard, the significant components that interior nonresident portion goes wrong often.After going wrong, the technician need to go analyzing failure cause debugging to eliminate fault.Yet, lack at present the integrated software of failure analysis memory a kind of simple to operate, with strong points (internal memory debug).
In addition, existing memory test instrument is mainly for example, towards the performance of test memory and sequential (RST instrument, the exploitation of U.S. Ultra-X company), make existing memory test software be difficult to carry out easily and directly failure analysis memory, and often need the multiple types of tools collocation just may make the demonstration of final debug, reduce the speed that the slip-stick artist analyzes memory failure and eliminates.And such testing software interface when carrying out failure analysis memory is friendly not, compatible poor, less to new chipset support, after changing a platform, often can't reading out data.
Related software about the failure analysis memory of Basic Input or Output System (BIOS) (Basic Input Output System, BIOS) in existing integration tool is less, and also is not specifically designed to the failure analysis memory software in performance history at present.Related software about the failure analysis memory of BIOS in existing integration tool comprises IO, the RU instrument, they can read memory SPD (Serial Presence Detect) information---one group of configuration information about memory modules, yet these instruments that can read SPD information need to manually type in some professional codes when often the switching internal memory reads on the mainboard of many CPU, and this mode affects the speed of failure analysis memory very much; And key in so professional code and need BIOS expert engineer could use these softwares to go to realize the function of some failure analysis memories, this has proposed very high requirement to the slip-stick artist, thereby has brought great inconvenience to manufacturer and those of ordinary skill.
For the problem existed in above-mentioned correlation technique, effective solution is not yet proposed at present.
Summary of the invention
For the problem in correlation technique, the present invention proposes a kind of method for computer memory error analysis, can increase the speed to computer memory error analysis, thereby greatly improves the speed that the slip-stick artist detects.
Technical scheme of the present invention is achieved in that
A kind of method for computer memory error analysis, the method comprises:
Type information and the System Management Bus SMBus base address information of the exchange component that identification is connected with current C PU and is connected with at least one other CPU;
Be switched to another CPU according to type information and the SMBus base address information of the exchange component of identifying from current C PU;
Obtain the SPD information of the internal memory be connected with described another CPU and show in order to carry out failure analysis memory by display interface.
In optional embodiment, described method can also comprise: read the storage component part information in the Desktop Management Interface information of multichannel memory and show in order to carry out failure analysis memory by display interface.
In optional embodiment, described method can also comprise: read the performance information of the internal memory in described computing machine and show in order to carry out failure analysis memory by display interface.
In optional embodiment, described method also comprises: the performance information of described internal memory comprises one of following or combination in any: the time sequence parameter of interior presence bit information, memory size, internal memory reading rate and internal memory.
In optional embodiment, described method also comprises: time sequence parameter and/or the reading rate of revising described internal memory.
In optional embodiment, under described method DOS system, realize.
In another aspect of this invention, the invention allows for a kind of system for computer memory error analysis, described system comprises:
SPD Card read/write module, type information and the System Management Bus SMBus base address information of the exchange component that is connected with current C PU and is connected with at least one other CPU for identification;
Be switched to another CPU according to type information and the SMBus base address information of the exchange component of identifying from current C PU;
Obtain the SPD information of the internal memory be connected with described another CPU and show in order to carry out failure analysis memory by display interface.
In optional embodiment, for the system of computer memory error analysis, also comprise:
The Desktop Management Interface information reading module, for the storage component part information of the Desktop Management Interface information that reads multichannel memory and show in order to carry out failure analysis memory by display interface.
In optional embodiment, described system also comprises: the internal memory performance information reading module, and for the performance information of the internal memory that reads described computing machine and show in order to carry out failure analysis memory by display interface.
In optional embodiment, the performance information of described internal memory comprises one of following or combination in any: the time sequence parameter of interior presence bit information, memory size, internal memory reading rate and internal memory.
In optional embodiment, described system also comprises:
The performance information modified module, for time sequence parameter and/or the reading rate of revising described internal memory.
In optional embodiment, the described system for computer memory error analysis is worked under the DOS system.
The SPD information of the internal memory that the present invention can be connected under the CPU from thereby current C PU switches other CPU acquisitions and switching for the automatic realization of the mainboard of many CPU, can greatly increase the speed of failure analysis memory like this, greatly improve the speed that the slip-stick artist detects, even and also easily use of non-BIOS expert engineer.
The accompanying drawing explanation
Fig. 1 is according to an embodiment of the invention for the method for computer memory error analysis;
Fig. 2 is according to another embodiment of the present invention for the system of computer memory error analysis.
Embodiment
Below in conjunction with accompanying drawing, the present invention is described in further detail.
As shown in Figure 1, the method for the computer memory error analysis of an alternate embodiment of the present invention comprises:
S101, type information and the System Management Bus SMBus base address information of the exchange component that identification is connected with current C PU and is connected with at least one other CPU.
S102, be switched to another CPU according to type information and the SMBus base address information of the exchange component of identifying from current C PU.
Particularly, in the situation that there are many CPU in computing machine, must there be one or more entity exchange components (Switch) to do switching, thereby obtain the information of the associated internal memory equipment on different CPU.The instrument that reads memory SPD information in prior art will realize that two CPU switchings in many CPU must carry out complicated code successively, and the Switch chip that for example BIOS expert engineer need to be based on different model and the SMBus chip of different model are realized the switching from a CPU to another CPU according to the professional code of the manual input of existing standard standard.
In embodiments of the present invention, can automatically realize the switching from current C PU to another CPU according to aforementioned S101 and S102 step computing machine to the Switch chip of any model and the SMBus chip of any model.
The SMBus chip of Switch PCA9545 chip and Intel Company of take is example, and the method for the embodiment of the present invention completes switching and comprises the following steps:
1, computer system is according to the type information of the exchange component of identification and the job specification that SMBus base address information is determined SMBus;
2, computer system is carried out following operation according to described definite SMBus job specification:
First clear mode bit, offset address 00h reads currency in place, then inserts this address;
The value of at offset address 03h place, filling out the CPU that need to be switched to, for example 01 representative is switched to CPU1, and 02 representative is switched to CPU2;
At the Slave Address of the value of the filling out swtich of offset address 04h place, as E6h;
Fill out 44h at offset address 02h place;
Obtain the value of offset address 00h, if the value got is 42h, computer system is carried out switching and is switched to the CPU according to aforementioned offset address 03h appointment from current C PU, and the information of transmission handover success is to computer interface; If the value got is 44h, to switch unsuccessfully, computer system sends the unsuccessful information of switching to computer interface.
The operation that has been more than the execution of switching is only the example explanation, and when the Switch chip for other models and SMBus chip, computer system can realize the switching from current C PU to another CPU to the requirement of switching according to the chip of these two models.
S103, obtain the SPD information of the internal memory be connected with described another CPU and show in order to carry out failure analysis memory by display interface.
In optional embodiment of the present invention, the method for computer memory error analysis also comprises:
Read the storage component part information (Memory Device information) in the Desktop Management Interface information (Desktop management interface, DMI) of multichannel memory and show in order to carry out failure analysis memory by display interface.
Reading of DMI information need to meet SMBIOS standard (System Management BIOS Reference Specification, system management BIOS is with reference to standard), the mode that specifically reads DMI has the set form definition in the SMBIOS standard, no longer carefully states here.In embodiments of the present invention, unlike existing software, read all DMI information, only reading the wherein Type 17 defined in the SMBIOS standard is Memory Device information.Can improve like this speed of obtaining DMI information and simplify the workload to failure analysis memory.
In optional embodiment of the present invention, the method for computer memory error analysis also comprises: read the performance information of the internal memory in described computing machine and show in order to carry out failure analysis memory by display interface.The performance information of described internal memory can comprise one of following or combination in any: the time sequence parameter of interior presence bit information, memory size, internal memory reading rate and internal memory.In optional embodiment, method of the present invention also comprises: time sequence parameter and/or the reading rate of revising described internal memory.
In optional embodiment of the present invention, computer system is that SPD information reads, the DMI information of multichannel memory reads and reads and formulate respectively special display interface and show with internal memory performance information.When by display interface or keyboard shortcut is set receives while reading the memory SPD information command, computer system can automatically realize reading the SPD information of the internal memory under current C PU and/or be switched to other CPU and read the SPD information of the internal memory this CPU from current C PU.
In optional embodiment, due to the DOS system of using USB interface to be easy to enter computing machine, therefore the method for computer memory error analysis of the present invention can be by realizing under the DOS system.Certainly according to the needs of realizing, also can under other operating systems of computing machine, realize.
As shown in Figure 2, the embodiment of the invention also discloses a kind of system for computer memory error analysis, described system comprises:
SPD Card read/write module 10, type information and the System Management Bus SMBus base address information of the exchange component that is connected with current C PU and is connected with at least one other CPU for identification;
Be switched to another CPU according to type information and the SMBus base address information of the exchange component of identifying from current C PU;
Obtain the SPD information of the internal memory be connected with described another CPU and show in order to carry out failure analysis memory by display interface.In one embodiment, computer system is that SPD Card read/write module 10 is provided with special SPD information display interface, and SPD Card read/write module is crossed the SPD information display interface by the SPD information exchange read and shown.
Alternatively, SPD Card read/write module 10 is also for when receiving the reading information transmitted by the SPD information display interface, and SPD Card read/write module, according to aforementioned workflow work, is taken out the SPD information of the internal memory under corresponding CPU.For example, by the keyboard combination key, select the SPD information in the SPD information display interface to read key, trigger reading of SPD information, SPD Card read/write module can according to this SPD reading information obtain the SPD information of the internal memory under current C PU or the basis selected the user on be switched to the CPU of user's expectation and obtain the SPD information of the internal memory this CPU from current C PU according to this SPD reading information.
Alternatively, the system for failure analysis memory of the embodiment of the present invention also comprises Desktop Management Interface information reading module 20, for the storage component part information of the Desktop Management Interface information that reads multichannel memory and show in order to carry out failure analysis memory by display interface.
Alternatively, the system for failure analysis memory of the embodiment of the present invention also comprises: internal memory performance information reading module 30, and for the performance information of the internal memory that reads described computing machine and show in order to carry out failure analysis memory by display interface.Wherein, the performance information of described internal memory can comprise one of following or combination in any: the time sequence parameter of interior presence bit information, memory size, internal memory reading rate and internal memory.
Alternatively, the system for failure analysis memory of the embodiment of the present invention also comprises: the performance information modified module, and for time sequence parameter and/or the reading rate of revising described internal memory.
As a kind of embodiment, the system for failure analysis memory of the embodiment of the present invention can be worked under the DOS system.The active computer mainboard all provides USB interface, uses the USB flash disk of USB interface to be easy to enter the DOS system, can greatly conveniently carry out failure analysis memory.Certainly, the trouble analysis system of the embodiment of the present invention also can be chosen in (for example Lunix operating system) work under other operating system according to the actual needs.
The method and system for failure analysis memory of the embodiment of the present invention is owing to proposing from BIOS exploitation angle, having simplified the debug stage does not need the performance test function of too much paying close attention to, only build the basic module for fault analysis, therefore can greatly increase the speed of failure analysis memory, greatly improve the speed that the slip-stick artist detects.In addition, friendly not for existing testing software median surface, to Switch chip and the SMBus chip poor compatibility of different model, and to the problem of new chipset, the failure analysis memory method and system of the embodiment of the present invention can be on the mainboard of many CPU easily CPU switching to obtain corresponding memory SPD information, even non-BIOS expert engineer also easily uses.
The foregoing is only preferred embodiment of the present invention, in order to limit the present invention, within the spirit and principles in the present invention not all, any modification of doing, be equal to replacement, improvement etc., within all should being included in protection scope of the present invention.
Claims (10)
1. the method for computer memory error analysis is characterized in that:
Type information and the System Management Bus SMBus base address information of the exchange component that identification is connected with current C PU and is connected with at least one other CPU;
Be switched to another CPU according to type information and the System Management Bus SMBus base address information of the exchange component of identifying from current C PU;
Obtain the SPD information of the internal memory be connected with described another CPU and show in order to carry out failure analysis memory by display interface.
2. method according to claim 1, is characterized in that, described method also comprises:
Read the storage component part information in the Desktop Management Interface information of multichannel memory and show in order to carry out failure analysis memory by display interface; And/or,
Read the performance information of the internal memory in described computing machine and show in order to carry out failure analysis memory by display interface.
3. method according to claim 2, is characterized in that, described method also comprises:
The performance information of described internal memory comprises one of following or combination in any: the time sequence parameter of interior presence bit information, memory size, internal memory reading rate and internal memory.
4. method according to claim 3, is characterized in that, described method also comprises:
Revise time sequence parameter and/or the reading rate of described internal memory.
5. according to the described method of claim 1 to 4 any one, it is characterized in that: under described method DOS system, realize.
6. the system for computer memory error analysis, described system comprises:
SPD Card read/write module, type information and the System Management Bus SMBus base address information of the exchange component that is connected with current C PU and is connected with at least one other CPU for identification;
Be switched to another CPU according to type information and the System Management Bus SMBus base address information of the exchange component of identifying from current C PU;
Obtain the SPD information of the internal memory be connected with described another CPU and show in order to carry out failure analysis memory by display interface.
7. system according to claim 6, is characterized in that, described system also comprises:
The Desktop Management Interface information reading module, for the storage component part information of the Desktop Management Interface information that reads multichannel memory and show in order to carry out failure analysis memory by display interface; And/or,
The internal memory performance information reading module, for the performance information of the internal memory that reads described computing machine and show in order to carry out failure analysis memory by display interface.
8. system according to claim 7 is characterized in that:
The performance information of described internal memory comprises one of following or combination in any: the time sequence parameter of interior presence bit information, memory size, internal memory reading rate and internal memory.
9. system according to claim 8, is characterized in that, described system also comprises:
The performance information modified module, for time sequence parameter and/or the reading rate of revising described internal memory.
10. according to the described system of claim 6 to 9 any one, it is characterized in that, described system is worked under the DOS system.
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| CN1479207A (en) * | 2002-08-29 | 2004-03-03 | 深圳市中兴通讯股份有限公司 | Internal storage detecting method |
| CN1929034A (en) * | 2006-09-07 | 2007-03-14 | 华为技术有限公司 | Method and system for RAM fault testing |
| CN102222025A (en) * | 2011-06-17 | 2011-10-19 | 华为数字技术有限公司 | Method and device for eliminating memory failure |
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| JPH11282764A (en) * | 1998-03-30 | 1999-10-15 | Oki Electric Ind Co Ltd | Memory error point cut-off circuit |
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Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1479207A (en) * | 2002-08-29 | 2004-03-03 | 深圳市中兴通讯股份有限公司 | Internal storage detecting method |
| CN1929034A (en) * | 2006-09-07 | 2007-03-14 | 华为技术有限公司 | Method and system for RAM fault testing |
| CN102222025A (en) * | 2011-06-17 | 2011-10-19 | 华为数字技术有限公司 | Method and device for eliminating memory failure |
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| JP特开平11-282764A 1999.10.15 |
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