CN102484449A

CN102484449A - Divide-by-two injection-locked ring oscillator circuit

Info

Publication number: CN102484449A
Application number: CN2010800390731A
Authority: CN
Inventors: 拉塞尔·J·法格
Original assignee: Qualcomm Inc
Current assignee: Qualcomm Inc
Priority date: 2009-09-03
Filing date: 2010-09-03
Publication date: 2012-05-30
Anticipated expiration: 2030-09-03
Also published as: US8487670B2; CN102484449B; JP2013504268A; KR20120062869A; KR101437506B1; EP2474093B1; JP5512816B2; WO2011029041A1; US20110050296A1; EP2474093A1

Abstract

A frequency divider involves a plurality of Injection-locked Ring Oscillators (ILRO). A first ILRO includes a pair of cross-coupled N-channel transistors, a pair of load resistors, an integrating capacitor, and a current injection circuit. The drain of each transistor is coupled to the gate of the other transistor. Each load resistor couples the drain of each transistor to a circuit voltage source. The integrating capacitor couples the sources of each transistor. The current injection circuit alternately opens and closes a path from the source of each transistor to circuit ground in response to an oscillatory input signal of a first frequency. In response, the voltage state at the drain of each transistor is alternately latched and toggled, generating a differential pair of oscillating signals frequency divided by two. A first and second ILRO driven in antiphase generate two differential output signals in phase quadrature.

Description

Divided by two injection locking ring type pierce circuits

Technical field

The embodiment that is disclosed relates generally to the frequency divider that comprises the frequency divider that can in wireless communication system, operate.

Background technology

For some application such as for example wireless communication systems, comprise that the frequency divider circuit is useful.In an example, frequency divider receives the vibration input signal, and said input signal is carried out the frequency division arithmetic, and produces the oscillation output signal through the frequency reducing division arithmetic.Said frequency division arithmetic is characterised in that the frequency division arithmetic that carries out with integer.In wireless communication system, visible frequency divider is used as the part of radio transceiver (emitter/receiver) continually.In the instance in radio transceiver; Frequency divider can be in order to receive the oscillator signal from local oscillator (LO); Said oscillator signal is carried out the frequency reducing division arithmetic, and produce the output signal of two lower frequencies: difference homophase (I) output signal and difference quadrature (Q) output signal.The frequency of output signal I and Q can (for example) be half of frequency of input signal.Q output signal has the frequency identical with the I output signal frequency, but on phase place, spends with respect to I output signal displacement 90.Thereby differential output signal I and Q are stated to be quadrature on phase place.Can (for example) be fed to the frequency mixer in the reception chain of radio transceiver through the set of the output signal of frequency reducing division arithmetic.This situation is the only a kind of application of frequency divider in wireless communication system.Also visible frequency divider is used in the phase-locked loop in the local oscillator, or also can carry out the frequency division arithmetic in order to the signal to other place in the wireless communication system circuit.

Fig. 1 (prior art) is the figure of one type frequency divider circuit 1.Frequency divider 1 comprises two conventional injection locking frequency dividers (ILFD) 2 and 3.Frequency divider 1 receives differential input signal LO, and it comprises signal LO+ and the signal LO-on the conductor 5 on the conductor 4.Frequency divider 1 produces two differential output signal I and Q.Differential output signal I comprises signal I+ and the signal I-on the conductor 7 on the conductor 6.Differential output signal Q comprises signal Q+ and the signal Q-on the conductor 9 on the conductor 8.Both are one type oscillating circuit for ILFD 2 and ILFD 3.For instance, be applied to ILFD 2 if will have the input signal of constant voltage, ILFD 2 will only vibrate with the natural frequency of himself so.Yet, being applied to ILFD 2 if will have at the vibration input signal that can accept the enough amplitudes in the frequency window, ILFD 2 vibrates " locking " to the frequency of vibration input signal and with half of frequency of vibration input signal so.Therefore, frequency divider 2 can be operated carrying out the frequency division arithmetic with two couples of input signal LO of integer, and is created in the output signal of quadrature on the phase place.Though the circuit of Fig. 1 is operation satisfactorily in some applications, it has many restrictions.Owing to the use of inductive load, the physics of conventional ILFD size is big for undesirably.In addition, inductor serves as the reflector and the receiver of electromagnetic interference (EMI) under the situation of big circuit.Therefore, inductor suppresses the performance of other circuit element, and the performance of frequency divider 1 is suppressed by other circuit element.In addition, for typical input signal amplitude, conventional ILFD will be reliably " locking " to and the scope of therefore carrying out the incoming frequency of division arithmetic be limited to the less relatively percentage of the tuning incoming frequency in center.Can realize widerly through increasing input signal amplitude or reducing the inductor factor of quality, but the method consumes more power.Tuning group of meticulous numerically controlled capacitor can expand 30% to 40% actual range into the tuning incoming frequency in center in order to the effective range with ILFD to, but the method is complicated and consume die area for undesirably.

Fig. 2 (prior art) is the figure of the frequency divider circuit 10 of another kind of type.Frequency divider 10 comprises two cross-linked common mode logics (CML) circuit 11 and 12.Frequency divider 10 receives differential input signal LO, and it comprises signal LO+ and the signal LO-on the conductor 14 on the conductor 13.Divider 10 produces two couples of differential output signal I and Q.Differential output signal I comprises signal I+ and the signal I-on the conductor 16 on the conductor 15.Differential output signal Q comprises signal Q+ and the signal Q-on the conductor 18 on the conductor 17.CML circuit 11 comprises that transistor T R1 is to TR6.LO-is fed to transistor T R3, and LO+ is fed to transistor T R4.The state of transistor T R1 and TR2 sensing CML circuit 12, and TR3 when being high through the LO-time control with the loading resistor of this state transitions to CML circuit 11.When TR3 is low through the LO-time control and TR4 when being high through the LO+ time control, transistor T R5 and TR6 latch the state of the resistor of CML 11 during this stage of clock circulation.In this way, output signal I+ and I-vibrates with the frequency of LO half.Similarly, output signal Q+ and Q-vibrates with the frequency of LO half.Yet, receive LO+ and the LO-be in opposite polarity because CML 12 compares with CML 11, so difference output is quadrature to (Q+, Q-) and difference output to (I+, I-) on phase place.Being limited in of frequency divider 10, the output voltage swing of divider are not for track to track.In fact, the low output voltage swing of frequency divider 10 only can reach and be higher than ground connection (VSS) hundreds of millivolt.Because this scope that reduces, the phase noise performance of divider is low with respect to other solution.In addition, must use the track to track transducer that frequency divider 10 and passive frequency mixer buffer stage Jie of inverter type are connect.The track to track transducer consumes a large amount of power at hundreds of megahertzes in the frequency range of thousands of megahertzes.

The frequency divider of another kind of type is for utilizing the dynamic logic divider based on transistorized inverter.Unfortunately, said inverter needs relative higher voltage supply rail to carry out division arithmetic.In fact, the supply voltage that inverter need add two drain electrode-source electrode saturation voltages greater than two threshold voltages is having enough gains, thus operation reliably.Second shortcoming is that the dynamic logic divider needs the track to track input signal to carry out division arithmetic.In the side circuit design, send input signal from local oscillator via the common holding wire that surpasses a millimeter of length.On this distance, tend to make the amplitude fading of oscillator signal along the power loss of said line generation.In order to overcome these losses and the track to track signal delivery to be arrived divider, must launch stronger signal by local oscillator, thereby cause undesirable level of power consumption.In application (for example; In the radio transceiver of battery powered cellular phone); Maybe be at frequency of operation divider under the minimal power consumption, said frequency divider receives through the vibration input signal of decay and produces low phase noise, track to track I signal and Q signal.

Summary of the invention

A kind of frequency divider comprises injection locking ring type oscillator (ILRO).In one embodiment, said frequency divider comprises two ILRO.Said frequency divider receives differential input signal, carries out division arithmetic with the frequency of two pairs of said input signals of integer, and exports two differential output signals.In the said differential signal first is homophase (I) differential signal that is produced by first ILRO.The two is quadrature (Q) differential output signal that is produced by second ILRO in the said differential signal the.Therefore said I and Q signal be each other about 90 degree of out-phase, and be quadrature on phase place.

Each ILRO comprise cross-linked transistor to, with each transistor corresponding load resistor, integrating condenser and the electric current injection circuit of said cross-linked pair of transistors.Said I differential output signal is present between the right drain electrode of the said cross-linked transistor of a said ILRO.Said Q differential output signal is present between the right drain electrode of the said cross-linked transistor of said the 2nd ILRO.In each ILRO, each transistorized said drain coupled is to the grid of the right said respective transistor of said cross-linked transistor.Loading resistor is coupled between circuit voltage source and each the transistorized said drain electrode.Said each transistorized source electrode of integrating condenser coupling.Said electric current injection circuit alternately opens and closes the path from each transistorized said source electrode to circuit ground in response to the vibration input signal with first frequency.As response, the voltage status of each transistorized said drain electrode place is through alternately latching and switch, thereby produces a pair of differential vibrating output signal that carries out the frequency division arithmetic with two.In this way, two ILRO that drive through said differential input signal anti-phase ground produce said two differential output signal I and Q.

In a second embodiment, a kind of frequency divider receives single-ended input signal, carries out division arithmetic with the frequency of two pairs of said input signals of integer, and two the differential output signal I and the Q of output quadrature on phase place.In this embodiment, said frequency divider comprises single ILRO.Be present in the said differential output signal I between the right drain electrode of said cross-linked transistor and be present in about 90 degree of differential signal out-phase between the right source electrode of said cross-linked transistor.Therefore, the said differential signal that is present between the right said source electrode of said cross-linked transistor is similar to difference quadrature signal Q.

In the 3rd embodiment, a kind of frequency divider is carried out the division arithmetic that carries out with four pairs of frequencies.In this embodiment, carry out the frequency reducing division arithmetic through an ILRO with two pairs of single-ended input signals.The output signal that is present in each right transistor drain place of the cross-linked transistor of a said ILRO is respectively through being sent to the input of the second and the 3rd ILRO.Therefore, the said second and the 3rd ILRO drives through the differential input signal anti-phase ground through the frequency reducing division arithmetic.The said second and the 3rd ILRO carries out the frequency division arithmetic with two pairs of said input signals through the frequency reducing division arithmetic, and produces two differential output signal I and Q.In this embodiment, carried out the frequency reducing division arithmetic with four pairs of said input signals to said frequency divider.A said ILRO carries out the frequency division arithmetic with two pairs of said input signals, and the said second and the 3rd ILRO carries out the frequency division arithmetic with two pairs of said signals once more and produces the output signal of quadrature in phase.

In the 4th embodiment, realize a kind of frequency divider with improved output conversion of signals rate.In this embodiment, said frequency divider comprises two ILRO.Said frequency divider receives differential input signal, carries out division arithmetic with the frequency of two pairs of said input signals, and two the differential output signal I and the Q of output quadrature on phase place.Exchange source-coupled to the three transistorized grids of (AC) coupling capacitor the first transistor that the cross-couplings of a said ILRO is right.The said the 3rd transistorized source-coupled is to current source.Said the 3rd transistor drain is coupled to the drain electrode of the right the first transistor of the cross-linked transistor of said the 2nd ILRO.In this way, the said signal at said source electrode place that is present in said the first transistor is through anti-phase, through amplifying, and is fed to first output node of said the 2nd ILRO.Therefore, first loading resistor of said the 2nd ILRO is by two transistor driving, thereby improves the said transfer ratio of the said output signal on the said first node that is present in said the 2nd ILRO.In addition, two of said differential input signal components drive the said output signal on the said first node that is present in said the 2nd ILRO.No matter this situation is improved frequency divider performance and input noise and device mismatch.With a similar fashion, the right said drain electrode of said cross-linked transistor that each right transistorized said source electrode of the said cross-linked transistor of each ILRO is coupled to said relative ILRO respectively.Therefore, said differential output signal I and the Q with said frequency divider realizes feature performance benefit.

Foregoing is summary and simplification, vague generalization and the omission that therefore contains details inevitably; Therefore, be understood by those skilled in the art that said summary only has illustrative and and do not mean that by any way for restrictive.As only by the others of defined device described herein of claims and/or process, invention feature and advantage with becoming obvious in the non-limiting embodiment of being set forth in this article.

Description of drawings

Fig. 1 (prior art) is the figure that comprises the frequency divider of two conventional injection locking frequency dividers (ILFD).

Fig. 2 (prior art) is the figure that comprises the frequency divider of two cross-linked common mode logics (CML) circuit.

Fig. 3 is the reduced graph according to the mobile communications device 100 of the use injection locking ring type oscillator (ILRO) of a novel aspect.

Fig. 4 is the more details drawing of the RF transceiver integrated circuit 102 of Fig. 3.

Fig. 5 is the figure of the operation of the frequency divider 113 in the reception chain 108 of RF transceiver integrated circuit 102 of Fig. 4.

Fig. 6 is the more details drawing of frequency divider 113 of reception chain 108 of the RF transceiver integrated circuit 102 of Fig. 4.

Fig. 7 A is the injection locking ring type oscillator 130 more details drawing in operation of the frequency divider 113 of Fig. 6 to 7D.

Fig. 8 explains input waveform and the output waveform that frequency divider 113 is in operation.

Fig. 9 explains second embodiment of frequency divider 113.

Figure 10 explain frequency divider 113 among the 3rd embodiment with four division arithmetics that carry out.

Figure 11 explains the frequency divider 113 among the 4th embodiment.

Figure 12 is the flow chart according to the method for an aspect.

Embodiment

Fig. 3 is that the utmost point of mobile communications device 100 (for example, cellular phone) is simplified the high-order block diagram.Device 100 comprises that (except that unaccounted other part) can be used for receiving and launching antenna 101, RF transceiver integrated circuit 102 and the digital baseband integrated circuit 103 of cellular phone communication.

Fig. 4 is the more details drawing of the RF transceiver integrated circuit 102 of Fig. 3.Simplify at a utmost point of the operation of cellular phone and to explain, if cellular phone receives on antenna 101 so and imports emission 104 into just in order to receive the audio-frequency information as the part of cellular phone conversation.Signal passes through duplexer 105 and matching network 106, and is amplified by the low noise amplifier (LNA) that receives chain 108 107.After carrying out down converted by frequency mixer 109 and after carrying out filtering by baseband filter 110, information is through being sent to digital baseband integrated circuit 103 to be used for the further processing of mould/number conversion and numeric field.As the part of down-conversion process, frequency mixer 109 receives the oscillator signal LO1/N through the frequency reducing division arithmetic that is produced by frequency divider 113, and uses this signal to come down converted by receiving chain 108 information processed.In fact the signal that is called as through the oscillator signal LO1/N of frequency reducing division arithmetic comprises two differential signal I and Q.The set of crossing over two conductors transmits each among differential signal I and the Q.Frequency divider 113 tightens to connect airtight at entity and is bordering on the circuit that receives chain 108.Frequency divider 113 receives local oscillator signal LO1, with Integer N the frequency of signal is carried out division arithmetic, and output is through the oscillator signal LO1/N of frequency reducing division arithmetic.Local oscillator signal LO1 is produced by local oscillator 111.LO1 can (for example) be the differential signal via two conductor emissions.In other instance, LO1 can be the single-ended signal via the plain conductor emission.LO1 is transmitted into frequency divider 113 via long " lossy " line 112.Such as hereinafter explanation, signal LO1 stands the parasitic power loss during the emission of crossing over long " lossy " line 112.These losses make the high fdrequency component decay of peak-to-peak signal amplitude and the LO1 of LO1.

On the other hand, if cellular phone 100 just in order to the audio-frequency information of emission as the part of cellular phone conversation, so armed audio-frequency information converts analog form in digital baseband integrated circuit 103.Analog information is fed to the baseband filter 114 of the emission chain 115 of RF transceiver integrated circuit 102.After filtering, carry out up conversion through 116 pairs of signals of frequency mixer.As the part of up conversion process, frequency mixer 116 receives the oscillator signal LO2/N through the frequency reducing division arithmetic that is produced by frequency divider 119, and uses this signal to come up conversion by emission chain 115 information processed.Amplify the signal of gained through driver amplifier 120 and external power amplifier 121 through up conversion.Be fed to antenna 101 to launch through amplifying signal as spreading out of emission 122.Comprise two differential signal I and Q through the oscillator signal LO2/N of frequency reducing division arithmetic.Frequency divider 119 receives local oscillator signal LO2, with integer divisor N the frequency of signal is carried out division arithmetic, and output is through the oscillator signal LO2/N of frequency reducing division arithmetic.Local oscillator signal LO2 is produced by local oscillator 117.LO2 can (for example) be the differential signal via two conductor emissions.In other instance, LO2 can be the single-ended signal via the plain conductor emission.LO2 is transmitted into frequency divider 119 via long " lossy " line 118, and said frequency divider 119 resident one-tenth closely approach to launch the circuit of chain 115.During the emission via long " lossy " line 118, signal LO2 stands the parasitic power loss, and said loss makes peak to peak amplitude and the high fdrequency component decay of signal LO2.

Fig. 5 is the more details drawing of the operation of the frequency divider 113 in the reception chain 108 of RF transceiver integrated circuit 102 of Fig. 4.Frequency divider 113 is coupled to frequency mixer 109 through conductor 132,133,144 and 145.Frequency divider 113 is coupled to local oscillator 111 through conductor 131 and 143.Frequency divider 113 receives differential input signal LO1, and it comprises signal LO+ and the signal LO-on the conductor 143 on the conductor 131.Frequency divider 113 produces the output signal LO1/N through the frequency reducing division arithmetic through with Integer N input signal LO1 being carried out the frequency division arithmetic.LO1/N comprises two differential output signal I and Q.Differential output signal I comprises signal I+ and the signal I-on the conductor 133 on the conductor 132.Differential output signal Q comprises signal Q+ and the signal Q-on the conductor 145 on the conductor 144.I+, I-, Q+ and Q-are four oscillator signals through the frequency reducing division arithmetic of quadrature on phase place together.Such as hereinafter explanation, the version of the approximate input of all four signals waveform LO1, but in four signal indications each is characterised in that the phase difference of about 90 degree through the frequency division arithmetic.

Frequency mixer 109 comprises the frequency mixer buffer stage that receives differential output signal I and Q via conductor 132,133,144 and 145.The frequency mixer buffer stage comprises inverter circuit.Frequency mixer buffer stage based on inverter is used for its power-efficient operating characteristic.Yet said frequency mixer buffer stage roughly track to track input waveform operates reliably.Therefore, the track to track amplitude waveform that differential output signal I and Q must approximate ideals is to drive frequency mixer 109 reliably.In operation, output signal I+, I-, Q+ and Q-vibrate between maximum voltage and minimum voltage, and said maximum voltage is in tens millivolts of circuit supply voltage VDD, and said minimum voltage is in tens millivolts of circuit ground voltage VSS.The frequency mixer buffer stage of frequency mixer 109 is operated when being driven by output signal I+, I-, Q+ and Q-from frequency divider 113 reliably.

Local oscillator 111 is coupled to frequency divider 113 through long " lossy " line 112.In this example, local oscillator 111 produces differential signal LO1.Long " lossy " line 112 comprises: the conductor 131 and the conductor 143 that comprises signal LO-that comprise signal LO+.In other instance, local oscillator 111 can produce single-ended signal, and line 112 can only comprise the plain conductor that comprises single-ended input signal.In wireless communication system (for example, battery powered cellular phone), local oscillator 111 is fed to multiple branch circuit (sub-circuit) with oscillator signal.Therefore, being built in entity, to tighten the local oscillator 111 that connects airtight nearly each branch circuit be impossible.As a result, local oscillator 111 does not closely approach to receive the frequency divider 113 of chain 108 usually on entity.For instance, the length of long " lossy " line 112 is more than one millimeter or one millimeter.Because this length, the oscillator signal that transmits via line 112 becomes the machine-processed victim of some power losss.Capacitive couplings to die substrate has the LPF effect to the high-frequency oscillation signal via line 112 emissions.The electromagnetic radiation loss also makes the amplitude fading via the high-frequency signal of line 112 emissions, and the charge/discharge of line 112 produces the loss of 1/2cv2f.Owing to the length of line 112, line 112 works as antennae, and stands radiation loss via the high-frequency signal of line 112 emissions.Because these power losss, the oscillator signal of launching via line 112 stands the decay of peak-to-peak signal amplitude and the decay of high fdrequency component.For instance, tighten at entity and connect airtight the waveform that is bordering on local oscillator 111 and measures and closely to be similar to ideal square wave from the signal LO of local oscillator 111.Yet, closely approach frequency divider 113 and the same signal measured can be through decaying aspect amplitude and high fdrequency component.For purposes of illustration, the transformation of square wave warp is decayed greatly, and is revealed as fillet in each transformation place.Though can overcome these power losss through increasing transmitting power, this situation causes undesirable increase of power consumption.Therefore, frequency divider 113 should be able to carry out division arithmetic reliably to the input signal through decay.

Fig. 6 is the more details drawing of frequency divider 113 of reception chain 108 of the RF transceiver integrated circuit 102 of Fig. 4.Frequency divider 113 comprises two injection locking ring type oscillators (ILRO) 130 and 142.Injection locking ring type oscillator 130 comprise a pair of

loading resistor

138 and 139, cross-linked transistor to 137, integrating condenser 136 and electric current injection circuit 135.In this example, the resistance value of each in the

resistor

138 and 139 is 200 ohm.In other instance, can use other resistance value.First lead-in wire of first resistor 138 and first lead-in wire of second resistor 139 are coupled to Voltage Reference node 148.At Voltage Reference node 148 places supply circuit supply voltage VDD.For instance, VDD can be as small as 700 millivolts.Second lead-in wire of resistor 138 is coupled to vibration node 140, and second lead-in wire of resistor 139 is coupled to vibration node 141.Output signal I-is present in vibration node 140 places, and on conductor 132, transmits from frequency divider 113.Output signal I+ is present on the vibration node 141, and on conductor 133, transmits from frequency divider 113.Cross-linked transistor comprises N channel transistor 152 (TR1) and N channel transistor 153 (TR2) to 137.The drain coupled of TR1 is to vibration node 140, and the drain coupled of TR2 is to vibration node 141.In addition, the gate coupled of TR1 is to the drain electrode of TR2, and the gate coupled of TR2 is to the drain electrode of TR1.The transconductance value of TR1 and TR2 and load resistance value multiply each other and define the gain of ILRO 130.For division arithmetic takes place, gain must be greater than one.In this example, be used for reliable division arithmetic greater than two gain.Integrating condenser 136 comprises first lead-in wire of the source electrode that is coupled to TR1 and is coupled to second lead-in wire of the source electrode of TR2.In this example, integrating condenser 136 is the metal-metal capacitor device, and it has tens of capacitances to hundreds of femto farads (femtofarad).Electric current injection circuit 135 comprises N channel transistor 154 (TR3) and N channel transistor 155 (TR4).The drain coupled of TR3 is to first lead-in wire of integrating condenser 136, and the drain coupled of TR4 is to second lead-in wire of integrating condenser 136.In this example, the size of TR3 and TR4 is similar to TR1 and TR2.The source electrode of TR3 and the source-coupled of TR4 are to the second Voltage Reference node 149.The second Voltage Reference node, 149 supply second circuit supply voltage VSS.For instance, VSS can be circuit ground.In addition, the gate coupled of the grid of TR3 and TR4 is to the input node 150 of injection locking ring type oscillator 130.Input node 150 is coupled to conductor 131.

Injection locking ring type oscillator (ILRO) 142 is similar to injection locking ring type oscillator 130.The cross-linked transistor that ILRO 142 comprises a pair of

loading resistor

182 and 183, comprise

N channel transistor

184 and 185 is to, integrating condenser 186 and electric current injection circuit 187.Output signal Q-is present in vibration node 146 places, and on conductor 144, transmits from frequency divider 113.Output signal Q+ is present on the vibration node 147, and on conductor 145, transmits from frequency divider 113.The input node 151 of injection locking ring type oscillator 142 is coupled to conductor 143.Because the LO+ signal is sent to the input voltage node 150 of ILRO 130 and the LO-signal is sent to the input voltage node 151 of ILRO 142, ILRO 130 and LRO 142 time controls are in the opposite phase of input signal LO.In this example, each LO+ signal and LO-signal have waveform, and vibration between about 100 millivolts and 1.3 volts.

Fig. 7 A is the injection locking ring type oscillator 130 more details drawing in operation of frequency divider 113 to 7D.On conductor 131, input signal LO+ is sent to the input voltage node 150 of ILRO 130.In this example, LO+ can be and has the square-wave signal of hundreds of megahertz to the frequency of oscillation of several Gigahertzs.Fig. 7 A explains the complete output circulation of the operation of ILRO 130 from time T 0 to time T4 respectively with four levels to 7D.Fig. 7 A is to 7D explanation LO+, I+ and the voltage waveform of I-from time T 0 to time T4.To T4, LO+ experiences two complete cycle cycles in said period of time T 0.On cycle, I-and I+ experience a complete cycle cycle at one time.Therefore, the operation of ILRO 131 causes carrying out the frequency division arithmetic with two couples of LO+.

Fig. 7 A explanation is in the ILRO 130 of " latching " state.The state that " latchs " is characterised in that the time cycle when input signal LO+ is in digital high state.Latch mode during the time cycle from T0 to T1 of Fig. 7 A explanation when LO+ is in high state.The signal LO+ at input voltage node 150 places is sent to the grid of TR3 and TR4.The transistor T R3 of ILRO130 and TR4 drive in the inelastic region of transistor operation through LO+.Therefore, when LO+ was in high state, TR3 and TR4 were what conduct.In time T 0, the drain electrode of TR1 is in low-voltage state, and the drain electrode of TR2 is in high-voltage state.Because the high-voltage state of drain electrode place of TR2 is sent to the grid of TR1, so TR1 is conduction substantially.Because TR1 and TR3 are conduction when T0, so electric current 134 flow to circuit ground node 149 from circuit supply voltage node 148 via loading resistor 138, TR1 and TR3.Because the resistance value of transistor T R1 and TR3 that is in conducted state is significantly less than the resistance value of loading resistor 138, so electric current 134 is substantially equal to the resistor values of the circuit supply voltage VDD at node 148 places divided by loading resistor 138.Because the low-voltage state of drain electrode place of TR1 is sent to the grid of TR2, so TR2 is opaque for substantially.Because TR2 is opaque for substantially, thus the no current TR2 that flows through substantially, and the voltage status of drain electrode place of TR2 remains height.Run through " latching " state from T0 to T1, the voltage status of drain electrode place of TR2 continues to drive for high, and the voltage status of drain electrode place of TR1 continues to drive to low.Term " latchs " state and refers to following notion, and: signal I-and the I+ that is present in drain electrode place of TR1 and TR2 respectively continues to drive in the duration of " latching " state and is its initial condition.Under the situation in being illustrated in Fig. 7 A, " latching " state lasts till time T 1 from time T 0.

Fig. 7 B explanation is in " switching " (toggle) ILRO 130 of state." switching " state is characterised in that the time cycle when LO+ is in the low state of numeral.Fig. 7 B explanation switching state during the time cycle from T1 to T2 of LO+ when low.Because TR3 and TR4 drive in the inelastic region of transistor operation through LO+, so when LO+ was in the state of hanging down, transistor T R3 and TR4 were opaque.The time that between the conducted state of TR3 and TR4 and non-conducting state, changes with respect to cycle of oscillation of LO+ for extremely short.In addition, term conducted state and non-conducting state should not hint conduction or complete opaque state fully, but confirm through actual N channel transistor embodiment.In time T 1, the drain electrode of TR1 is in low-voltage state, and the drain electrode of TR2 is in high-voltage state.Because the high-voltage state of drain electrode place of TR2 is sent to the grid of TR1, so TR1 is conduction substantially.Yet, since TR1 for conduction substantially and TR3 begin to substantially opaquely from T1, so electric current flow to the integrating condenser 136 via loading resistor 138 from circuit supply voltage node 148.Along with the time proceeds to time T 2 from time T 1, voltage is formed at the source electrode place of TR1, and because TR1 and TR2 operate in the linear zone that transistor is operated, so voltage also is formed at drain electrode place of TR1.The voltage signal that is formed at drain electrode place of TR1 is sent to the grid of TR2.As response, TR2 begins conduction.As a result, electric current begins from circuit supply voltage node 148 via loading resistor 139 and flow to the integrating condenser 136.Along with this electric current begins to flow, the voltage of drain electrode place of TR2 begins to reduce.Because the voltage signal of drain electrode place of TR2 is sent to the grid of TR1, so TR1 begins to change non-conducting substantially into from conducting substantially.Therefore, the signal I-of drain electrode place of TR1 is driven into high-voltage state through the combination of two mechanism from low-voltage state.First mechanism is through 136 chargings increase the voltage at the source electrode place of TR1 to integrating condenser along with the electric current through TR1.Second mechanism is that the drain electrode of grid and TR2 of drain electrode and TR2 of TR1 is to the cross-couplings of the grid of TR1.This cross-couplings promotes the disconnection of TR1 through the grid that low voltage signal is sent to TR1 in response to the voltage of drain electrode place of TR1 raises.Therefore, integrating condenser 136 increases through the voltage swing of the signal I-that launches these two mechanism and make output node 140 places.Run through " switching " state from T1 to T2, the voltage status of drain electrode place of TR1 drives to low, and the voltage status of drain electrode place of TR2 drives to high.Term " switching " state refers to following notion: signal I-and the I+ that is present in drain electrode place of TR1 and TR2 respectively drives in the duration of " switching " state and is the state opposite with its initial condition.Under the situation in being illustrated in Fig. 7 A, " switching " state lasts till time T 2 from time T 1.

Fig. 7 C explanation is in digital high state once more along with LO+ and is in the ILRO 130 of " latching " state.Latch mode during the time cycle of Fig. 7 C explanation from T2 to T3.Quick exchange arrives conducted state in response to LO+ is converted to high state for transistor T R3 and TR4.In time T 2, the drain electrode of TR1 is in high-voltage state, and the drain electrode of TR2 is in low-voltage state.Because the low-voltage state of drain electrode place of TR2 is sent to the grid of TR1, so TR1 is opaque for substantially.Because TR1 is opaque for substantially, thus flow through TR1 or TR3 of no current substantially, and the voltage status of drain electrode place of TR1 remains height.Because the high-voltage state of drain electrode place of TR1 is sent to the grid of TR2, so TR2 is conduction substantially.Because TR2 and TR4 are conduction when T2, so electric current flow to circuit ground node 149 from circuit supply voltage node 148 via loading resistor 139.Because the resistance value of transistor T R2 and TR4 that is in conducted state is significantly less than the resistance value of loading resistor 139, so this electric current is substantially equal to the resistor values of the circuit supply voltage VDD at node 148 places divided by loading resistor 139.Run through " latching " state from T2 to T3, the voltage status of drain electrode place of TR1 continues to drive for high, and the voltage status of drain electrode place of TR2 continues to drive to low.Therefore, signal I-and the I+ that is present in drain electrode place of TR1 and TR2 respectively continues to drive in the duration of " latching " state from time T 2 to time T3 and is its initial condition.

Fig. 7 D explanation is in the ILRO 130 of " switching " state once more.Fig. 7 D explanation switching state during the time cycle from T3 to T4 of LO+ when low.Transistor T R3 and TR4 are converted to the non-conducting state apace in response to LO+ is converted to low state.In time T 3, the drain electrode of TR1 is in high-voltage state, and the drain electrode of TR2 is in low-voltage state.Because the high-voltage state of drain electrode place of TR1 is sent to the grid of TR2, so TR2 is conduction substantially.Yet, since TR2 be conduction substantially and TR4 opaque for substantially when T3, so electric current is supplied voltage node 148 from circuit and is flow to the integrating condenser 136 via loading resistor 139.Along with the time proceeds to time T 4 from time T 3, voltage is formed at the source electrode place of TR2, and because TR1 and TR2 operate in the linear zone that transistor is operated, so voltage also is formed at drain electrode place of TR2.The voltage signal that is formed at drain electrode place of TR2 is sent to the grid of TR1.As response, TR1 begins conduction.As a result, electric current begins from circuit supply voltage node 148 via loading resistor 138 and flow to the integrating condenser 136.Along with this electric current begins to flow, the voltage of drain electrode place of TR1 begins to reduce.Because the voltage signal of drain electrode place of TR1 is sent to the grid of TR2, so TR2 begins to change non-conducting substantially into from conduction substantially, thereby constrained flow is through the electric current of TR2 and further form voltage in drain electrode place of TR2.Therefore, the voltage signal of drain electrode place of TR2 is driven into high-voltage state through the combination of two mechanism from low-voltage state.First mechanism is for 136 chargings increase the voltage at the source electrode place of TR2 to integrating condenser along with the electric current through TR2.Second mechanism is that the drain electrode of grid and TR1 of drain electrode and TR1 of TR2 is to the cross-couplings of the grid of TR2.This cross-couplings promotes the disconnection of TR2 through the grid that low voltage signal is sent to TR2 in response to the voltage in drain electrode place of TR2 raises.Therefore, integrating condenser 136 increases through the voltage swing of the signal I+ that launches these two mechanism and make output node 141 places.Run through " switching " state from T3 to T4, the voltage status of drain electrode place of TR2 drives to high, and the voltage status of drain electrode place of TR1 drives to low.Term " switching " state refers to following notion: signal I-and the I+ that is present in drain electrode place of TR1 and TR2 respectively drives in the duration of " switching " state and is the state opposite with its initial condition.Under the situation in being illustrated in Fig. 7 D, " switching " state lasts till time T 4 from time T 3.

Fig. 8 explains input waveform and the output waveform that frequency divider 113 is in operation.As discussing in detail in 7D at Fig. 7 A, an ILRO 130 receives LO+, carries out division arithmetic with two pairs of frequencies, and the oscillator signal I+ and the I-through the frequency reducing division arithmetic of output anti-phase.In a similar manner, ILRO 142 receives vibration input signal LO-, carries out division arithmetic with two pairs of frequencies, and the oscillation output signal Q+ and the Q-through the frequency reducing division arithmetic of output anti-phase.The frequency of oscillation of input signal LO is characterised in that to input signal LO and passs to follow the trail of the time cycle of complete cycle.This cycle time can be described as the input cycle period.The frequency of oscillation of each in the oscillator signal of frequency reducing division arithmetic be characterised in that in the said signal each and pass to follow the trail of the time cycle of complete cycle.This cycle time can be described as the output cycle period.Because ILRO 130 and 142 carries out division arithmetic with two pairs of frequencies, so the output cycle period is the twice of input cycle period.Because LO+ and LO-are the opposite input signal LO of phase place, so LO-is characterized as and lags behind half the or (equivalently) that LO+ reaches the input cycle period on the time and export 1/4th of cycle period.This postpones directly to propagate via ILRO 142, makes signal Q+ and Q-lag behind signal I+ and I-respectively and reaches and export 1/4th of cycle period.Perhaps, this hysteresis can be expressed as the phase lag of 90 degree.Therefore, frequency divider 113 is output as the set of four signals (I+, I-, Q+, Q-) of quadrature on phase place, and it vibrates with half of the frequency of input signal LO separately.

Fig. 9 explains second embodiment of frequency divider 113.Frequency divider 113 only comprises ILRO 130.As describing among Fig. 9, ILRO 130 is as described in Fig. 6.Yet in this example, ILRO 130 comprises the output node 160 and the output node 161 that is coupled to source electrode TR2 of the source electrode that is coupled to TR1.Output signal Q+ is present on the output node 160, and on conductor 156, transmits from frequency divider 113.Output signal Q-is present on the output node 161, and on conductor 157, transmits from frequency divider 113.ILRO 130 receives vibration input signal LO+ via conductor 131, carries out division arithmetic with two pairs of frequencies, and on conductor 133,132,156 and 157, exports oscillator signal I+, I-, Q+ and Q-through the frequency reducing division arithmetic respectively.The signal Q+ that is present in output node 160 places lags behind the signal I-that is present in vibration node 140 places and reaches about 90 degree.Similarly, the signal Q-that is present in vibration node 161 places lags behind the signal I+ that is present in vibration node 141 places and reaches about 90 degree.Therefore, combination, the signal that is present in vibration node 140,141,160 and 161 places on phase place for quadrature.Therefore, the single ILRO that drives through single-ended oscillator signal can two carries out the frequency division arithmetics, and four oscillator signals through the frequency reducing division arithmetic of output quadrature on phase place.The phase noise performance of second embodiment is less than the phase noise performance of first embodiment.But, through only using an ILRO but not two ILRO come to carry out frequency division arithmetics (having quadrature in phase output) with two, power is able to practice thrift.In addition, only a conductor is sent to frequency divider 113 with the vibration input signal from local oscillator 111, thereby saves the space on the integrated circuit die.Therefore, exchange in the application of lower cost and power consumption at availability performance, second embodiment of frequency divider 113 compares with first embodiment and can be preferably.

Figure 10 explain frequency divider 113 among the 3rd embodiment with four division arithmetics that carry out.In this example, frequency divider 113 comprises ILRO 130, ILRO 142 and ILRO 162.As in Figure 10, describing, ILRO 130 and ILRO 142 are as described in Fig. 6, and ILRO 162 is similar to ILRO 130.Output signal I-is present in vibration node 140 places of ILRO130, and on conductor 132, transmits from frequency divider 113.Output signal I+ is present on the vibration node 141 of ILRO130, and on conductor 133, transmits from frequency divider 113.Output signal Q-is present in vibration node 146 places of ILRO142, and on conductor 144, transmits from frequency divider 113.Output signal Q+ is present on the vibration node 147 of ILRO142, and on conductor 145, transmits from frequency divider 113.Input signal I1+ is present on the input node 167 of ILRO 162.Input node 167 is coupled to conductor 131, and input signal I1+ receives on conductor 131 through frequency divider 113.The vibration node 165 of ILRO 162 is coupled to the input node 150 of ILRO 130 through conductor 163.The vibration node 166 of ILRO 162 is coupled to the input node 151 of ILRO 142 through conductor 164.

ILRO 162 receives vibration input signal I1+ via conductor 131, and carries out division arithmetic about 130 argumentations of ILRO with two pairs of frequencies like preceding text.ILRO 162 with differential output signal LO be output as be present on the output node 165 through the oscillator signal LO+ of frequency reducing division arithmetic be present in the oscillator signal LO-on the output node 166 through the frequency reducing division arithmetic.Owing on the conductor 163 the LO+ signal is being sent to the input voltage node 150 of ILRO 130, on conductor 164, the LO-signal is being sent to the input voltage node 151 of ILRO 142 from node 166 from node 165, ILRO 130 and LRO 142 time controls are in the opposite phase of input signal LO.ILRO 130 receives vibration input signal LO+, carry out division arithmetic with two pairs of frequencies, and output is through oscillator signal I+, the I-of frequency reducing division arithmetic.Similarly, ILRO 142 receives vibration input signal LO-, carry out division arithmetic with two pairs of frequencies, and output is through oscillator signal Q+, the Q-of frequency reducing division arithmetic.Signal I+, I-, Q+ and Q-are quadrature on phase place.Because ILRO 162 carries out first frequency division arithmetics and ILRO 130 with two and carries out the subsequent frequencies division arithmetics with 142 with two, therefore carries out division arithmetic like frequency divider 113 depicted in figure 10 with four pairs of frequencies.In a similar manner, can carry out division arithmetic by N, wherein N is 2 power.For instance, can in series dispose Y ILRO, the ILRO receiving inputted signal I1+ of wherein said serial ILRO, and the last ILRO of said serial ILRO output through the differential signal of frequency reducing division arithmetic to drive ILRO 130 and 142.Among Y ILRO each is carried out the frequency division arithmetics with two.ILRO 130 and ILRO 142 carry out last division arithmetic with two, and produce four output signals of quadrature on the phase place.Perhaps, second embodiment of frequency divider 113 can be used as the last ILRO of said serial ILRO, and all four output signals of quadrature can be exported by single ILRO on the phase place.

Figure 11 explains the frequency divider 113 among the 4th embodiment.In this example, frequency divider 113 comprises ILRO130 and ILRO 142.As in Figure 11, describing, ILRO 130 and ILRO 142 be as described in Fig. 6, yet, comprise additional element in this example.ILRO 130 comprises transistor 174 and 175.The source-coupled of the source electrode of transistor 174 and transistor 175 is to first lead-in wire of current source 180.Second lead-in wire of current source 180 is coupled to circuit supply-voltage source VSS.The grid of transistor 174 is via exchanging the vibration node 160 that (AC) coupling capacitor 172 is coupled to ILRO 130.AC coupling capacitor 172 is through setting size stopping direct current (DC) offset voltage signal, and high frequency (interchange) AC voltage signal is passed through.Similarly, AC coupling capacitor 173 arrives the gate coupled of transistor 175 the vibration node 161 of ILRO130.The drain coupled of transistor 174 is to the vibration node 146 of ILRO 142.Owing to be coupled, so current source 180, transistor 174 and resistor 182 are operating as the inverting amplifier of the voltage signal at the grid place that is present in transistor 174.The drain coupled of transistor 175 is to the vibration node 147 of ILRO 142.Owing to be coupled, so current source 180, transistor 175 and resistor 183 are operating as the inverting amplifier of the voltage signal at the grid place that is present in transistor 175.ILRO 142 comprises transistor 178 and 179.The source-coupled of the source electrode of transistor 178 and transistor 179 is to first lead-in wire of current source 181.Second lead-in wire of current source 181 is coupled to circuit supply-voltage source VSS.The grid of transistor 178 is via exchanging the vibration node 170 that (AC) coupling capacitor 176 is coupled to ILRO 142.AC coupling capacitor 176 is through setting size stopping direct current (DC) offset voltage signal, and high frequency (interchange) AC voltage signal is passed through.Similarly, AC coupling capacitor 177 arrives the gate coupled of transistor 179 the vibration node 171 of ILRO142.The drain coupled of transistor 179 is to the vibration node 140 of ILRO 130.Owing to be coupled, so current source 181, transistor 179 and resistor 138 are operating as the inverting amplifier of the voltage signal at the grid place that is present in transistor 179.The drain coupled of transistor 178 is to the vibration node 141 of ILRO 130.Owing to be coupled, so current source 181, transistor 178 and resistor 139 are operating as the inverting amplifier of the voltage signal at the grid place that is present in transistor 178.

As about second embodiment institute note, signal Q+ is present on the vibration node 160 of ILRO 130.This signal transmits through AC coupling capacitor 172, and also amplifies through the anti-phase that is used for of current source 180, transistor 174 and resistor 182, to produce the voltage signal 188 through anti-phase.Signal Q-on composite signal 188 and the vibration node 146 that is present in ILRO 142.Through making up these signals at vibration node 146 places, existing two transistors at the state that exchanges vibration node 146 places.This situation increases the conversion rates of the voltage signal at vibration node 146 places.In addition, the voltage status at vibration node 146 places is just through driving via the in-phase signal LO+ of ILRO 130 and inversion signal LO-via ILRO 142.Similarly, signal Q-is present in vibration node 161 places of ILRO 130.This signal transmits through AC coupling capacitor 173, and through current source 180, transistor 175 and resistor 183 be used for anti-phase and amplifying, with the vibration node 147 that is present in ILRO 142 on signal Q+ coupling.In a similar manner, the vibration node 140 of ILRO 130 and 141 cross-couplings are to ILRO 142.Through the node cross-couplings ILRO of

place

130 and 142 that vibrates at each, phase noise is able to reduce, and the device mismatch is reduced the adverse effect of quadrature in phase accuracy, and big capacity load can drive through frequency divider 113 under given supply of current.

Figure 12 is the flow chart according to the method 200 of a novel aspect.Injection locking ring type oscillator (ILRO) 130 latchs (step 201) and is present in the voltage on the first node of ILRO 130 in response to digital high input signal value.During latch mode, the N channel transistor that electric current is flowed through and is coupled to first node, said electric current equal the resistance value of circuit supply voltage VDD divided by the loading resistor that is coupled to first node substantially.In an example, electric current 134 is showed among Fig. 7 A.In another example, be present in voltage on the first node in 100 millivolts of circuit ground VSS.

Next (step 202), ILRO 130 makes the voltage status that is present on the first node switch to second voltage status in response to digital low input-signal value.During switching state, the voltage that is present on the first node comes stored charge to increase through crossing over integrating condenser.In an example, step 202 is showed among Fig. 7 B.In another example, second voltage status is in 50 millivolts of circuit supply voltage VDD.

In one or more example embodiment, can hardware, software, firmware or its any combination implement described function.If implement with software, so said function can be used as one or more instructions or code and is stored on the computer-readable media or via computer-readable media launches.Computer-readable media comprises computer storage media may and communication medium, communication medium comprise promotion with computer program from one be sent to another place any medium.Medium can be can be by any useable medium of general or special-purpose computer access.Through instance and unrestricted; This type of computer-readable media can comprise RAM, ROM, EEPROM, CD-ROM or other optical disk storage apparatus, disk storage device or other magnetic storage device, or can be used for carrying or storage be instruction or data structure form the program code devices of wanting and can be by any other medium general or special-purpose computer or general or application specific processor access.And, can any connection be called computer-readable media rightly.For instance; If use coaxial cable, Connectorized fiber optic cabling, twisted-pair feeder, digital subscribe lines (DSL); Or for example wireless technologys such as infrared ray, radio and microwave from the website, server or other remote source emission software; Coaxial cable, Connectorized fiber optic cabling, twisted-pair feeder, DSL so, or for example wireless technologys such as infrared ray, radio and microwave are included in the definition of medium.As used herein; Disk (Disk) and CD (disc) comprise compact disc (CD), laser-optical disk, optics CD, digital versatile disc (DVD), floppy discs and Blu-ray Disc; Wherein disk reproduces data with magnetic means usually, and CD reproduces data with laser with optical mode.Above-mentioned each person's combination also should be included in the scope of computer-readable media.

In an illustrative example, the set of processor executable 191 is stored in the memory (processor readable media) 192 in the digital baseband integrated circuit 103 of Fig. 2.Processor 190 is crossed over bus access memories 192, and executes instruction 191, causes the frequency divider 113 in the reception chain 108 of integrated circuit 103 configurations and control and monitoring RF transceiver integrated circuit 102 whereby.

Although preceding text have been described some specific embodiment from the purpose that instructs, the teaching of this patent documentation has general applicability and is not limited to the described specific embodiment of preceding text.For instance, in the application's case will with two carry out division arithmetic frequency divider be described as injection locking ring type oscillator, but frequency divider can be another injection locked oscillator.Therefore, can under the situation of the scope that does not depart from appended claims, put into practice the various characteristics of described specific embodiment various modifications, adjust and make up.

Claims

1. frequency divider, it comprises:

The first injection locking ring type oscillator ILRO, it comprises:

The first cross-linked transistor is right; It comprises a N channel transistor and the 2nd N channel transistor; The drain electrode of a wherein said N channel transistor is first output node; The drain electrode of wherein said the 2nd N channel transistor is second output node, and the gate coupled of a wherein said N channel transistor is to said second output node, and the gate coupled of wherein said the 2nd N channel transistor is to said first output node;

First capacitor, second lead-in wire that it has first lead-in wire of the source electrode that is coupled to a said N channel transistor and is coupled to the source electrode of said the 2nd N channel transistor; And

The first electric current injection circuit, its have the said source electrode that is coupled to a said N channel transistor first lead-in wire, be coupled to second lead-in wire and the first input node of the said source electrode of said the 2nd N channel transistor.

2. frequency divider according to claim 1; The input signal that wherein has first frequency is present on the said first input node of the said first electric current injection circuit; The output signal that wherein has second frequency is present between said first and second output node of a said ILRO, and wherein said first frequency is the twice of said second frequency.

3. frequency divider according to claim 1, the wherein said first electric current injection circuit comprises:

The 3rd N channel transistor; It has source electrode, drain and gate; The said drain coupled of wherein said the 3rd N channel transistor is to the said source electrode of a said N channel transistor, and the said gate coupled of wherein said the 3rd N channel transistor is to the said first input node of the said first electric current injection circuit; And

The 4th N channel transistor; It has source electrode, drain and gate; The said drain coupled of wherein said the 4th N channel transistor is to the said source electrode of said the 2nd N channel transistor, and the said gate coupled of wherein said the 4th N channel transistor is to the said first input node of the said first electric current injection circuit.

4. frequency divider according to claim 1, it further comprises:

The second injection locking ring type oscillator ILRO, it comprises:

The second cross-linked transistor is right; It comprises the 3rd N channel transistor and the 4th N channel transistor; The drain electrode of wherein said the 3rd N channel transistor is the 3rd output node; The drain electrode of wherein said the 4th N channel transistor is the 4th output node, and the gate coupled of wherein said the 3rd N channel transistor is to said the 4th output node, and the gate coupled of wherein said the 4th N channel transistor is to said the 3rd output node;

Second capacitor, second lead-in wire that it has first lead-in wire of the source electrode that is coupled to said the 3rd N channel transistor and is coupled to the source electrode of said the 4th N channel transistor; And

The second electric current injection circuit, its have the said source electrode that is coupled to said the 3rd N channel transistor first lead-in wire, be coupled to second lead-in wire and the second input node of the said source electrode of said the 4th N channel transistor.

5. frequency divider according to claim 4; Wherein differential input signal is present in said second the importing between the node of said first input node and the said second electric current injection circuit of the said first electric current injection circuit; Wherein homophase (I) differential output signal is present between said first and second output node of a said ILRO, and wherein quadrature (Q) differential output signal is present between the said the 3rd and the 4th output node of said the 2nd ILRO.

6. frequency divider according to claim 1; Wherein input signal is present on the said first input node of the said first electric current injection circuit; Wherein homophase (I) differential output signal is present between said first and second output node, and wherein quadrature (Q) differential output signal is present between the said source electrode of said source electrode and said the 2nd N channel transistor of a said N channel transistor.

7. frequency divider according to claim 1, it further comprises:

The second injection locking ring type oscillator ILRO, it has second input node, the 3rd output node and the 4th output node; And

The 3rd injection locking ring type oscillator ILRO; It has the 3rd input node, the 5th output node and the 6th output node; Said the 5th output node of wherein said the 3rd ILRO is coupled to the said first input node of a said ILRO, and said the 6th output node of wherein said the 3rd ILRO is coupled to the said second input node of said the 2nd ILRO.

8. frequency divider according to claim 7; The input signal that wherein has first frequency is present on said the 3rd input node of said the 3rd ILRO; Homophase (I) differential output signal that wherein has second frequency is present between said first and second output node of a said ILRO; Wherein quadrature (Q) differential output signal is present between the said the 3rd and the 4th output node of said the 2nd ILRO, and wherein said first frequency is four times of said second frequency.

9. frequency divider according to claim 4, a wherein said ILRO further comprises:

The 5th N channel transistor; It has source electrode, drain and gate; The said drain coupled of wherein said the 5th N channel transistor is to said the 3rd output node of said the 2nd ILRO, and the said grid of wherein said the 5th N channel transistor exchanges the said source electrode that the AC coupling capacitor is coupled to a said N channel transistor via first;

The 6th N channel transistor; It has source electrode, drain and gate; The said drain coupled of wherein said the 6th N channel transistor is to said the 4th output node of said the 2nd ILRO; The said grid of wherein said the 6th N channel transistor exchanges the said source electrode that the AC coupling capacitor is coupled to said the 2nd N channel transistor via second, and the said source-coupled of the said source electrode of wherein said the 5th N channel transistor and said the 6th N channel transistor is to current source.

10. frequency divider according to claim 3, it further comprises:

First loading resistor, it has first lead-in wire and second lead-in wire, and said first lead-in wire of wherein said first loading resistor is coupled to said first output node;

Second loading resistor; It has first lead-in wire and second lead-in wire; Said first lead-in wire of wherein said second loading resistor is coupled to said second output node; And said second lead-in wire of said second lead-in wire of wherein said first loading resistor and said second loading resistor is coupled to the supply voltage node, and the said source-coupled of the said source electrode of said the 3rd N channel transistor of wherein said electric current injection circuit and said the 4th N channel transistor is to the ground connection node.

11. a frequency divider, it comprises:

The first injection locking ring type oscillator ILRO; It has first input lead that receives first oscillator signal with first frequency, first output lead and second output lead that output has homophase (I) differential output signal of second frequency; Wherein said first frequency is the twice of said second frequency, and wherein said ILRO comprises:

Cross-linked transistor is right; It comprises a N channel transistor and the 2nd N channel transistor; The drain coupled of a wherein said N channel transistor is to said first output lead, and the drain coupled of wherein said the 2nd N channel transistor is to said second output lead;

Capacitor, second lead-in wire that it has first lead-in wire of the source electrode that is coupled to a said N channel transistor and is coupled to the source electrode of said the 2nd N channel transistor; And

The electric current injection circuit; It has the said source electrode that is coupled to a said N channel transistor first lead-in wire, be coupled to said the 2nd N channel transistor said source electrode second lead-in wire and be coupled to the 3rd lead-in wire of said first input lead of a said ILRO.

12. frequency divider according to claim 11, it further comprises:

The 2nd ILRO; It has the structure of the structure that is equal to a said ILRO substantially; It has second input lead that receives second oscillator signal, the 3rd output lead and the 4th output lead of output orthogonal (Q) differential output signal; Wherein said first oscillator signal and said second oscillator signal are differential input signal, and wherein said homophase (I) signal and about 90 degree of said quadrature (Q) signal out-phase.

13. a method, it comprises:

The voltage that will be present in response to the digital high state of first input signal on first output node of the first injection locking ring type oscillator ILRO is latched into first voltage status, wherein equals circuit supply voltage substantially divided by the flow through N channel transistor of a said ILRO of the electric current of the first loading resistor value; And

The said voltage that will be present on said first output node in response to the low state of numeral of said first input signal switches to second voltage status, and the said voltage that wherein is present on said first output node increases through crossing over the first capacitor stored charge.

14. method according to claim 13; Wherein circuit ground voltage and said circuit supply voltage are fed to a said ILRO; And wherein said first voltage status is in 100 millivolts of said circuit ground voltage, and said second voltage status is in 50 millivolts of said circuit supply voltage.

15. method according to claim 13, it further comprises:

The voltage that will be present in response to the said digital high state of said first input signal on second output node of a said ILRO is latched into said second voltage status, wherein flow through the 2nd N channel transistor of a said ILRO of no current substantially; And

The said voltage that will be present on said second output node in response to the low state of said numeral of said first input signal switches to said first voltage status, and the said voltage at the wherein said second output node place reduces through crossing over the said first capacitor stored charge.

16. method according to claim 15, a wherein said ILRO is the part of frequency divider circuit.

17. method according to claim 15, it further comprises:

Reception is present in said first output node of a said ILRO and the differential output signal between said second output node.

18. method according to claim 15, it further comprises:

Latch the voltage on voltage and the 4th output node that is present in said the 2nd ILRO on the 3rd output node that is present in the 2nd ILRO in response to the digital high state of second input signal; And

Switch the said voltage on said voltage and said the 4th output node that is present in said the 2nd ILRO on said the 3rd output node that is present in said the 2nd ILRO in response to the digital high state of said second input signal, wherein said first input signal and the said second input signal out-phase about 180 is spent.

19. method according to claim 18, it further comprises:

Latch the voltage on voltage and the 6th output node that is present in said the 3rd ILRO on the 5th output node that is present in the 3rd ILRO in response to the digital high state of the 3rd input signal; And

Switch the said voltage on said voltage and said the 6th output node that is present in said the 3rd ILRO on said the 5th output node that is present in said the 3rd ILRO in response to the digital high state of said the 3rd input signal; Wherein said the 5th output node is fed to a said ILRO with said first input signal, and said the 6th output node is fed to said the 2nd ILRO with said second input signal.

20. method according to claim 18, it further comprises:

Make the voltage signal anti-phase on the tertiary voltage node that is present in a said ILRO, produce voltage signal whereby through anti-phase; And

Said voltage signal through anti-phase is transmitted into said first output node of said the 2nd ILRO.

21. a frequency divider circuit, it comprises:

Conductor, it receives first input signal on the said frequency divider circuit; And

Be used for said input signal being carried out the device that the frequency division arithmetic produces homophase (I) differential output signal whereby with fixed integer; Wherein said device comprises first capacitor, and wherein said first capacitor increases the voltage swing of said I differential output signal at least in part.

22. frequency divider circuit according to claim 21; Wherein said device is injection locking ring type oscillator ILRO; Wherein said ILRO comprises that cross-linked transistor is right; Said transistor is to comprising a N channel transistor and the 2nd N channel transistor, and first lead-in wire of wherein said first capacitor is coupled to the source electrode of a said N channel transistor, and second lead-in wire of said first capacitor is coupled to the source electrode of said the 2nd N channel transistor.

23. frequency divider circuit according to claim 21, it further comprises:

Second conductor; It receives second input signal on the said frequency divider circuit; Wherein said first input signal and said second input signal are differential input signal, and wherein said device carries out the frequency division arithmetic to said second input signal, produce quadrature (Q) differential output signal whereby; And wherein said device also comprises second capacitor, and wherein said second capacitor increases the voltage swing of said Q differential output signal at least in part.