CN102480852B - Method for manufacturing circuit boards - Google Patents
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- CN102480852B CN102480852B CN201010553786.1A CN201010553786A CN102480852B CN 102480852 B CN102480852 B CN 102480852B CN 201010553786 A CN201010553786 A CN 201010553786A CN 102480852 B CN102480852 B CN 102480852B
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Abstract
The invention discloses a method for manufacturing circuit boards, which includes steps of manufacturing conductive layers and product holes on the circuit boards while manufacturing a plurality of via holes and pads in non-product areas of the circuit boards, forming a path between the via holes and the welding trays, and judging electric conductance performance of the conductive layers and the product holes in the product areas of the circuit boards by testing conductive conditions of the path formed between the via holes and the pads, wherein the via holes in different layers are communicated to each other. Accordingly, destructive test to the circuit boards can be avoided, and performance of the via holes for electroplating of the circuit boards can be judged simply and conveniently.
Description
Technical field
The present invention relates to circuit board technology field, particularly a kind of manufacture method of circuit board.
Background technology
Printed circuit board (PCB) is widely applied because having packaging density advantages of higher.Application about high-density interconnected circuit board refers to document Takahashi, A.O oki, N.Nagai, A.Akahoshi, H.Mukoh, A.Wajima, M.Res.Lab, High density multilayer printed circuit board for HITAC M-880, IEEE Trans.on Components, Packaging, and Manufacturing Technology, 1992,15 (4): 418-425.
In recent years, along with improving constantly of circuit board density, aperture, interlayer conduction hole is also more and more less.Conventionally after completing, circuit board making all can carry out the conduction of circuit board to carry out sampling Detection.Currently used method generally is to be randomly drawed a certain amount of sample number and does slicing experiment at ad-hoc location in a collection of product.So, circuit board is carried out to destructive testing, not only lose the circuit board of test passes, be also difficult to the conduction of testing every circuit board accurately.
Summary of the invention
Therefore, be necessary to provide a kind of manufacture method of circuit board, to electroplate conduction between testing circuit flaggy easily.
A kind of circuit board manufacturing method, comprise step: provide the circuit board that is formed with internal layer circuit, described circuit board is divided into He Fei product zone, product zone, described product zone forms the first line layer, described non-product zone forms a plurality of the first pads and many first connecting lines, described in each, the two ends of the first connecting line are connected between the first adjacent pad, and each first pad is only connected with first connecting line.The first line layer and first pad pressing the first copper foil base material at circuit board, form the second line layer and with a plurality of and the first pad the second pad one to one, and form the first holes of products of a plurality of connection the first line layers and the second line layer, and in the non-product zone of correspondence, forming the first via at formation the first holes of products simultaneously, each first via connects mutually corresponding the first pad and the second pad.Pressing the 5th copper foil base material on the second line layer and the second pad, in corresponding the first outer holes of products and the first outer-layer circuit of forming of product area, described the first outer holes of products is communicated with the first outer-layer circuit and described the second line layer, at corresponding the first outer layer pad and the 3rd connecting line of forming of non-product area, described the first outer layer pad is corresponding one by one with the first pad, the 3rd connecting line is connected between the first adjacent outer layer pad, and in non-product zone, form a plurality of the first outer vias when forming the first outer holes of products, make can form and connect all the first outer vias between two the first outer layer pad that are not connected by the 3rd connecting line, remaining first outer layer pad, all the second pads, the path of all the first vias and all the first pads.And test the situation that conducts between described two the first outer layer pad that are not connected by the 3rd connecting line, judge the conducting situation between the first outer-layer circuit, the first outer holes of products, the second line layer, the first holes of products and the first line layer.
The manufacture method of the circuit board of the technical program, when the product of circuit board removes to make conductive layer and holes of products, in the non-product zone of circuit board, make several vias and the pad of conducting layer by layer, and design and between all vias and pad, form a path, by forming a path between test conduction hole and pad, obtain conducting situation, the conductive layer forming with decision circuitry panel products region and holes of products conduct performance.Thereby, can avoid circuit board to do destructive testing the performance of the via of the deduction circuit board electroplating of mode that just can be easy.
Accompanying drawing explanation
Fig. 1 is the floor map of the internal layer double-sided PCB that provides of the technical program embodiment.
Fig. 2 be Fig. 1 along II-II profile.
Fig. 3 is that pressing the first copper foil base material and the second copper foil base material that the technical program embodiment provides forms the floor map after circuit.
Fig. 4 is that Fig. 3 is along the profile of IV-IV.
Fig. 5 is the technical program embodiment press fit of circuit boards the 3rd copper foil base material and the 4th copper foil base material that provide and forms the profile after circuit.
Fig. 6 is the technical program embodiment press fit of circuit boards the 5th copper foil base material and the 6th copper foil base material that provide and forms the floor map after circuit.
Fig. 7 be Fig. 6 along VII-VII profile.
Main element symbol description
Circuit board 100
Non-product zone 102
The first line layer 111
The first pad 130
The first connecting line 131
The 4th line layer 121
The first copper foil base material 201
The second line layer 202
The first holes of products 203
The first via 204
The second pad 205
The second copper foil base material 301
The 5th line layer 302
Three products hole 303
The 3rd via 304
The 5th pad 305
The second copper foil base material 401
The second holes of products 403
The second via 404
The 3rd pad 405
The 3rd copper foil base material 501
The 6th line layer 502
Four-product hole 503
The 4th via 504
The 6th pad 505
The first outer copper foil base material 601
The first outer-layer circuit 602
The first outer holes of products 603
The first outer via 604
The first outer layer pad 605
The second connecting line 610
The first testing weld pad 611
The second testing weld pad 612
The second outer five copper foil base materials 701
The second outer-layer circuit 702
The second outer holes of products 703
The second outer via 704
The second outer layer pad 705
The 4th connecting line 711
Embodiment
The manufacture method of circuit board the technical program being provided below in conjunction with a plurality of drawings and Examples is described in further detail.
Step 1, sees also Fig. 1 and Fig. 2, and an inner layer circuit board 100 that is formed with conducting wire is provided.
In the present embodiment, the double-layer circuit board that is formed with conducting wire is inner layer circuit board, take to adopt described double-layer circuit board to make 8-layer printed circuit board to describe as example.Circuit board 100 comprises the 101He Fei product zone, product zone 102 adjoining each other, and the boundary of definition 101He Fei product zone, product zone 102 is cross surface 105.Set the Width that the direction parallel with cross surface 105 is circuit board 100, the length direction that the direction vertical with cross surface 105 is circuit board.Circuit board 100 comprises insulating barrier 150, the first line layer 111 and the 4th line layer 121.Insulating barrier 150 has relative first surface 110 and second surface 120.First surface 110, the four line layers 121 that the first line layer 111 is formed at insulating barrier are formed at the second surface 120 of insulating barrier.Meanwhile, the first surface 110 in non-product zone 102 forms several the first pads 130 and the first connecting line 131, and second surface 120 forms several the 4th pads 140 and the 3rd connecting line (not shown).The first pad 130 and the 4th pad 140 are arranged in array.In the present embodiment, the first pad 130 and the 4th pad 140 all form 3 rows on the Width of circuit board, form in the longitudinal direction 6 and are listed as the 4th pad 140.Often ranked first pad 130 connects between two on Width, and each first pad 130 is only connected with its adjacent first pad 130, be that 6 the first pads 130 of same row are along its bearing of trend, between first first pad 130 and second the first pad 130, between the 3rd the first pad 130 and the 4th the first pad 130 and be connected with the first connecting line 131 between the 5th the first pad 130 and the 6th the first pad 130.The arrangement mode of the 4th pad 140 and the 3rd connecting line is consistent with the first pad 130 and the first connecting line 131.Between the number of the first pad 130 and the 4th pad 140 and the circuit board number of plies and board layer, the number of via is relevant, when the number of plies of circuit board more, the number in interlayer conduction hole is more, and the number of the first pad 130 and the 4th pad 140 is also just more, be generally tens to hundreds of not etc.
Step 2, see also Fig. 3 and Fig. 4, first line layer 111 pressing the first copper foil base materials 201 at the first surface 110 of inner layer circuit board 100, form the second line layer 202 and the first holes of products 203, and form the first vias 204 in the non-product zone 102 of correspondence.At the 4th line layer 121 pressing the second copper foil base materials 301 of second surface 120, and form the 5th line layer 302 and three products hole 303, and form the 3rd via 304 in the non-product zone 102 of correspondence.
First, first surface 110 pressing the first copper foil base material 201, the first copper foil base materials 201 at inner layer circuit board 100 comprise insulating substrate and copper foil layer.The insulating substrate of the first copper foil base material 201 is contacted with first surface 110.Secondly, at the first copper foil base material 201, form a plurality of the first holes of products 203 and the first via 204.The aperture of the first via 204 is consistent with the aperture of the first holes of products 203.The first holes of products 203 is formed in product zone 101, and needs the region of conducting corresponding with conducting wire.The first via 204 is formed at non-product zone 102, and each first via 204 is all corresponding with first pad 130.Again, described copper foil layer is being carried out to image transfer technique and etch process, forming the second line layer 202 and a plurality of the second pad 205 being separated from each other.The second pad 205 is formed at the non-product zone 102 of circuit board 100, the number of the second pad 205 is relation one to one with first pad 130 numbers phase the second pads 205 and each the first pad 130 with each second pad 205, and each first pad 130 and each second pad 205 place, center of circle straight line are perpendicular to first surface 110 place planes.Finally, the while also adopts identical technological parameter to electroplate conductting layer at the first holes of products 203 and the interior formation of the first via 204, and each first pad 130 is connected by the first via 204 with the second corresponding with it pad 205.Corresponding the first line layer 111 and the second line layer 202 of connecting of each the first holes of products 203.
Second surface 120 pressing the second copper foil base material 301, the second copper foil base materials 301 at circuit board 100 comprise insulating substrate and copper foil layer.The insulating substrate of the second copper foil base material 301 is contacted with second surface 120.Secondly, at the second copper foil base material 301, form a plurality of three products hole 303 and the 3rd via 304.The aperture of the 3rd via 304 is consistent with the aperture in three products hole 303.Three products hole 303 is formed in product zone 101, and needs the region of conducting corresponding with the second line layer 202.The 3rd via 304 is formed at non-product zone 102, and each the 3rd via 304 is all corresponding with the 4th pad 140.Again, described copper foil layer is being carried out to image transfer technique and etch process, forming the 5th line layer 302 and a plurality of the 5th pad 305 being separated from each other.The 5th pad 305 is formed at the non-product zone 102 of circuit board 100, the number of the 5th pad 305 equates with the 4th pad 140 numbers, the 5th pad 305 and each the 4th pad 140 are relation one to one, and each the 5th pad 305 and each the 4th pad 140 place, center of circle straight line are perpendicular to second surface 120 place planes.Finally, in three products hole 303 and the interior formation of the 3rd via 304, electroplate conductting layer, each the 4th pad 140 is connected by the 3rd via 304 with the 5th corresponding with it pad 305.Corresponding the 4th line layer 121 and the 5th line layer 302 of connecting in each three products hole 303.
Step 3, refers to Fig. 5, with reference to the technique of step 2, at surperficial pressing the second copper foil base material 401 of the second line layer 202, and forms tertiary circuit layer 402 and the second holes of products 403, and forms the second via 404 in the non-product zone 102 of correspondence.The second line layer 202 and tertiary circuit layer 402 are communicated with by the second holes of products 403.In the corresponding non-product zone 102 of the second copper foil base material 401, there are independently 3 rows 6 corresponding with the second pad 205 and be listed as the 3rd pad 405.The second pad 205 is communicated with by the second via 404 with the 3rd pad 405.The aperture of the second via 404 is consistent with the aperture of the second holes of products 403.
Surperficial pressing the 3rd copper foil base material 501 at the 5th line layer 302, forms the 6th line layer 502 and four-product hole 503, and forms the 4th via 504 in the non-product zone 102 of correspondence.The aperture of the 4th via 504 is consistent with the aperture in four-product hole 503.And in the non-product zone 102 of the 3rd copper foil base material 501 correspondences, there are corresponding with the 5th pad 305 independently 3 rows 6 and be listed as the 6th pad 505.The 5th pad 305 is communicated with by the 4th via 504 with the 6th pad 505.
In production practices, because the number of plies of product is different, this step can repeatedly be carried out.Be understandable that, when making 6 layer circuit board, also can not comprise this step.
Step 4, refer to Fig. 6 and Fig. 7, surperficial pressing the first outer copper foil base material 601 at tertiary circuit layer 402,101 corresponding the first outer holes of products 603 and the first outer-layer circuit 602 of forming in product zone, the first outer holes of products 603 is for being communicated with the first outer-layer circuit 602 and tertiary circuit layer 402, at corresponding a plurality of the first outer layer pad 605, the second connecting line 610, the first testing weld pad 611 and the second testing weld pad 612 of forming in non-product zone 102.And forming a plurality of the first outer vias 604, each first outer via 604 correspondence is communicated with first outer layer pad 605 and the 3rd pads 405.And at outer five copper foil base materials 701 of surperficial pressing second of the 6th line layer 502, form the outer holes of products 703 of the second outer-layer circuit 702 and the second outer holes of products 703, the second and be communicated with the second outer-layer circuit 702 and the 6th line layers 502.And forming the second outer via 704, the second outer layer pad 705, the 4th connecting line 711, the 3rd testing weld pad and the 4th testing weld pad in the non-product zone 102 of correspondence, the second outer via 704 is communicated with the second outer layer pad 705 and the 6th pad 505.
At the surperficial pressing first outer copper foil base material 601 of tertiary circuit layer 402, and in corresponding product zone, form the first outer-layer circuit 602 and the first outer holes of products 603.In the non-product zone 102 of correspondence, also form a plurality of the first outer vias 604, a plurality of the first outer layer pad 605, many second connecting lines 610, the first testing weld pad 611 and the second testing weld pads 612, place, the center of circle straight line of each the first outer layer pad 605 and each the first pad 130 is perpendicular to first surface 110.Each first outer via 604 is consistent with the aperture of each the first outer holes of products 603.The relation one to one that presents of each the first outer layer pad 605 and each the 3rd pad 405.Between each first outer layer pad 605 and each the 3rd pad 405, rely on the first outer via 604 to be communicated with.The first outer layer pad 605 with the arrangement of the first pad 130 consistent, also present 3 rows' 6 row.Its arrangement mode is, first first outer layer pad 605 of first row connects first testing weld pads 611, and any one first outer layer pad 605 is not connected with other.Two the first outer layer pad 605 of residue of first row are connected by the second connecting line 610.Answer in contrast, last first outer layer pad 605 of the 3rd row connects the second testing weld pad 612, and any one first outer layer pad 605 is not connected with other.Two the first outer layer pad 605 of residue of first row are electrically connected to.Two the first outer layer pad 605 of the 6th row residue are connected by the second connecting line 610.Remaining the first outer layer pad 605 of every row connects between two on Width, and each first outer layer pad 605 is only connected by the second connecting line 610 with first outer layer pad 605.
At outer five copper foil base materials 701 of surperficial pressing second of the 6th line layer 502, and 101 form the second outer-layer circuit 702 and the second outer holes of products 703 in corresponding product zone.In the non-product zone 102 of correspondence, also form several the second outer vias 704, several the second outer layer pad 705, many articles of the 4th connecting lines 711, the 3rd testing weld pad (not shown) and the 4th testing weld pad (not shown), place, the center of circle straight line of each the second outer layer pad 705 and each the first pad 130 is perpendicular to first surface 110.The second outer holes of products 703 is consistent with the aperture of the second outer via 704.The relation one to one that presents of each the second outer layer pad 705 and each the 4th pad 140.Between each second outer layer pad 705 and each the 6th pad 505, rely on the second outer via 704 to be communicated with.The second outer layer pad 705 with the arrangement of the first outer layer pad 605 consistent, also present 3 rows' 6 row.First second outer layer pad 705 of first row is connected with the 3rd testing weld pad, and any one second outer layer pad 705 is not connected with other.Two the second outer layer pad 705 of residue of first row are connected by the 4th connecting line 711.Answer in contrast, the 3rd last second outer layer pad 705 of row is connected with the 4th testing weld pad, and any one second outer layer pad 705 is not connected with other.Two the second outer layer pad 705 of residue of first row are connected by the 4th connecting line 711.Two the second outer layer pad 705 of residue of the 6th row are connected by the 4th connecting line 711.Remaining the second outer layer pad 705 of every row connects between two on Width, and each second outer layer pad 705 is only connected with each second outer layer pad 705.
So far, when in circuit board making process, the accurate and thru-hole electroplating of contraposition is good, between the first testing weld pad 611 and the second testing weld pad 612, can be interconnected by the outer via 604 of the first outer layer pad 605, first, the 3rd pad 405, the second via 404, the second pad 205, the first via 204 and the first pad 130.Between the 3rd testing weld pad and the 4th testing weld pad, can be interconnected by the outer via 704 of the second outer layer pad 705, second, the 6th pad 505, the 4th via 504, the 5th pad 305, the 3rd via 304 and the 4th pad 140.
Step 5, to carrying out testing electrical property between the first testing weld pad 611 and the second testing weld pad 612, with the conduction property of holes of products in decision circuit plate.
Due in every one deck via is being made by identical process conditions with holes of products simultaneously, therefore, the conduction property that the conduction property of via can reactor product hole.By test between the first testing weld pad 611 and the second testing weld pad 612 the performance that electrically conducts, can judge the conducting situation between the first line layer 111, the first holes of products 203, the second line layer 202, the second holes of products 403, the outer holes of products 603 of tertiary circuit layer 402, first and the first outer-layer circuit 602.By test conduction property between the 3rd testing weld pad and the 4th testing weld pad can judge the 4th line layer 121, the three products holes 303, the 5th line layer 302, four-product hole 503, the outer holes of products 703 of the 6th line layer 502, second and the second outer-layer circuit 702 conduction property.If electrically conduct and can infer the equal conducting of electroplating hole between board layer between the first testing weld pad 611 and the second testing weld pad 612, if electrically not conducting between two testing weld pads illustrates that between board layer, electroplating hole exists poor plating phenomenon.
Be understandable that, distributing order at the pad of each line layer, and not only stick to arranging that the present embodiment provides, as long as after reaching circuit board and completing, be understandable that, the mode that the first connecting line 131 in the first outer layer pad 605 or the first pad 130 or the connected mode of the second connecting line 610 are not limited to provide in the present embodiment, as long as can form unique between the first testing weld pad 611 and the second testing weld pad 612 and be communicated with the first all outer layer pad 605 according to design, the first outer via 604, the 3rd pad 405, the second via 404, the second pad 205, the first via 204 and the first pad 130 paths.When not being provided with the first testing weld pad 611 and the second testing weld pad 612, formation can and be communicated with other all the one the first outer vias 604 of outer layer pad 605, first, the 3rd pad 405, the second via 404, the second pad 205, the first via 204 and the first pad 130 paths together with the unique of two the first outer layer pad 605.The first holes of products 203, the second holes of products 403 and the first outer holes of products 603 also can be located along the same line, can be by being arranged at the direct mutual conduction in conducting wire between the first holes of products 203, the second holes of products 403 and the first outer holes of products 603.
The manufacture method of the circuit board of the technical program, when the product of circuit board removes to make conductive layer and holes of products, in the non-product zone of circuit board, make several vias and the pad of conducting layer by layer, and design and between all vias and pad, form a path, by forming a path between test conduction hole and pad, obtain conducting situation, the conductive layer forming with decision circuitry panel products region and holes of products conduct performance.Thereby, can avoid circuit board to do destructive testing the performance of the via of the deduction circuit board electroplating of mode that just can be easy.
Be understandable that, for the person of ordinary skill of the art, can make other various corresponding changes and distortion by technical conceive according to the present invention, and all these change and distortion all should belong to the protection range of the claims in the present invention.
Claims (10)
1. a manufacture method for circuit board, comprises step:
The circuit board that is formed with internal layer circuit is provided, described circuit board is divided into He Fei product zone, product zone, described product zone forms the first line layer, described non-product zone forms a plurality of the first pads and many first connecting lines, described in each, the two ends of the first connecting line are connected between the first adjacent pad, and each first pad is only connected with first connecting line;
The first line layer and first pad pressing the first copper foil base material at circuit board, form the second line layer and with a plurality of and the first pad the second pad one to one, and form the first holes of products of a plurality of connection the first line layers and the second line layer, and in the non-product zone of correspondence, forming the first via at formation the first holes of products simultaneously, each first via connects mutually corresponding the first pad and the second pad;
Pressing the first outer copper foil base material on the second line layer and the second pad, in corresponding the first outer holes of products and the first outer-layer circuit of forming of product area, described the first outer holes of products is communicated with the first outer-layer circuit and described the second line layer, at corresponding the first outer layer pad and the second connecting line of forming of non-product area, described the first outer layer pad is corresponding one by one with the first pad, the 3rd connecting line is connected between the first adjacent outer layer pad, and in non-product zone, form a plurality of the first outer vias when forming the first outer holes of products, make can form and connect all the first outer vias between two the first outer layer pad, remaining first outer layer pad, all the second pads, the path of all the first vias and all the first pads, and test the situation that conducts between described the first outer layer pad, judge the conducting situation between the first outer-layer circuit, the first outer holes of products, the second line layer, the first holes of products and the first line layer.
2. the manufacture method of circuit board as claimed in claim 1, it is characterized in that, when forming the first outer layer pad, also be formed with the first testing weld pad and the second testing weld pad, described two the first outer layer pad are connected respectively the first testing weld pad or the second testing weld pad, when testing, the conducting property of testing between described the first testing weld pad and the second testing weld pad is judged the conducting situation between the first outer-layer circuit, the first outer holes of products, the second line layer, the first holes of products and the first line layer.
3. the manufacture method of circuit board as claimed in claim 1, is characterized in that, the aperture of described the first holes of products equates with the aperture of the first via.
4. the manufacture method of circuit board as claimed in claim 1, it is characterized in that, before the second line layer and second land side pressing the first outer copper foil base material, the second line layer and second pad pressing the second copper foil base material at circuit board, form tertiary circuit layer and with a plurality of and the first pad the 3rd pad one to one, and form the second holes of products of a plurality of connection tertiary circuit layers and the second line layer, and in the non-product zone of correspondence, form the second via at formation the second holes of products simultaneously, each second via connects mutually corresponding the second pad and the 3rd pad.
5. the manufacture method of circuit board as claimed in claim 4, is characterized in that, described the second holes of products is consistent with the aperture of described the second via.
6. the manufacture method of circuit board as claimed in claim 1, it is characterized in that, the side that described inner layer circuit board is relative with the first line layer also has the 4th line layer that is positioned at described product zone and the 4th pad that is positioned at non-product zone, the manufacture method of described circuit board is also included in described the 4th line layer and the 4th pad pressing the 3rd copper foil base material, form the 5th line layer and with a plurality of and the 4th pad the 5th pad one to one, and form the three products hole of a plurality of connections the 4th line layer and the 5th line layer, and forming non-product zone formation three via of three products hole while in correspondence, each the 3rd via connects mutually corresponding the 4th pad and the 5th pad, pressing the second outer copper foil base material on the 5th line layer and the 5th pad, in corresponding the second outer holes of products and the second outer-layer circuit of forming of product area, described the second outer holes of products is communicated with the second outer-layer circuit and described the 5th line layer, at corresponding the second outer layer pad and the 3rd connecting line of forming of non-product area, described the second outer layer pad is corresponding one by one with the 5th pad, the 3rd connecting line is connected between the second adjacent outer layer pad, and in non-product zone, form a plurality of the second outer vias when forming the second outer holes of products, make can form and connect all the second outer vias between two the second outer layer pad that are not connected by the 3rd connecting line, remaining second outer layer pad, all the second pads, the path of all the second vias and all the second pads.
7. the manufacture method of circuit board as claimed in claim 6, it is characterized in that, described two the second outer layer pad that are not connected by the 3rd connecting line also connect respectively the 3rd testing weld pad and the 4th testing weld pad, and the conducting property of testing between described the 3rd testing weld pad and the 4th testing weld pad is judged the conducting situation between the second outer-layer circuit, the second outer holes of products, the 5th line layer, the second holes of products and the 4th line layer.
8. the manufacture method of circuit board as claimed in claim 6, it is characterized in that, the circuit board of described internal layer circuit also has the 4th line layer that is positioned at described product zone and the 4th pad that is positioned at non-product zone, pressing the second outer copper foil base material on the 4th line layer and the 4th pad, in corresponding the second outer holes of products and the second outer-layer circuit of forming of product area, described the second outer holes of products is communicated with the second outer-layer circuit and described the 4th line layer, at corresponding the second outer layer pad and the 3rd connecting line of forming of non-product area, described the second outer layer pad is corresponding one by one with the 4th pad, the 3rd connecting line is connected between the second adjacent outer layer pad, and in non-product zone, form a plurality of the second outer vias when forming the second outer holes of products, make can form and connect all the second outer vias between two the second outer layer pad that are not connected by the 3rd connecting line, remaining second outer layer pad, all the second pads, the path of all the second vias and all the second pads.
9. the manufacture method of circuit board as claimed in claim 8, it is characterized in that, described two the second outer layer pad that are not connected by the 3rd connecting line also connect respectively the 3rd testing weld pad and the 4th testing weld pad, and the conducting property of testing between described the 3rd testing weld pad and the 4th testing weld pad is judged the conducting situation between the second outer-layer circuit, the second outer holes of products, the 4th line layer.
10. the manufacture method of circuit board as claimed in claim 4, is characterized in that, described the first holes of products and the second holes of products are directly interconnected.
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| CN201010553786.1A CN102480852B (en) | 2010-11-22 | 2010-11-22 | Method for manufacturing circuit boards |
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| CN201010553786.1A CN102480852B (en) | 2010-11-22 | 2010-11-22 | Method for manufacturing circuit boards |
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| CN102480852B true CN102480852B (en) | 2014-02-05 |
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| JP2008135585A (en) * | 2006-11-29 | 2008-06-12 | Hitachi Ltd | STRUCTURE OF INSPECTION PATTERN FOR INSPECTING POSITIONAL DEVIATION OF Via HOLE OF PRINTED WIRING BOARD |
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| CN1392418A (en) * | 2001-06-19 | 2003-01-22 | 华通电脑股份有限公司 | Detection method for missing curcuit board wire |
| CN101341414A (en) * | 2005-12-30 | 2009-01-07 | 美光科技公司 | Connection verification technique |
| CN101459155A (en) * | 2007-12-12 | 2009-06-17 | 三星电子株式会社 | Circuit board having bypass pad |
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Cited By (2)
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| CN107548229A (en) * | 2016-06-27 | 2018-01-05 | 中兴通讯股份有限公司 | PCB and its manufacture method |
| CN107548229B (en) * | 2016-06-27 | 2022-01-28 | 中兴通讯股份有限公司 | PCB and manufacturing method thereof |
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|---|---|
| CN102480852A (en) | 2012-05-30 |
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