CN102480447B - Correction apparatus of time series data of receiver and method thereof - Google Patents
Correction apparatus of time series data of receiver and method thereof Download PDFInfo
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- CN102480447B CN102480447B CN201010568262.XA CN201010568262A CN102480447B CN 102480447 B CN102480447 B CN 102480447B CN 201010568262 A CN201010568262 A CN 201010568262A CN 102480447 B CN102480447 B CN 102480447B
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Abstract
The invention relates to a correction apparatus of time series data of a receiver and a method thereof. The correction apparatus comprises a clock data recovery (CDR) unit and a weight calculating unit. The CDR unit receives and carries out processing on a compensation signal of an equalization filter so as to generate an error signal, a sampling clock signal, a transition sampling signal and a data signal; the weight calculating unit receives the error signal, the sampling clock signal, the transition sampling signal and the data signal as well as utilizes a run length technology to carry out weight calculation so as to generate weight data; and the weight data are output and a voltage control clock circuit is controlled, so that a phase and frequency of the sampling clock signal are adjusted.
Description
Technical field
The present invention relates to a kind of receiver apparatus, particularly about a kind of receiver time series data means for correcting and method.
Background technology
The framework of general communication system, please refer to Fig. 1, its comprise transmitter 101, channel 102, with receiver equalization device 103, wherein, receiver equalization device 103 comprises: equalization filter 110 and clock and data recovery unit 120 (Clock Data Recovery unit, CDR unit).Wherein, equalization filter 110 is in order to receive channel signal VR and be compensated for as compensating signal X, and CDR unit 120 is in order to receive compensating signal X outputting data signals Z and sampled clock signal CLK.
Clock and data recovery of the prior art unit 120, in the time that data occur to change, ignore the interdependence (data dependent) of data, just similarly go sampled clock signal CLK to tune up or slow down, so on the contrary may be by incorrect CLK of correct CLK furnishing, the speed that also can make CLK adjust is slack-off.Moreover, when channel signal VR is by serious interference, equalization filter 110 is compensate for channel signal VR fully, and make the signal of compensating signal X imperfect, CDR unit 120 receives this incomplete compensating signal X, and serious skew or losing lock are occurred to for phase place and the frequency of the CLK that makes CDR unit 120.At this moment, when equalization filter 110 receives normal channel signal VR and produces compensating signal X, CDR of the prior art unit 120 still utilizes phase place and the frequency of the CLK being offset sample and obtain sampled data compensating signal X repeatedly, and arithmetic logic unit in CDR unit 120 utilizes sampled data to carry out computing, and incremental phase place and the frequency that obtains normal CLK little by little, and it cannot be adjusted rapidly.And when the circuit because generation noise jamming in CDR unit 120, and cause CLK that serious skew or losing lock occur, then, in the time that CDR unit recovers normal, CDR of the prior art unit also cannot be made correction fast and adjust the phase place of CLK and frequency.
Summary of the invention
The invention provides a kind of receiver time series data means for correcting, utilize length coding technology (runlength) to carry out weight calculation, to solve the problem of known technology.
One of object of the present invention is to provide a kind of receiver time series data means for correcting, and it comprises: clock and data recovery unit and weight calculation unit.Wherein, clock and data recovery unit couples equalization filter, in order to receive compensating signal and to produce sampled clock signal, data-signal, error signal and conversion sampled signal; Weight calculation unit couples clock and data recovery unit, also carries out weight calculation according to this and produces weight data in order to receive error signal and data-signal; Wherein, sampled clock signal is adjusted according to weight data in clock and data recovery unit.
Another object of the present invention is to provide a kind of method that receiver time series data is proofreaied and correct, and comprises following steps: receive compensating signal to produce sampled clock signal, data-signal, error signal and conversion sampled signal; Carry out weight calculation according to this error signal, conversion sampled signal and data-signal, to produce weight data; And, adjust sampled clock signal according to weight data.
For above and other objects of the present invention, feature and advantage can be become apparent, several preferred embodiments cited below particularly, and coordinate appended accompanying drawing, be described in detail below:
Brief description of the drawings
Fig. 1 is the functional block diagram of communication system;
Fig. 2 is the functional block diagram of the receiver time series data means for correcting of communication system;
Fig. 3 is the first embodiment of the weight calculation unit of receiver time series data means for correcting;
Fig. 4 is the second embodiment of the weight calculation unit of receiver time series data means for correcting;
Fig. 5 is data-signal and the sequential chart of changing sampled signal; And
Fig. 6 is the method flow diagram of receiver time series data means for correcting.
Primary clustering symbol description
10,11,12 latch lock unit (trigger) 13,14 XOR gate
15 adder 16 low pass filters (LPF)
17 voltage-controlled oscillators (VCO), 21 length coding devices
The balanced determining device of 22 arithmetic calculator 23
101 transmitter 102 channels
103 receiver equalization devices
105 receiver time series data means for correcting 110 equalization filters
120 clock and data recovery unit 130 weight calculation unit
200 communication systems
Embodiment
Please refer to Fig. 2, it is the functional block diagram of the time series data means for correcting of explanation communication system of the present invention.Wherein, the receiver time series data means for correcting 105 of communication system 200 comprises: clock and data recovery unit 120 and weight calculation unit 130.The signal transmission VX that transmitter 101 transmits becomes channel signal VR after channel 102.Channel signal VR is compensated for as compensating signal X through equalization filter 110.Clock and data recovery unit 120 couples equalization filter 110, in order to process compensating signal X, and produces error signal E, sampled clock signal CLK, conversion (transition) sampled signal S and data-signal Z.And weight calculation unit 130 couples CDR unit 120, in order to receive error signal E and data-signal Z (Fig. 3 embodiment), or receive conversion sampled signal S, error signal E and data-signal Z (Fig. 4 embodiment), and utilize calculating that length coding technology carries out weight to produce weight data we, and adjust phase place and the frequency of CLK according to these weight data we.
The present invention, by the weight calculation unit 130 providing, utilizes the mode of length coding computing to improve the problem of prior art.The binary sequence number of for example compensating signal X is 1111011111, getting its latter half of sequence number 011111 at this illustrates, it is that a and the second coded data are b that length coding computing first defines first coding data, if with the length (length coding value) of the continuous low level of [a b] representative data conversion front and back and the length coding (run length) of continuous high level, its run length is specially [1 5].In practice, find that the result (abs (a-b)) that a deducts b and take absolute value is larger, if clock and data recovery unit 120 has produced preferably phase place and the frequency of CLK, now, CDR unit 120 more should not go to adjust phase place and the frequency of CLK.And in the time that a equals b (a=b) (receive continuous binary sequence number be 01010101,001100110011,000111000111,0000111100001111 etc.), because it contains the better degree of discrimination (waveform that is also signal 1 and 0 is more symmetrical), can adjust to rapidly phase place and the frequency of good CLK by sequence number now.If taking 000111 as example, a equals 3, and b equals that 3, a deducts b and the result that takes absolute value is zero (abs (3-3)=0), utilizes this result to go to adjust phase place and the frequency of CLK, by preferably phase place and the frequency of CLK of being easy to get.
Below, the embodiment of two receiver time series data means for correctings will be enumerated respectively.
Please refer to Fig. 3, it illustrates the first embodiment of the weight calculation unit 130 of receiver time series data means for correcting 105 of the present invention.Wherein, the weight calculation unit 130 of receiver time series data means for correcting 105 comprises: length coding device 21 and arithmetic calculator 22.Wherein, CDR unit 120 couples equalization filter 110, carries out computing produce error signal E, conversion sampled signal S, data-signal Z and CLK in order to the data that receive compensating signal X and according to CLK, compensating signal X is sampled.Length coding device 21 couples clock and data recovery unit 120, is first coding data a and the second coded data b in order to encoded data signal Z.Arithmetic calculator 22 couples length coding device 21, in order to receive error signal E, first coding data a and the second coded data b, and carries out the calculating of arithmetic and produces weight data we to CDR unit 120.Wherein, the forward position of CLK produces signal Y to compensating signal X sampling, and the rear edge of CLK produces data-signal Z to signal Y sampling.XOR gate 13 receives compensating signal X and signal Y and produces signal U, and XOR gate 14 receives signal Y and data-signal Z and produce signal D, and adder 15 will provide error signal E after signal U subtraction signal D.
For example one: tentation data signal Z (00001111) inputs to length coding device 21, and length coding device 21 utilize length coding technology data-signal is encoded and produce a be 4 with b be 4.Now, the operational formula of arithmetic calculator 22 is:
We=(max_run_length-abs (a-b)) * E ... formula 1
Wherein, length coding maximum (max_run_length) is default length coding value, predeterminable is 5, after formula 1 (we=(5-abs (4-4)) * E) computing, will make weight data we=5E, and its weight is 5.These weight data we=5E is delivered to CDR unit 120, and weight data we=5E will export low pass filter 16 to filter away high frequency noise and control voltage-controlled oscillator (VCO) 17.Computing via formula 1 learns, in the time that a equals b, its weight data we is 5E, represents to contain preferably weight data we in the binary sequence number 00001111 of this data-signal Z.Utilize this preferably weight data we remove to control voltage-controlled oscillator 17, will make the voltage-controlled oscillator 17 of CDR unit 120 can adjust to rapidly phase place and the frequency of correct CLK.
For example two: tentation data signal Z (011111) inputs to length coding device 21, and length coding device 21 data-signal Z is encoded and produce a be 1 with b be 5.Arithmetic calculator 22 is tried to achieve weight data we=(5-abs (1-5)) * E by formula 1 computing, weight data we=1E, and its weight is 1.These weight data we=1E is delivered to CDR unit 120, and weight data we=1E first exports low pass filter 16 to filter away high frequency noise and controls voltage-controlled oscillator (VCO) 17.Via formula 1 learn when a be 1 and b while being 5, its weight data we is 1E, represents not contain preferably weight data we in the binary sequence number 00001111 of this data-signal Z.These weight data we can only adjust voltage-controlled oscillator (VCO) 17 slightly, in practice even as long as first coding data a deducts the second coded data b and the result difference that takes absolute value is excessive, can not adjust voltage-controlled oscillator 17 (VCO), in order to avoid change too large and then cause the phase place of CLK and frequency that serious shift phenomenon occurs because adjusting.
Then, please refer to Fig. 4, it illustrates the second embodiment of the weight calculation unit 130 of receiver time series data means for correcting 105 of the present invention.Wherein, the difference of the second embodiment of the weight calculation unit 130 of Fig. 4 and the first embodiment of Fig. 3 is that it has added balanced determining device 23 and assisted weight calculation unit 130 to judge the situation of the CLK of CDR unit 120.Wherein, the weight calculation unit 130 of receiver time series data means for correcting 105 comprises: length coding device 21, balanced determining device 23 and arithmetic calculator 22.Wherein, clock and data recovery unit 120 couples equalization filter 110, in order to receive compensating signal X and to produce error signal E, conversion sampled signal S, data-signal Z and CLK.Length coding device 21 couples clock and data recovery unit 120, is first coding data a and the second coded data b in order to encoded data signal Z.Balanced determining device 23 couples clock and data recovery unit 120, in order to judge fading channel overcompensation (over EQ) according to conversion sampled signal S and data-signal Z, or channel attenuation compensation deficiency (under EQ), to produce a balanced judged result.Arithmetic calculator 22 couples length coding device 21, balanced determining device 23, in order to receive error signal E, balanced judged result, conversion sampled signal S, data-signal Z, first coding data a and the second coded data b and to carry out algorithm calculations, to produce weight data we and to export clock and data recovery unit 120 to.
Wherein, balanced determining device 23 can be a digital accumulator, changes sampled signal S and data-signal Z and judges the situation into over EQ or under EQ now, and produce two kinds of balanced judged results in order to accumulative total is multiple.Wherein, the first equalization data in balanced judged result represents the situation of over EQ, and the second equalization data in balanced judged result represents the situation of under EQ.Common balanced determining device 23 is in order to accumulative total dozens of or hundreds of above conversion sampled signal S and data-signal Z, and judged that the compensating signal X that present receive channel signal VR compensates via equalization filter 110 is over EQ or under EQ.
Then, Fig. 5 is data-signal Z and the sequential chart of changing sampled signal S.If CDR unit 120 be input as compensating signal X
n, be output as sampled clock signal CLK
n, conversion sampled signal S
nwith data-signal Z
n.Wherein, conversion sampled signal S
nfor sampled clock signal CLK
n-1in rear along time to compensating signal X
nthe obtained signal of sampling, and S
n-1represent sampled clock signal CLK
n-2in rear along time to compensating signal X
n-1the obtained signal of sampling.Now, data-signal Z
nfor clock signal clk
n-1during for forward position to compensating signal X
nsample and recycle sampled clock signal CLK
n-1in rear along time the obtained signal of again sampling, and Z
n-1represent sampled clock signal CLK
n-2during for forward position to compensating signal X
n-1sample and utilize sampled clock signal CLK
n-2for rear along time the obtained signal of again sampling.
When the CLK of CDR unit 120 is under state preferably, or CLK is at sampled point preferably, and now the judgment mode of Over EQ is: be greater than zero and S if first coding data a deducts the second coded data b
n-1equal Z
n-1or first coding data a deducts the second coded data b and is less than zero and S
n-1equal Z
n, i.e. { [(a-b > 0) & (S
n-1=Z
n-1)] or[(a-b < 0) & (S
n-1=Z
n)], compensating signal X is Over EQ; And the judgment mode of Under EQ is: be less than zero and S if a deducts b
n-1equal Z
n-1or a deducts b and is greater than zero and S
n-1equal Z
n, i.e. { [(a-b < 0) & (S
n-1=Z
n-1)] or[(a-b > 0) & (S
n-1=Z
n)], compensating signal X is Under EQ.
If under the Rule of judgment of above-mentioned Over EQ, balanced determining device 23 but judges to be now Under EQ (the second equalization data in balanced judged result), or under the Rule of judgment of above-mentioned Under EQ, balanced determining device 23 but judges to be now Over EQ (the first equalization data in balanced judged result), the CLK that represents CDR unit 120 is now not under state preferably, but have grave error or losing lock, need carry out at once the adjustment of high weight.Its running is as follows: arithmetic calculator 22 can carry out according to first coding data a, the second coded data b, the first equalization data, the second equalization data, conversion sampled signal S and data-signal Z the related operation of the Rule of judgment of above-mentioned Over EQ or Under EQ, and make comparisons with the judged result of balanced determining device 23, and then the CLK of CDR unit 120 instantly of judgement is whether at state preferably, or there are grave error or losing lock; If there is grave error CDR unit, must carry out the correction (calibration) of high weight.Correlation formula and condition are as follows:
If (first equalization data is true & { [(a-b < 0) & (S
n-1=Z
n-1)] or[(a-b > 0) & (S
n-1=Z
n)] is true) condition 2
calibration＝max_run_length
We=max (max_run_length-abs (a-b), calibration) * E ... formula 2
Else if (second equalization data is true & { [(a-b > 0) & (S
n-1=Z
n-1)] or[(a-b < 0) & (S
n-1=Z
n)] is true) condition 3
calibration＝max_run_length
We=max (max_run_length-abs (a-b), calibration) * E ... formula 3
Else condition 4
calibration＝0
We=max (max_run_length-abs (a-b), calibration) * E ... formula 4
From above-mentioned correlation formula and condition, the second embodiment of the present invention is under the condition of the formula 1 of the first embodiment, if add determination methods and the Fast Correction mechanism thereof of (but grave error or losing lock in the situation that) not under state preferably as the CLK of CDR unit 120.
For example one: tentation data signal Z binary sequence number is 011001111100 to input to length coding device 21, wherein, the number of the 4th later continuous 0 is 2, that is, first coding data a is that the number of 2, the 6 later continuous 1 is 5, that is, the second coded data b is 5, and length coding maximum (max_run_length) is set as 5.And condition 2 is true, the first equalization data is that the Rule of judgment of true and Under EQ is also true, so represent that arithmetic calculator 22 judges the situation for channel attenuation compensation deficiency instantly, but the result that balanced determining device 23 is judged by past data is the contradictory phenomena of fading channel overcompensation.Therefore, if condition 2 is set up, there is serious deviation in phase place and the frequency of the CLK of representative CDR unit 120 instantly, now must give maximum corrected value (calibration), allows it adjust rapidly and recover normal, and now corrected value is 5.Now formula 2 is calculated as max (5-abs (2-5), 5) * E, its representative: it is 3 that first coding data a (being 2) deducts the result taking absolute value after the second coded data b (being 5), it is 2 that recycling length coding maximum (max_run_length) (being 5) deducts 3 result, again with corrected value 5 relatively, get the two in maximum (max).So it is 5E that arithmetic calculator 22 obtains weight data we, its weight is 5, then is that 5E delivers to CDR unit 120 and carries out the adjustment of CLK with rapid adjustment voltage-controlled oscillator (VCO) 17 by weight data we, to obtain preferably phase place and frequency.
For example two: tentation data signal Z binary sequence number is 011001111100 to input to length coding device 21, and wherein, a is that 2, b is that 5, max_run_length is set as 5.And the condition 4 in arithmetic calculator 22 is set up (representing that condition 2 and condition 3 are all false).Now, calibration=0, is calculated as max (5-abs (2-5) according to formula 4,0) * E, so it is 2E that arithmetic calculator 22 obtains weight data we, its weight is 2, then is that 2E delivers to CDR unit 120 to carry out the adjustment of phase place and frequency of CLK by weight data we.Wherein, weight data we is that 2E representative needs only and adjusts a little VCO17 now, can obtain phase place and the frequency of more suitable CLK.
For example three: tentation data signal Z binary sequence number is 0110000111100 to input to length coding device 21, and wherein, a is that 4, b is that 4, max_run_length is set as 5.And the condition 4 in arithmetic calculator 22 is set up (representing that condition 2 and condition 3 are all false).Now, calibration=0, is calculated as max (5-abs (4-4) according to formula 4,0) * E, so it is 5E that arithmetic calculator 22 obtains weight data we, its weight is 5, then is that 5E delivers to clock and data recovery unit 120 by weight data we.Wherein, weight data we is that 5E represents in compensating signal X and contains the better degree of discrimination, and clock and data recovery unit 120 can utilize compensating signal X to carry out computing, and utilizes the result of computing to allow VCO17 adjust rapidly phase place and the frequency of CLK.As long as receive that continuous binary sequence number is 01010101,001100110011,000111000111,0000111100001111 etc. so run into), can adjust rapidly phase place and the frequency of CLK.
The parameter and the numerical value thereof that note that above-mentioned formula and condition are not particularly limited, parameter select and the practical application of the setting visible system of numerical values recited is selected and is changed.
Then, please refer to Fig. 6, it is the method flow diagram that receiver time series data of the present invention is proofreaied and correct, and comprises step:
S110: receive compensating signal to produce sampled clock signal, data-signal, error signal and conversion sampled signal.
S120: carry out weight calculation according to error signal, conversion sampled signal and data-signal, to produce weight data.
S130: adjust sampled clock signal according to weight data.
Wherein, conversion sampled signal is sampled to compensating signal on the rear edge of sampled clock signal, and data-signal is sampled and again sampled with the rear edge of sampled clock signal compensating signal in the forward position of sampled clock signal.Wherein, weight calculation is to utilize length coding technology, data-signal is carried out to length coding, so as to producing first coding data and the second coded data, first coding data is that continuous low level binary number and the second coded data are that the binary number of continuous high level or first coding data are that binary number and second coded data of continuous high level is continuous low level binary number.
Although preferred embodiment of the present invention discloses as mentioned above; so it is not in order to limit the present invention; anyly have the knack of related art techniques person; without departing from the spirit and scope of the present invention; when doing a little change and retouching, therefore scope of patent protection of the present invention must be as the criterion depending on the appended claim person of defining of this specification.
Claims (13)
1. a receiver time series data means for correcting, comprises:
One clock data recovery unit, in order to receive a compensating signal and to produce a sampled clock signal, a data-signal, an error signal and a conversion sampled signal; And
One weight calculation unit, couples described clock and data recovery unit, also carries out weight calculation according to this and produces weight data in order to receive described error signal and described data-signal;
Wherein, described sampled clock signal is adjusted according to described weight data in described clock and data recovery unit,
Wherein said weight calculation unit comprises: a length coding device, couple described clock and data recovery unit, be a first coding data and one second coded data in order to the described data-signal of encoding, described first coding data is continuous low level binary number, and described the second coded data binary number that is continuous high level; And an arithmetic calculator, couple described length coding device, described clock and data recovery unit, in order to receive described error signal, described first coding data and described the second coded data, and carry out algorithm calculations to produce described weight data.
2. according to the receiver time series data means for correcting of claim 1, wherein said arithmetic calculator produces a weight of described weight data according to the absolute value of the difference of described first coding data and described the second coded data.
3. according to the receiver time series data means for correcting of claim 2, wherein, when the absolute value of the difference of described first coding data and described the second coded data is larger, described weight is less.
4. according to the receiver time series data means for correcting of claim 2, the absolute value that wherein said arithmetic calculator deducts the difference of described first coding data and described the second coded data according to a length coding value produces described weight.
5. according to the receiver time series data means for correcting of claim 1, wherein said weight calculation unit receives described error signal, described conversion sampled signal and described data-signal also carries out weight calculation according to this and produces described weight data, and described weight calculation unit comprises:
One length coding device, couple described clock and data recovery unit, be a first coding data and one second coded data in order to the described data-signal of encoding, described first coding data is continuous low level binary number, and described the second coded data binary number that is continuous high level;
One balanced determining device, couples described clock and data recovery unit, in order to judge fading channel overcompensation or channel attenuation compensation deficiency according to described conversion sampled signal and described data-signal, to produce a balanced judged result; And
One arithmetic calculator, couple described length coding device, in order to receive described error signal, described balanced judged result, described conversion sampled signal, described data-signal, described first coding data and described the second coded data, and carry out algorithm calculations to produce described weight data.
6. according to the receiver time series data means for correcting of claim 5, wherein said balanced determining device is a digital accumulator, produces according to this described balanced judged result in order to the described conversion sampled signal of accumulative total with described data-signal.
7. according to the receiver time series data means for correcting of claim 5, wherein said arithmetic calculator produces a weight of described weight data according to the absolute value of the difference of described first coding data and described the second coded data.
8. according to the receiver time series data means for correcting of claim 5, wherein said arithmetic calculator produces an equilibrium condition judged result to compare with described balanced judged result according to described conversion sampled signal, described data-signal, described first coding data and described the second coded data, to produce a judged result, and produce a weight of described weight data according to the absolute value of the difference of described judged result and described first coding data and described the second coded data.
9. according to the receiver time series data means for correcting of claim 5, wherein said arithmetic calculator deducts the difference of described first coding data and described the second coded data absolute value according to a length coding value is got large person in both and produces a weight of described weight data again with a corrected value comparison.
10. the method that receiver time series data is proofreaied and correct, comprises following steps:
Receive a compensating signal to produce a sampled clock signal, a data-signal, an error signal and a conversion sampled signal;
Carry out weight calculation according to described error signal, described conversion sampled signal and described data-signal, to produce weight data; And
Adjust described sampled clock signal according to described weight data,
The step of wherein carrying out weight calculation also comprises: the described data-signal of continuous low level binary number is encoded to a first coding data, and the described data-signal of the binary number of continuous high level is encoded to one second coded data.
The method that the 11. receiver time series datas according to claim 10 are proofreaied and correct, the step of wherein carrying out weight calculation also comprises: a weight that produces described weight data according to the absolute value of the difference of described first coding data and described the second coded data.
The method that the 12. receiver time series datas according to claim 10 are proofreaied and correct, the step of wherein carrying out weight calculation also comprises: produce an equilibrium condition judged result to compare with described balanced judged result according to described conversion sampled signal, described data-signal, described first coding data and described the second coded data, to produce a judged result, and produce a weight of described weight data according to the absolute value of the difference of described judged result and described first coding data and described the second coded data.
The method that the 13. receiver time series datas according to claim 10 are proofreaied and correct, the step of wherein carrying out weight calculation also comprises: the absolute value that uses a length coding value to deduct the difference of described first coding data and described the second coded data is got large person in both and produce a weight of described weight data again with a corrected value comparison.
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| CN106302281B (en) * | 2016-08-31 | 2019-08-23 | 硅谷数模半导体（北京）有限公司 | The adaptive equilibrium method and device of receiver |
| CN112019225B (en) * | 2020-08-27 | 2022-07-05 | 群联电子股份有限公司 | Signal receiving circuit, memory storage device and method for calibrating equalizer circuit |
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| CN101771656A (en) * | 2001-06-22 | 2010-07-07 | 汤姆森许可公司 | Method and system for compensating carrier frequency offset in OFDM receiver |
| CN101848007A (en) * | 2009-03-27 | 2010-09-29 | 台湾积体电路制造股份有限公司 | The apparatus and method that are used for the digital adaptive equalizer of serial receiver |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101771656A (en) * | 2001-06-22 | 2010-07-07 | 汤姆森许可公司 | Method and system for compensating carrier frequency offset in OFDM receiver |
| CN101848007A (en) * | 2009-03-27 | 2010-09-29 | 台湾积体电路制造股份有限公司 | The apparatus and method that are used for the digital adaptive equalizer of serial receiver |
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