CN102478763A - Photoetching method - Google Patents
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- CN102478763A CN102478763A CN2010105676582A CN201010567658A CN102478763A CN 102478763 A CN102478763 A CN 102478763A CN 2010105676582 A CN2010105676582 A CN 2010105676582A CN 201010567658 A CN201010567658 A CN 201010567658A CN 102478763 A CN102478763 A CN 102478763A
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Abstract
The invention provides a photoetching method, which comprises: providing a layer to be etched; forming a DBARC layer, a hard mask layer and a photoresist mask in order on the surface of the layer to be etched; taking the photoresist mask as a mask and etching the hard mask layer, the DBARC layer and the layer to be etched in order, and removing the photoresist mask as well as the hard mask layer simultaneously; using a developing solution to remove the DBARC layer. The photoetching mask in the invention employs a DBARC material able to dissolve in a developing solution as a bottom antireflective layer, which can be cleaned and removed directly through the developing solution after etching, thus avoiding damaging a medium on the inner wall of a through hole or groove.
Description
Technical field
The present invention relates to semiconductor fabrication process, relate in particular to a kind of photoetching method.
Background technology
Photoetching technique is the basic processing procedure in the semiconductor fabrication process, is widely used in etching and graphical operation.Basic purpose is the litho pattern on the mask is transferred to mask layer; Generally include following steps: on semiconductor wafer, form photoresist layer; Said photoresist layer is carried out the selectivity exposure, and make the photoresist layer after the exposure further form the photoresist pattern through development step; With the photoresist layer behind the said patterning is mask, and said semiconductor wafer is carried out etching, thus with the figure transfer on the mask to semiconductor wafer.
Along with dwindling day by day of chip feature size, because the exposure reflection problems that optical qualitative difference produced is serious day by day, become the key factor that influences lithography performance between photoresist layer and its following coating.So in order to satisfy the growth requirement of small size photoetching process, generally being employed in the prior art increases bottom antireflective coating (Bottom Anti-Reflective Coating BARC) solves above-mentioned exposure reflection problems under the photoresist layer.The material category that forms BARC has a lot, for example with the organic BARC that is rich in C of organic material manufacturing, perhaps is rich in the Si-BARC of Si, and other inorganic material, for example the formed BARC of SiON etc.About the background technology introduction of BARC, in No. 200810205382.6 disclosed content of one Chinese patent application, can also find more.
Fig. 1 to Fig. 5 has introduced a kind of existing employing and has comprised that the mask of BARC carries out the method for etching.
As shown in Figure 1, semiconductor structure to be etched is provided, comprising: etching stop layer 11 is positioned at said etching stop layer 11 surfaces dielectric layer 12 to be etched.
As shown in Figure 2, form overlayer 13, bottom anti-reflection layer 14 and hard mask layer 15 successively on the surface of said dielectric layer 12.
As shown in Figure 3, at the surface-coated photoresist of said hard mask layer 15, and carry out exposure imaging, form photoresist mask 16.
As shown in Figure 4, be mask with said photoresist mask 16, etch hardmask layer 15, bottom anti-reflection layer 14, overlayer 13, dielectric layer 12 form required through hole or groove until etching stop layer 11 successively.Be generally the saving operation; Can be according to the dielectric layer degree of depth of required etching; The thickness ratio of dielectric layer 12, photoresist mask 16 and hard mask layer 15 is set; Make that photoresist mask 16 and hard mask layer 15 are consumed simultaneously and finish, and only remain bottom anti-reflection layer 14 on dielectric layer 12 surfaces after the said etch step of completion.
As shown in Figure 5, etching is removed said bottom anti-reflection layer 14.
There is following problem in existing photoetching method: existing bottom anti-reflection layer 14 adopts plasma etching industrial to remove usually, and when removing said bottom anti-reflection layer, whole semiconductor structure exposes to the open air under plasma environment.Therefore, shown in Fig. 5 arrow, the sidewall of through hole or groove also receives etching easily and loses certain thickness in the dielectric layer 12, form easily young in big shape.In addition, if the material of dielectric layer 12 is advanced low-k materials black diamond BD, its principal ingredient Si-CH
3 (x)Easily and the oxonium ion in the plasma react and form Si-OH
(x), and form the Si-OH of one deck high-k at the sidewall of through hole or groove
(x)Film is with the electrical property that has a strong impact on semiconductor devices.
Summary of the invention
The object of the invention is to provide a kind of photoetching method, has solved when after etching, removing bottom anti-reflection layer, and the through hole or the medium in the groove that easily etching are formed cause dysgenic problem.
Photoetching method of the present invention comprises:
Layer to be etched is provided;
Form DBARC layer, hard mask layer and photoresist mask successively at said laminar surface to be etched;
With said photoresist mask is mask etch hardmask layer, DBARC layer and layer to be etched successively, and said etching is also removed photoresist mask and hard mask layer simultaneously;
Use developer solution to remove said DBARC layer.
Optional, said layer to be etched comprises etching stop layer and position dielectric layer on it, the material of said dielectric layer is a black diamond, specific inductive capacity 2.2～3.0.
Optional, before forming the DBARC layer, the surface that also is included in said layer to be etched forms overlayer.Said tectal material is ethyl orthosilicate, silicon oxynitride or its combination; Form through chemical vapor deposition, thickness range is
Optional; Said DBARC layer adopts spin coating proceeding to form, and thickness range is
Optional; Said hard mask layer is low-temperature oxidation silicon layer, siliceous anti-reflecting layer or cryogenic nitrogen silicon oxide layer; Form through chemical vapor deposition, thickness range is 170 ℃～250 ℃ for
depositing temperature scope.
Optional; Said photoresist mask forms through spin coating photoresist and exposure imaging, and thickness range is
Mask of the present invention adopts the DBARC material that dissolves in developer solution as bottom anti-reflection layer, and after etching, directly removes through the developer solution cleaning and removing, thereby has avoided the medium of through hole or trench wall is produced damage.
Description of drawings
Through the more specifically explanation of the preferred embodiments of the present invention shown in the accompanying drawing, above-mentioned and other purposes, characteristic and advantage of the present invention will be more clear.The parts identical with prior art have used identical Reference numeral in the accompanying drawing.Accompanying drawing and not drawn on scale focus on illustrating purport of the present invention.In the accompanying drawings for clarity sake, amplified the size of layer with the zone.
Fig. 1 to Fig. 5 is the existing photoetching method diagrammatic cross-section that adopts bottom anti-reflection layer;
Fig. 6 is the diagrammatic cross-section of mask according to the invention;
Fig. 7 is the schematic flow sheet of photoetching method according to the invention;
Fig. 8 to Figure 16 is the diagrammatic cross-section of embodiment of the invention photoetching method.
Embodiment
In existing photoetching process, after etching finishes, when removing bottom anti-reflection layer, damage the dielectric layer that through hole or trench wall expose to the open air easily, the electrical property of device is exerted an adverse impact.The present invention then replaces the material of bottom anti-reflection layer in the mask, and removes the method for bottom anti-reflection layer in the change etching technics, avoids and damage through hole or trench wall.
The mask that photoetching method of the present invention adopted is formed at semiconductor structure surface to be etched, and as shown in Figure 6, basic structure comprises:
Be positioned at the bottom anti-reflection layer 101 on semiconductor structure to be etched 100 surfaces, said bottom anti-reflection layer is the organic antireflective coating material DBARC (Develop Barc) that dissolves in developer solution.
Be positioned at the hard mask layer 102 and the photoresist mask 103 on said bottom anti-reflection layer 101 surfaces, said hard mask layer 102 spacer lithography glue mask 103 and bottom anti-reflection layer 101 make directly not contact between the two.
The schematic flow sheet of photoetching method according to the invention is as shown in Figure 7, and basic step comprises:
Execution in step S101, layer to be etched is provided; The purpose of said etching is, on the figure transfer of lithography mask version layer extremely to be etched.Above-mentioned layer to be etched can comprise the patterned semiconductor medium layer of needs, semiconductor devices and even other complicated semiconductor structures.Usually said layer to be etched should comprise etching stop layer and position dielectric layer on it.Said etching stop layer is used for when the said dielectric layer of etching, playing the effect of etching stopping.
Execution in step S102, form the DBARC layer on the surface of said layer to be etched.Said DBARC layer can be formed at the surface of layer to be etched through the technology of spin coating or spraying, specifically depends on the surface topography of layer to be etched.Preferably, before forming said DBARC layer, can also form overlayer on the surface of layer to be etched, said overlayer is used for when plasma etching industrial, preventing the plasma penetration mask and the non-etch areas of damaging dielectric layer; Be particularly useful for protecting being positioned at mask open dielectric layer on every side, the through hole or the groove that make etching formation, top is smooth vertical.
Execution in step S103, form hard mask layer at said DBARC laminar surface; Said hard mask layer is used for when follow-up making photoresist mask, interval D BARC layer and photoresist, and avoiding in the developing process, developer solution dissolves the DBARC layer.
Execution in step S104, form the photoresist mask on said hard mask layer surface; Said photoresist mask is through the spin coating photoresist, and carries out exposure imaging and form.
Execution in step S105, be mask with said photoresist mask, the said hard mask layer of etching, DBARC layer and dielectric layer successively;
Concrete, in etching process, be termination with the etching stop layer in the layer to be etched, above-mentioned each layer of etching in the opening of photoresist mask., after finishing in etching, laminar surface to be etched only remains the DBARC layer, so that subsequent step chemical development is removed.Can be according to the dielectric layer degree of depth of required etching, the deposit thickness of adjustment hard mask layer and the spin coating thickness of photoresist, make that etching finishes after, hard mask layer and photoresist mask be all by full consumption, and expose said DBARC layer.
Execution in step S106, use developer solution are removed said DBARC layer.Because the DBARC layer promptly dissolves in developer solution at normal temperatures, when the structure after therefore adopting developer solution to above-mentioned etching is cleaned, the DBARC layer will be removed, and the layer to be etched in through hole that etching forms or the groove can't produce reaction with developer solution.Usually also should carry out the cleaning of deionized water, to remove the residue that is produced behind the dissolves DBARC layer.
Below in conjunction with concrete embodiment; The present invention is done further introduction; Though wherein set forth a lot of details so that make much of the present invention; But the present invention can implement much to be different from alternate manner described here, and those skilled in the art can do similar popularization under the situation of intension of the present invention, so the present invention does not receive the restriction of following disclosed practical implementation.
Fig. 8 to Figure 16 is the diagrammatic cross-section of each step of embodiment of the invention photoetching method.
At first as shown in Figure 8, Semiconductor substrate 200 is provided, the interlayer dielectric layer 202 that said Semiconductor substrate 200 surfaces are formed with etching stop layer 201 and are positioned at said etching stopping laminar surface.
Concrete, said Semiconductor substrate 200 is monocrystalline substrate or silicon-on-insulator.Said etching stop layer 201 can be carbon containing silicon nitride SiCN; Contain silicon oxide carbide SiCO or silicon nitride layer; Thickness range is
, and said interlayer dielectric layer 202 is advanced low-k materials; Black diamond for example; Specific inductive capacity is 2.2～3.0, and thickness range is
Suppose present embodiment, need carry out etching, form until the through hole that exposes etching stop layer 201 to interlayer dielectric layer 202.
As shown in Figure 9, form overlayer 203 on the surface of said interlayer dielectric layer 202.
Concrete; The material of said overlayer 203 is ethyl orthosilicate TEOS or silicon oxynitride SiON; Can adopt chemical vapor deposition to form; Said overlayer 203 is used for protective dielectric layer 202 when etching, ion penetration mask damage dielectric layer surface when preventing follow-up plasma etching, and its thickness is unsuitable blocked up; To avoid influencing the speed of etching, thickness range is
Shown in figure 10, form DBARC layer 204 on the surface of said overlayer 203.Said DBARC layer is an organic polymer; Can be at normal temperatures; Be dissolved in developer solution, concrete, can adopt the ARC DS-K101P organic antireflecting material of BrewerScience company; Mode through spin coating or spraying forms, and thickness range is
Shown in figure 11, form hard mask layer 205 on the surface of said DBARC layer 204.The material of said hard mask layer 205 can be cryogenic oxidation silicon layer (LTO), cryogenic nitrogen silicon oxide layer or siliceous anti-reflecting layer.Present embodiment is an example with the low-temperature oxidation silicon layer; Said low-temperature oxidation silicon layer adopts chemical vapor deposition method to form, and deposit thickness is
It is pointed out that the DBARC layer at high temperature decomposes easily, when therefore above-mentioned chemical vapor deposition formed hard mask layer 205, depositing temperature was unsuitable too high.And low excessively depositing temperature causes the rate of sedimentation of hard mask layer 205 slow easily, and composition is loose, when influence is carried out exposure imaging to photoresist to the protection effect of DBARC layer 204.Preferably, the depositing temperature scope of said low-temperature oxidation silicon layer is 170 ℃～250 ℃.
Shown in figure 12, form photoresist 206 on the surface of said hard mask layer 205.Said photoresist 206 can also can be negative glue for positive glue, can adopt spraying or spin coating method to form.In the present embodiment; Said photoresist 206 is positive glue; Adopt spin coating method to be coated on the surface of hard mask layer 205 equably, the thickness range of spin coating is
After forming above-mentioned each layer; Usually the step of baking before also comprising; Under vacuum condition,, heated 30 seconds～60 seconds with 85 degrees centigrade～120 degrees centigrade temperature; Through the organic solvent that uses in residual above-mentioned each the spraying/spin coating method of heated volatile, and the internal stress that strengthens the adhesiveness between each layer and discharge photoresist.
Shown in figure 13, use lithography mask version that photoresist 206 is made public, developing then forms photoresist mask 207.
Usually behind end exposure, also should comprise the step of back baking, under vacuum condition,, heat 30 seconds～60 seconds, can reduce standing wave effect with 110 degrees centigrade～130 degrees centigrade temperature.When adopting developer solution to develop, will comprise above-mentioned semiconductor structure and be immersed in the developer solution, the said developer solution that is applied to positive glue can be TMAH (TMAH).Wherein photoresist 206 part of being made public is with dissolved.Though and DBARC layer 204 is dissolved in developer solution, because the protection of hard mask layer 204 can not contact with developer solution.After the development, use residual developer solution and the photoresist residue of washed with de-ionized water.After clean finishing, can also be aided with hard baking step, the residual organic solvent on the evaporation photoresist mask 207 plays post bake simultaneously and further reduces effect such as standing wave effect.
Shown in figure 14, be mask with said photoresist mask 207, adopt plasma etching industrial, etch hardmask layer 205, DBARC layer 204, overlayer 203, interlayer dielectric layer 202 until exposing etching stop layer 201, form required through hole successively.
Shown in figure 15, after etching finished, said photoresist mask 207 and hard mask layer 205 were consumed and finish, and directly expose DBARC layer 204.In above-mentioned etching process, photoresist mask layer 207 etching spending rates are very fast, and hard mask layer 205 etching spending rates are relatively slow.In order to make above-mentioned two-layer being consumed finish; Except etching depth and each layer etching speed according to interlayer dielectric layer 202 are adjusted the method for each layer thickness; Can also be after etching be exposed etching stop layer 201; Carry out the over etching of certain hour, lightening holes DBARC layer does not simultaneously have photoresist mask layer 207 and hard mask layer 205 residual to guarantee the DBARC laminar surface.
Shown in figure 16, adopt developer solution to remove said DBARC layer.
Concrete, will comprise above-mentioned semiconductor structure and be immersed in the developer solution, said developer solution can with aforementioned when photoresist is developed employed developer solution identical, for example adopt TMAH (TMAH).Because the hard mask layers 204 on DBARC layer 204 surface have been consumed in etching process, so the DBARC layer will directly contact with developer solution, and dissolves.After the DBARC layer dissolves fully, issuable organic detritus when using residual developer solution of washed with de-ionized water and DBARC dissolving.Final completion photoetching method of the present invention.
Visible from the foregoing description, because after the etching end, what remove the employing of DBARC layer is that developer solution cleans.Therefore though through-hole wall also can contact with developer solution in the said interlayer dielectric layer 202, black diamond and developer solution can't react, and can not change surface electrical properties, and sidewall that also can etching through hole causes the loss of thickness.
Though above embodiment is an example with the interlayer dielectric layer of etching low dielectric constant material, the present invention can be applied in other the etching technics equally.For example in metal interconnected during to the etching of metal level, metal material can be removed BARC because of plasma etching equally and sustain damage and produce the cavity of trenched side-wall, also can be suitable for photoetching method of the present invention to avoid the problems referred to above.
Claims (7)
1. a photoetching method is characterized in that, comprising:
Layer to be etched is provided;
Form DBARC layer, hard mask layer and photoresist mask successively at said laminar surface to be etched;
With said photoresist mask is mask etch hardmask layer, DBARC layer and layer to be etched successively, and said etching is also removed photoresist mask and hard mask layer simultaneously;
Use developer solution to remove said DBARC layer.
2. photoetching method as claimed in claim 1 is characterized in that, said layer to be etched comprises etching stop layer and position dielectric layer on it, and the material of said dielectric layer is a black diamond, specific inductive capacity 2.2～3.0.
3. photoetching method as claimed in claim 1 is characterized in that, before forming the DBARC layer, the surface that also is included in said layer to be etched forms overlayer.
4. photoetching method as claimed in claim 3; It is characterized in that; Said tectal material is ethyl orthosilicate, silicon oxynitride or its combination; Form through chemical vapor deposition, thickness range is
5. photoetching method as claimed in claim 1; It is characterized in that; Said DBARC layer adopts spin coating proceeding to form, and thickness range is
6. photoetching method as claimed in claim 1; It is characterized in that; Said hard mask layer is low-temperature oxidation silicon layer, siliceous anti-reflecting layer or cryogenic nitrogen silicon oxide layer; Form through chemical vapor deposition, thickness range is 170 ℃～250 ℃ for
depositing temperature scope.
7. photoetching method as claimed in claim 6; It is characterized in that; Said photoresist mask forms through spin coating photoresist and exposure imaging, and thickness range is
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| CN2010105676582A CN102478763A (en) | 2010-11-30 | 2010-11-30 | Photoetching method |
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| CN2010105676582A CN102478763A (en) | 2010-11-30 | 2010-11-30 | Photoetching method |
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Cited By (9)
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|---|---|---|---|---|
| CN103632928A (en) * | 2012-08-29 | 2014-03-12 | 中芯国际集成电路制造(上海)有限公司 | Self-aligned double patterning formation method |
| CN103832968A (en) * | 2014-03-17 | 2014-06-04 | 上海华虹宏力半导体制造有限公司 | Manufacturing method of MEMS (micro-electro-mechanical system) device |
| CN103902115A (en) * | 2012-12-28 | 2014-07-02 | 深圳欧菲光科技股份有限公司 | Transparent conductor for touch screen and preparing method and application of transparent conductor |
| CN104064450A (en) * | 2013-03-19 | 2014-09-24 | 中芯国际集成电路制造(上海)有限公司 | Manufacturing method for semiconductor device |
| CN104064449A (en) * | 2013-03-19 | 2014-09-24 | 中芯国际集成电路制造(上海)有限公司 | Manufacturing method for semiconductor device |
| CN104555893A (en) * | 2013-10-17 | 2015-04-29 | 上海华虹宏力半导体制造有限公司 | Method for forming induction material membrane in deep groove |
| CN106449378A (en) * | 2016-11-30 | 2017-02-22 | 上海华力微电子有限公司 | Structure and method for improving high aspect ratio photoresist morphology |
| CN110211920A (en) * | 2018-02-28 | 2019-09-06 | 中芯国际集成电路制造(上海)有限公司 | The forming method of semiconductor devices |
| CN113517188A (en) * | 2021-06-29 | 2021-10-19 | 上海华力集成电路制造有限公司 | Patterning process method adopting multi-layer mask plate |
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| CN103902115B (en) * | 2012-12-28 | 2018-04-06 | 深圳欧菲光科技股份有限公司 | Touch-screen transparent conductive body and its preparation method and application |
| CN103902115A (en) * | 2012-12-28 | 2014-07-02 | 深圳欧菲光科技股份有限公司 | Transparent conductor for touch screen and preparing method and application of transparent conductor |
| CN104064450A (en) * | 2013-03-19 | 2014-09-24 | 中芯国际集成电路制造(上海)有限公司 | Manufacturing method for semiconductor device |
| CN104064449A (en) * | 2013-03-19 | 2014-09-24 | 中芯国际集成电路制造(上海)有限公司 | Manufacturing method for semiconductor device |
| CN104555893A (en) * | 2013-10-17 | 2015-04-29 | 上海华虹宏力半导体制造有限公司 | Method for forming induction material membrane in deep groove |
| CN104555893B (en) * | 2013-10-17 | 2017-06-06 | 上海华虹宏力半导体制造有限公司 | The method that inductive material film is formed in deep trench |
| CN103832968B (en) * | 2014-03-17 | 2016-04-13 | 上海华虹宏力半导体制造有限公司 | The manufacture method of MEMS |
| CN103832968A (en) * | 2014-03-17 | 2014-06-04 | 上海华虹宏力半导体制造有限公司 | Manufacturing method of MEMS (micro-electro-mechanical system) device |
| CN106449378A (en) * | 2016-11-30 | 2017-02-22 | 上海华力微电子有限公司 | Structure and method for improving high aspect ratio photoresist morphology |
| CN106449378B (en) * | 2016-11-30 | 2019-05-10 | 上海华力微电子有限公司 | A kind of structures and methods improving high-aspect-ratio photoresist pattern |
| CN110211920A (en) * | 2018-02-28 | 2019-09-06 | 中芯国际集成电路制造(上海)有限公司 | The forming method of semiconductor devices |
| CN113517188A (en) * | 2021-06-29 | 2021-10-19 | 上海华力集成电路制造有限公司 | Patterning process method adopting multi-layer mask plate |
| CN113517188B (en) * | 2021-06-29 | 2024-04-26 | 上海华力集成电路制造有限公司 | Patterning process method using multi-layer mask plate |
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