CN102474481B - Scrambling method and communication apparatus - Google Patents
Scrambling method and communication apparatus Download PDFInfo
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- CN102474481B CN102474481B CN201080031240.8A CN201080031240A CN102474481B CN 102474481 B CN102474481 B CN 102474481B CN 201080031240 A CN201080031240 A CN 201080031240A CN 102474481 B CN102474481 B CN 102474481B
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L25/00—Baseband systems
- H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
- H04L25/03—Shaping networks in transmitter or receiver, e.g. adaptive shaping networks
- H04L25/03828—Arrangements for spectral shaping; Arrangements for providing signals with specified spectral properties
- H04L25/03866—Arrangements for spectral shaping; Arrangements for providing signals with specified spectral properties using scrambling
Abstract
The present invention is directed to transmission of scrambled data in which the data redundancy has been suppressed and which has a bit sequence characteristic suitable for transmission. There are included the steps of: generating, by use of an isochronous scrambler, scrambled data from a reference frame in which a reference value has been added as the header of the reference frame; generating scrambled data of a compared frame in which a value different from the reference value has been added as the header of the compared frame; calculating an evaluation value related to the bit sequence characteristic of each scrambled data; selecting the evaluation value representative of the bit sequence characteristic that is the most suitable for transmission; transmitting the scrambled data of the selected evaluation value; if the scrambled data of the compared frame has been transmitted, correcting the value held by a shift register of the scrambler to a value specified in consideration of the time of completion of the scrambled data of the compared frame; and applying the value as corrected to the reference frame of a new data block.
Description
Technical field
The present invention relates to scrambling (scrambling) technology in communication.
Background technology
In transmission processing during base band in digital communication transmits, the Bit String experience that send processes to meet the DC balance of the balance between the number of indication 0 and 1 and the constraint run length.This processing is called as " line coding (line coding) ".Line coding is roughly divided into two kinds of methods: a kind of is to meet constraint, to carry out coding by adding redundant code; Another kind is by carrying out coding with scrambler to meet randomly constraint.
Front a kind of method based on redundant code with
(Ethernet
) in the Manchester's code or the 8B/10B that use be encoded to representative.When transfer rate surpasses 10 Gbps, redundancy increases, and correspondingly, channel speed likely increases.Therefore, the requirement for sending/receiving equipment becomes strict.For example, in the situation that 8B/10B encodes, for transmit the channel speed of information with 10 Gbps, be 12.5 Gbps, thereby require to have the sending/receiving equipment that can support this channel speed.For the requirement relating in this high-speed communication, it is preferably using rear a kind of coding method of scrambler.
Use the method utilization of scrambler to come randomization to send bit sequence by the pseudo-random number sequence of easy-to-install LFSR (linear feedback shift register) generation.Such method for scrambling is roughly divided into synchronized model and motor synchronizing type.
Synchronous method for scrambling is to realize randomized method by information sequence with from the addition (XOR, XOR) of the pseudo-random number sequence of LFSR.Figure 14 shows according to the synchronous transmit leg scrambler 101 of method for scrambling and the ios dhcp sample configuration IOS DHCP of recipient's scrambler 102.The LFSR of transmit leg scrambler 101 has shift register 103a, and similarly, the LFSR of recipient's scrambler 102 has shift register 103b.The value that these registers (103a, 103b) represent is called as LFSR state.
In this synchronous method for scrambling, between transmit leg (101) and recipient (102), need Complete Synchronization LFSR state.The favourable part of the method is mistake (bit reversal) and can propagate if occurred.Synchronous method for scrambling more than adopting at the SONET of the standard as multiplexed, as CCSDS of the recommendation of satellite communication etc.
Motor synchronizing method for scrambling be by by the output bit storage in past in LFSR and the method with the execution scrambling of information sequence phase Calais from the output of LFSR.Figure 15 shows the ios dhcp sample configuration IOS DHCP of motor synchronizing method for scrambling.Transmit leg scrambler 201 has shift register 203a, and similarly, recipient's scrambler 202 has shift register 203b.If the disadvantage of the method is the mistake such as bit reversal and occurs, can propagate by the number of the connecting line from LFSR, and favourable part is not need to carry out frame synchronization, thereby if there is lock-out, may therefrom recovers.
In addition, motor synchronizing scrambling is favourable with regard to fail safe.As the security threat in scrambling, can consider for example network nuisance of the data of input offset scrambling effect.Assailant selects the initial condition of LFSR to harm sequence to generate at random in the case.Yet, by abundant increase LFSR length, can fully reduce the initial condition probability consistent with actual initial condition that assailant sets.
?
64b/66b coding in use motor synchronizing method for scrambling.64b/66b coding is a kind of like this method: the data sequence that has experienced motor synchronizing scrambling according to generator polynomial g (x)=x^57+x^19+1 be divided into 64 bit data block and add for 2 synchronous bit heads (" 01 " or " 10 ") to the beginning of each data block, thereby form 66 bits, sending frame.
In the line coding based on scrambling, the bit mode of deteriorated communication characteristic is inevitable randomly.As technology related to this, the known for example method of the disclosed CIMT of being called as (Conditional Inversion Master Transition, condition reverse main transformation) in the PTL 1 and 2 listing below.
CIMT method keeps in advance the accumulation of DC balance and calculates the DC balance of the data block that will send.When the polarity of the polarity (direction of balance) of the DC of the data block that will send balance and the DC balance of previous data block is consistent with each other, all bits in the data block that send are all inverted and the piece that reverses is sent out.Otherwise the bit in this data block is sent by its primitive form.The head of now, indicating this piece whether to be inverted is added to this piece.This makes to send bit sequence can be adjusted to better direction of DC balance all the time.
{ quoted passage list }
{ patent documentation }
{ PTL 1} U.S. Patent No. 5,022,051, specification
{ PTL 2} U.S. Patent No. 5,438,621, specification
Summary of the invention
{ technical problem }
According to disclosed method in PTL 1 and 2, can adjust accumulation DC balance; Yet method for scrambling is synchronized model, thereby need to carry out frame synchronization between transmit leg and recipient.In addition, in above method, the mistake in head causes the mistake in whole, thereby requires as disclosed defencive function in PTL 2, and this has increased redundancy.In addition, for complete zero piece or complete one, bit value is just inverted, thereby does not change in the run length in piece, and this makes to be difficult to reduce maximum run length.
Therefore an object of the present invention is to provide a kind of method for scrambling and communicator, for sending data redudancy, obtained suppressing and having the scrambled data of the bit sequence characteristic of the transmission of being suitable for.
{ scheme of dealing with problems }
According to a first aspect of the invention, provide a kind of method for scrambling, having comprised: using fiducial value as head, added the beginning of data block to form reference frame; By using motor synchronizing scrambler to generate the scrambled data of reference frame; By the scrambled data of correction sequence and reference frame being added to generate the scrambled data of comparison frame, in this comparison frame, the value different from fiducial value is used as head and added data block to; According to evaluation criteria, calculate about the assessed value of the bit sequence characteristic of the scrambled data of reference frame with about another assessed value of the bit sequence characteristic of the scrambled data of frame relatively; From the assessed value calculating, select to represent the assessed value of optimum bit sequence characteristic for transmission; When selected assessed value is during corresponding to reference frame, send the scrambled data of reference frame; And when selected assessed value is during corresponding to frame relatively, send by the scrambled data of correction sequence and reference frame being added to the scrambled data obtaining, the value that the shift register of scrambler is preserved is corrected to value definite when considering the completing of scrambled data of comparison frame, and calibrated value is applied to the reference frame of new data block.
According to a second aspect of the invention, provide a kind of communicator, having comprised: head addition portion, this head addition portion is added the beginning of data block to form reference frame using fiducial value as head; Scrambling portion, this scrambling portion is by being used motor synchronizing scrambler to generate the scrambled data of reference frame; Assessment detection unit, this assessment detection unit: by the scrambled data of correction sequence and reference frame being added to generate the scrambled data of comparison frame, the value different from fiducial value is used as head and added data block in this comparison frame; According to evaluation criteria, calculate about the assessed value of the bit sequence characteristic of the scrambled data of reference frame with about another assessed value of the bit sequence characteristic of the scrambled data of frame relatively; From the assessed value calculating, select to represent the assessed value of optimum bit sequence characteristic for transmission; And according to selecting output calibration sequence or null sequence; And adder, this adder is added and sends addition results by the scrambled data of correction sequence or null sequence and reference frame, wherein, when selected assessed value is during corresponding to frame relatively, assessment detection unit offers the result of selection scrambling portion and correction sequence is outputed to adder, and the value that scrambling portion preserves the shift register of scrambler when the result of selecting is sent out is corrected to value definite when considering the completing of scrambled data of comparison frame, and calibrated value is applied to the reference frame of new data block.
{ advantageous effects of the present invention }
According to the present invention, can send the scrambled data that data redudancy has obtained suppressing and having the bit sequence characteristic of the transmission of being suitable for.
Accompanying drawing explanation
Fig. 1 is the block diagram of the communicator in exemplary embodiment of the present invention.
Fig. 2 is the key diagram about the frame format in exemplary embodiment of the present invention.
Fig. 3 is the flow chart about the basic operation of the communicator in exemplary embodiment of the present invention.
Fig. 4 is the ios dhcp sample configuration IOS DHCP of the scrambler with calibration function in exemplary embodiment of the present invention.
Fig. 5 is the ios dhcp sample configuration IOS DHCP of the assessment detection unit in exemplary embodiment of the present invention.
Fig. 6 be about in exemplary embodiment of the present invention in the situation that weighted accumulation DC balance is used as evaluation criteria the flow chart of the operation of detection unit.
Fig. 7 be about in exemplary embodiment of the present invention in the situation that using the first and second evaluation criterias the flow chart of the operation of detection unit.
Fig. 8 be about in exemplary embodiment of the present invention in the situation that using random bit sequence the flow chart of the operation of detection unit.
Fig. 9 be in exemplary embodiment of the present invention in the situation that weighted accumulation DC balance is used as evaluation criteria the block diagram of detection unit.
Figure 10 be in exemplary embodiment of the present invention in the situation that weighted accumulation DC balance is used as evaluation criteria another block diagram of detection unit.
Figure 11 is the diagram about the weighted accumulation DC balance (ρ=0.9) in exemplary embodiment of the present invention.
Figure 12 is the diagram about the weighted accumulation DC balance (ρ=1.0) in exemplary embodiment of the present invention.
Figure 13 is the diagram about the accumulation DC balance of a limited number of frame in exemplary embodiment of the present invention.
Figure 14 is the key diagram about synchronous scrambler.
Figure 15 is the key diagram about motor synchronizing scrambler.
{ label list }
101,201: transmit leg scrambler
102,202: recipient's scrambler
103a, 103b, 203a, 203b: shift register
500: communicator
501: head addition portion
502: the scrambler (scrambling portion) with calibration function
503: buffer
504: assessment detection unit
505: adder
601: corrected value
701: correction sequence generating unit
702a, 702b: assessed value calculating part
703: detection unit
704: selector
1101,1202: register
1102: adder
1103: multiplier
1201: shift register
Embodiment
Fig. 1 shows the configuration of the transmitting system of the communicator 500 in exemplary embodiment of the present invention.Head addition portion 501 is added the scrambling head with fiducial value to each beginning of the fixed-length block obtaining by dividing data, to generate the frame with the structure shown in Fig. 2.
The frame that wherein fiducial value is set to scrambling head is corresponding to reference frame of the present invention.The bit number of scrambling head and fiducial value can be set to any value; In this exemplary embodiment, the bit number of head is set to 1 bit, and fiducial value is set to " 0 ".In the situation that 1 bit scramble head is added to the data block of N bit as in this exemplary embodiment, the redundancy of frame is represented as (N+1)/N.Even in the situation that N is set to 32, the bit number of head is set to 1 bit, and also to make redundancy be 1.03, thus with 1.25 comparing of obtaining in 8B/10B coding, reduced fully redundancy.
The scrambler 502 with calibration function utilize motor synchronizing scrambler to reference frame application scrambling to generate scrambled data T0.The scrambled data T0 generating (bit length: (N+1) bit) be once stored in buffer 503.Scrambler 502, according to the result of determination from after a while the assessment detection unit of describing 504 feedbacks being come, is adjusted being applied to the state of the LFSR of new data block to be processed.
Assessment detection unit 504 calculates the assessed value about the assessed value of data T0 and scrambled data T1 by obtaining as from head to this data block interpolation value (" 1 ") different from fiducial value.Assessed value is for judging whether the bit sequence characteristic of scrambled data plays favourable value to the transmission of data.Scrambled data T1 is corresponding to the scrambled data of the comparison frame that utilizes as described later data T0 to generate.
Assessment detection unit 504 selects to represent that of for transmission optimum bit sequence characteristic from the assessed value of T0 and T1, and carries out control so that the scrambled data of optimum assessed value (T0 or T1) is sent out.
More specifically, when selecting the assessed value of T1,504 outputs of assessment detection unit are after a while by the correction sequence M describing.Correction sequence M is added to form T1 by adder 505 and the output (T0) from buffer 503, and T1 is sent out subsequently.Correction sequence M is the output sequence obtaining in following situation:, it is complete zero that the initial condition of LFSR is set to, and scrambling is applied to and by scrambling head " 1 " is added to, has the frame ((N+1) bit) that the full zero data blocks of bit length N obtains.On the other hand, when selecting the assessed value of T0, assessment detection unit 504 output null sequences (entirely zero).
In addition, 504 of assessment detection units are that T0 or the information of T1 feed back to above-mentioned scrambler 502 as result of determination about being assessed as the scrambled data of optimum assessed value.
With reference to the flow chart shown in figure 3, description is there is to the basic operation of the communicator 500 of above-mentioned configuration.The process of Fig. 3 shows the handling process when processing t data block.The state of LFSR when the processing of the frame to corresponding with t data block starts in scrambler 502 is represented by S (t).
When addition portion 501 from the head receives that wherein scrambling head " 0 " has been added to the reference frame of data block t, scrambler 502 in state S (t) to this reference frame application scrambling to generate scrambled data T0 (step S401).Tentation data block length is N bit, and the total data length of T0 is (N+1) bit.The T0 generating is stored in buffer 503, and is provided for assessment detection unit 504.
Assessment detection unit 504 calculates the assessed value (step S402) of T0 according to predefined evaluation criteria.To the computational methods of assessed value be described after a while.
In addition, assessment detection unit 504 has been added to the frame (relatively frame) of data block t, generation scrambled data T1 (bit length: (N+1) bit) (step S403) among state S (t) based on scrambling head " 1 " wherein.Data T1 is according to after a while the method for description being utilized T0 to generate.Assessment detection unit 504 calculates the assessed value (step S404) of the T1 generating.
After calculating the assessed value of T0 and T1, assessment detection unit 504 compares them and based on evaluation criteria, judges the assessed value that represents optimum bit sequence characteristic.In the situation that the assessed value of T0 is better than the assessed value ("Yes" in S405) of T1, assessment detection unit 504 is carried out and is controlled so that T0 is sent out.That is to say, assessment detection unit 504 is to the full null sequence of adder 505 output N bit.This full null sequence is added with T0 in adder 505, thereby final T0 is sent out (step S406).
Assessment detection unit 504 is showing to have selected the information of the assessed value of the T0 corresponding with head " 0 " to feed back to scrambler 502 as result of determination.In the case, the state of LFSR when scrambler 502 completes T0, current time is stored in the value in LFSR, is familiar with the LFSR state S (t+1) (step S407) for new data block (t+1).
On the other hand, in the situation that the assessed value of T1 is better than the assessed value ("No" in S405) of T0, assessment detection unit 504 is carried out and is controlled so that T1 is sent out.That is to say assessment detection unit 504 output calibration sequence M.This correction sequence M is added with T0 in adder 505, thereby final T1 is sent out (step S408).
Assessment detection unit 504 is showing to have selected the information of the assessed value of the T1 corresponding with head " 1 " to feed back to scrambler 502 as result of determination.In the case, the LFSR state S (t) when scrambler 502 completes T0 is corrected into and considers when T1 completes and definite state, and is the S (t+1) (step S409) of new data block (t+1) calibrated state understanding.To method that carry out this correction be described after a while.
Can executed in parallel step S401 and S403.In addition, for the T0 and the T1 that generate in turn, can perform step in turn S402 and S404.Hereinafter use description to realize the hardware configuration of the communicator 500 of this processing.
Fig. 4 shows the ios dhcp sample configuration IOS DHCP of the scrambler 502 with calibration function.Scrambler 502 configures (Figure 15) based on motor synchronizing scrambler, and is designed to adjust according to the result of determination of coming from assessment detection unit 504 feedbacks the state of LFSR.
Scrambler 502 is preserved the corrected value 601 (constant) of LFSR.Shown corrected value 601 " 1 ", " 0 ", " 1 " is example just, and never limits the corrected value 601 of this exemplary embodiment.In the situation that come the result of determination of self-evaluating detection unit 504 corresponding to T1, scrambler 502 is added state so that the state correction of LFSR is completed to T1 the value in the register of corrected value 601 and LFSR and thinks next data block (t+1) prepare (Fig. 3, step S409).On the other hand, in result of determination, corresponding to T0 in the situation that, without corrected value 601, proofread and correct the state of LFSR.
The corrected value 601 of LFSR is in the initial condition of LFSR, to be set to the register value of the LFSR obtaining in the situation that zero and " 100 ... 000 " (number of " 0 " is data block length) is transfused to entirely, and is represented by the corresponding bit number of the register capacity with LFSR.
Fig. 5 is the ios dhcp sample configuration IOS DHCP of assessment detection unit 504.From the T0 of scrambler 502 outputs, be imported into assessment detection unit 504.The above-mentioned correction sequence M of correction sequence generating unit 701 output.This can realize by store precalculated value in memory.The scrambled data T1 with the comparison frame of header value " 1 " can be by obtaining correction sequence M and the T0Xiang Calais exporting from scrambler 502.
One assessed value calculating part 702a calculates the assessed value of T0, and another assessed value calculating part 702b calculates the assessed value of T1.The processing that assessed value calculating part 702a and 702b carry out occurs according to the input in turn of T0.Detection unit 703 is judged optimum bit sequence characteristic from the assessed value of T0 and T1, and result of determination is fed back to scrambler 502, and result of determination is provided to the control port of selector 704.
In the situation that from the result of determination of control port corresponding to head " 0 ", selector 704 is exported the full null sequence of N bit as mentioned above as the sequence that will be output to adder 505.In the case, the T0 from buffer 503 is sent out in the not reformed situation of value.In the situation that from the result of determination of control port corresponding to head " 1 ", selector 704 outputs are from the correction sequence M of correction sequence generating unit 701.This M is added to convert T0 to T1 with the T0 exporting from buffer 503, and this T1 is sent out subsequently.
[assessed value model 1]
To the assessed value model using in assessment detection unit 504 be described below.With regard to realization, it is important being easy to calculate assessed value.The DC balance (difference between the number of the number of " 0 " and " 1 ") of supposing the scrambled data based on data block t is Y (t).For example, therein the number of " 0 " be 30 and the number of " 1 " be (Frame length: N+1=64), DC balance Y (t) is-4 in the situation of 34 scrambled data.
Can utilize DC balance Y (t) and drop on the weight coefficient ρ (0≤ρ≤1) in preset range, according to following formula (1), define the data block t (t=1 based on continuous, 2,3 ...) the weighted accumulation DC balance Z (t) of scrambled data.
Z (t)=ρ (Y (t)+Z (t-1))=ρ Y (t)+(ρ ^2) Y (t-1)+(ρ ^3) Y (t-2)+... formula (1)
In above formula, Z (0) is set to 0.The in the situation that of ρ=0, formula (1) only represents the DC balance of present frame, and the in the situation that of ρ=1, formula (1) represents not have the model of the decay in past value.By suitably setting the coefficient ρ for weighting, weighted accumulation DC balance can be used in various types of sending/receiving equipment and transfer path aptly.
In the situation that weighted accumulation DC balance is used as evaluation criteria, assessed value calculating part 702a and 702b (Fig. 5) calculate respectively DC balance Y0 (t) and the Y1 (t) of T0 and T1.By according to the flow chart description of Fig. 6 processing procedure of detection unit 703 in the case.
When respectively from the DC balance Y0 (t) of assessed value calculating part 702a and 702b input T0 and T1 and Y1 (t) (step S800), the absolute value (step S801) of the weighted accumulation DC balance of detection unit 703 comparison Y0 (t) and Y1 (t).According to formula (1), for Y0 (t), as present frame assessed value Y0 (t) and the absolute value of the addition results of assessed value Z (t-1) in the past | Y0 (t)+Z (t-1) | be obtained as the value that will compare, and for Y1 (t), | Y1 (t)+Z (t-1) | be obtained as the value that will compare.
In the situation that above, relatively show corresponding with the assessed value of T0 | Y0 (t)+Z (t-1) | less ("Yes" in S801), detection unit 703 judges that the assessed value of T0 is optimum (step S802), and the information about this judgement is fed back to scrambler 502.In addition, in order to prepare for the assessment of subsequent data piece (t+1), detection unit 703 utilizes the Y0 (t) of present frame to upgrade weighted accumulation DC balance Z (t) (step S803) according to Z (t)=ρ (Y0 (t)+Z (t-1)).
On the other hand, in the situation that corresponding with the assessed value of T1 | Y1 (t)+Z (t-1) | less ("No" in S801), detection unit 703 judges that the assessed value of T1 is optimum (step S804). then, detection unit 703 utilizes the Y1 (t) of present frame to upgrade weighted accumulation DC balance Z (t) (step S805) according to Z (t)=ρ (Y1 (t)+Z (t-1)).
[assessed value model 2]
As another example of using the assessed value model of accumulation DC balance, can enumerate the method for the scrambled data of using nearest constant, numbers.Suppose that constant frame number is K+1, the accumulation DC balance of this model can be by defining with following formula (2).
Z (t)=Y (t)+Y (t-1)+... + Y (t-K+1) | formula (2)
The in the situation that of K=1, the same with the situation of ρ=0 in formula (1), formula (2) represents the assessed value model of the DC balance based on present frame.In addition, the accumulation DC balance that also definable obtains from the combination of formula (1) and (2).In preserving the implementation of Z (t), the renewal of the Z (t) in formula (2) can be carried out as represented with following formula (3).In this model, must preserve the DC equilibrium valve of a nearest K frame.
Z (t)=Y (t)+Z (t-1)-Y (t-K+1) formula (3)
[assessed value model 3]
Except DC balance, the maximum run length of scrambled data also can be used as assessed value.This model is to check " 0 " run length in T0 and T1 or " 1 " run length (number of continuous " 0 " or " 1 ") and utilize its maximum to be that maximum run length is as the method for assessed value.In the assessment of this model, judge that for example maximum run length is less, bit sequence characteristic is just better.
[assessed value model 4]
Can consider to use above-mentioned two class assessed values to accumulate the assessed value model of DC balance and maximum run length.To the processing procedure of detection unit 703 in the case be described according to the flow chart of Fig. 7.Below, suppose that using the method (Fig. 6) of weighted accumulation DC balance is the first evaluation criteria, and the method for use maximum run length is the second evaluation criteria.The priority of the first evaluation criteria is set higher than the priority of the second evaluation criteria.
Detection unit 703 calculates the assessed value (weighted accumulation DC balance) of T0 and T1 based on the first evaluation criteria and judges whether the difference between them surpasses predetermined threshold value (step S901).In the situation that the difference between two assessed values surpasses threshold value, detection unit 703 is the result of determination (step S902) based on the first evaluation criteria according to said process (S801 to S805 of Fig. 6) application.
On the other hand, in the situation that the difference between T0 and the assessed value of T1 is not more than threshold value ("No" in S901), there is not big-difference in detection unit 703 judgements, and based on the second evaluation criteria, carry out another and judge (judgement based on maximum run length) (step S903) between the T0 based on the first evaluation criteria and the assessed value of T1.Then, detection unit 703 feeds back to scrambler 502 (step S904) result of determination.
By setting that the second evaluation criteria take, by the information setting of T0, be result of determination all the time, by in the situation that do not exist big-difference to export all the time the optimum result of determination of assessed value of T0 between two assessed values in the assessment based on the first evaluation criteria, can realize a model, when wherein the more only difference between assessed value between assessed value surpasses threshold value, just carry out.This has reduced the frequency of the correct operation of carrying out in scrambler 502.
[assessed value model 5]
As the modification of the method (Fig. 7) of above-mentioned use two class evaluation criterias, available have a method of using random bit sequence.The processing procedure of the method is shown in Figure 8.In illustrated process, the method is used weighted accumulation DC balance as the first evaluation criteria, and the method adopts and uses the random alternative of random bit sequence as the second virtual evaluation criteria simultaneously.Below, by only describe with Fig. 7 in the difference of process.
In the situation that the T0 based on weighted accumulation DC balance and the difference between the absolute value of T1 are not more than threshold value ("No" in S901), detection unit 703 is read random bit sequence (step S1001).Random bit sequence can be arbitrarily, as long as it can not be inferred completely by third party.For example, random bit sequence can be part value or the time parameter of the LFSR in scrambler 502.
Detection unit 703 judges that whether the random bit obtaining is consistent or corresponding with predefined predicted value.For example, in the situation that random bit sequence is time parameter, given time band is redefined for predicted value, then judges that the indicated time of random bit sequence is whether corresponding to the time band of predicted value.
In the situation that random bit sequence does not correspond to predicted value ("No" in step S 1002), the scrambled data that detection unit 703 judgements have optimum assessed value is T0 (step S1003).On the other hand, in random bit sequence, corresponding to predicted value in the situation that, detection unit 703 judges that T1 are optimum (step S1004).Thereby, adopt random alternative method to make to improve the resistance of antagonism to the attack of scrambled data.
As mentioned above, according to this exemplary embodiment, can realize the transmission that redundancy had obtained suppressing and had the scrambled data that is suitable for the bit sequence characteristic that sends.This makes to improve the quality of high-speed communication.
In this exemplary embodiment, the recipient of scrambled data only needs to be provided with existing motor synchronizing descrambler.That is to say, the head mistake in the scrambled data receiving, does not require special layout.
The circuit scale of expection transmit leg may be approximately that traditional twice is so large; Yet scrambler itself is a little circuit, thereby the increase of this circuit is very little for the impact of the scale of whole transmitter.In addition, the increase of delay during transmission is just so short with about corresponding time of piece.
At correction sequence M, be set to have pseudo-random characteristics in the situation that, the improvement of DC balance is that " 0 " or " 1 " are randomness based on head; Yet in fact, the distribution of DC balance can be greatly improved.For example, suppose the extreme model that uses the accumulation DC balance that there is no the decay in past value, accumulate when DC is equilibrated at the existing scrambler of use and present and be uniformly distributed; And according to this exemplary embodiment, can obtain zero-mean exponential distribution.In addition, select by this way correction sequence M to make to improve the assessed value such as maximum run length except DC balance.
< < example > >
To the more specifically example of above-mentioned exemplary embodiment be described.In order to realize above exemplary embodiment, must preset the corrected value 601 (Fig. 4) of LFSR and the output sequence M (Fig. 5) of correction sequence generating unit 701 at that time.For example, the generator polynomial of supposing LFSR is that " g (x)=x^8+x^6+x^5+x^4+1 " and data block length N are 32 (frame length=33), corrected value 601 is set to " 1000_0100 " (8 bit), and correction sequence M is set to " 1011_0001_1110_1000_0111_1111_1001_0000_1 " (33 bit).
In the situation that exist and postpone the obtaining of the result of determination from the end of data block to assessment detection unit 504, corrected value 601 is considered this delay and is set.In the case, depend on the scrambling head of previous data block, according to retardation, to the beginning application delay of the current data block of buffer 503, proofread and correct.Assessment detection unit 504 starts to process after this correction completes.
Correction sequence M preferably has the value that makes T0 and T1 there is no correlation and have superperformance with regard to DC balance, maximum run length and randomness.In the situation that 64b/66b encodes, use the scrambler being represented by the generator polynomial with following formula (4).
G (x)=x^59+x^19+1 formula (4)
According to formula (4), " 1 " that correction sequence M is included in beginning is continuous 38 bits " 0 " afterwards, and the in the situation that of N=32, seem for the not impact of scrambling head.In actual realization of the present invention, need to avoid this scrambler.
Meanwhile, when adopting, using following formula (5) during as generator polynomial, the in the situation that of N=32, correction sequence M presents a full sequence.That is to say, by generator polynomial being set as with following formula (5), with regard to CIMT or accumulation DC balance, can obtain identical effect.
G (x)=x^63+x^62+1 formula (5)
Fig. 9 shows according to upgrade the realization example of the detection unit 703 of weighted accumulation DC balance Z (t) with above formula (1).Illustrated detection unit 703 comprises register 1101 for storing in turn Z (t), for adder 1102 that the output of register 1101 and Y (t+1) are added and for the multiplier 1103 of above addition results and weight coefficient ρ are multiplied each other (constant times).When ρ=0.875 for example, by once displacement and a subtraction can be realized ρ times.
Figure 10 shows according to upgrade the realization example (K=4) of detection unit 703 of the accumulation DC balance Z (t) of a limited number of frame with above formula (3).Detection unit 703 in the case comprise adder 1102, for store a nearest K=4 frame Y (t) shift register 1201 and for storing the register 1202 of Z (t).
Figure 11 and 12 diagram show the distribution that (Fig. 6) obtains in the situation that weighted accumulation DC balance is used as assessed value separately.The diagram of Figure 11 shows the distribution obtaining the in the situation that of ρ=0.9, and the diagram of Figure 12 shows the distribution obtaining the in the situation that of ρ=1.0.In both cases, data block length N is set to 63 (frame length is 64), and the number of piece is 1,000,000, and input data are random generations.
The distribution of accumulation DC balance indicates the value (Y (t)+Z (t-1))/2 counting being obtained by each data block.The vertical axis of diagram is logarithmic scale.As the generator polynomial of LFSR, use with following formula (6).
G (x)=x^63+x^62+x^57+x^40+x^34+x^17+1 formula (6)
The distribution of each the width figure in Figure 11 and 12 " traditional scheme " is the value for each data block (64 bit), accumulation DC balance counting being obtained by the situation that applying typical scrambling.From the diagram of Figure 11 and 12, can find out, in example of the present invention, significantly improve the distribution of accumulation DC balance.For example, in Figure 11, suppose that the absolute value of accumulation DC balance surpasses 20, the situation lower frequency in the typical scrambling being indicated by " traditional scheme " becomes more than 1/100, and frequency for once reaches 1/1,000,000 in this example.Especially, in the model of ρ=1.0 shown in Figure 12, in " traditional scheme ", obtain and be uniformly distributed, and index access distributes in example of the present invention.
The diagram of Figure 13 show in the situation that under the setting identical with the situation of the diagram of Figure 11 and 12 the accumulation DC balance of a limited number of frame (K=4) based on formula (3) be used as the distribution that evaluation criteria obtains.Can find out, similar with the situation of Figure 11, in example of the present invention, the distribution of accumulation DC balance is improved.For example, in Figure 13, in the situation that the absolute value of accumulation DC balance surpasses 20 relative frequency becomes more than 1/100 in " traditional scheme ", and be 1/10,000 in example of the present invention.
Exemplary embodiment of the present invention is not limited to above-mentioned exemplary embodiment, but can in the scope of following claim, revise as required.For example, although the bit number of scrambling head is 1 bit in above exemplary embodiment, it can be 2 bits or more.In this case, calculate 2^d head assessed value (T0, T1 ... each is (N+d) bit naturally), and from 2^d assessed value one of selection the best.
How all the content that the assessment detection unit 504 of above exemplary embodiment is configured to result of determination feedback and judge result.Yet as an alternative, assessment detection unit 504 only can be configured to when result of determination indication T1, only when needs utilize corrected value 601 correction LFSR (S409, Fig. 3), ability feeds back to scrambler 502 by result of determination.
Although realize according to communicator 500 available hardware of exemplary embodiment of the present invention, it also can be by computer realization, this computer reads and makes this computer can be used as the program of communicator 500 and carry out this program from computer readable recording medium storing program for performing.
Although realize according to the communication means available hardware of exemplary embodiment of the present invention, it also can be by computer realization, this computer reads and makes this computer can carry out the program of the method and carry out this program from computer readable recording medium storing program for performing.
Above-mentioned exemplary embodiment is the preferred embodiments of the present invention, but scope of the present invention is not only limited to this exemplary embodiment, can carry out various modifications to it, as long as these are revised, does not depart from spirit of the present invention.
The application, based on (on July 10th, 2009 submits to) Japanese patent application No.2009-163798 require its priority according to Paris Convention formerly, is incorporated to the full content of this application here by reference.
Although described exemplary embodiment of the present invention in detail, should be appreciated that and can it be made various changes, substitutes and be replaced, and do not depart from the spirit and scope of the present invention that are defined by the following claims.In addition, inventor wishes, even revised claim in course of the review, and also all equivalents of the invention of beachhead demand protection.
Part or all of above embodiment can be described as following remarks, but is not limited to this.
(remarks 1) a kind of method for scrambling, comprising:
Using fiducial value as head, add the beginning of data block to form reference frame;
By using motor synchronizing scrambler to generate the scrambled data of described reference frame;
By the scrambled data of correction sequence and described reference frame being added to generate the scrambled data of comparison frame, in this comparison frame, the value different from described fiducial value is used as head and added described data block to;
According to evaluation criteria, calculating is about the assessed value of the bit sequence characteristic of the scrambled data of described reference frame with about described relatively another assessed value of the bit sequence characteristic of the scrambled data of frame;
From the assessed value calculating, select to represent the assessed value of optimum bit sequence characteristic for transmission;
When selected assessed value is during corresponding to described reference frame, send the scrambled data of described reference frame; And
When selected assessed value is during corresponding to described relatively frame, send by the scrambled data of described correction sequence and described reference frame being added to the scrambled data obtaining, the value that the shift register of described scrambler is preserved is corrected to value definite when considering the completing of scrambled data of described relatively frame, and calibrated value is applied to the reference frame of new data block.
(remarks 2), according to the method for scrambling described in remarks 1, also comprises:
When the DC balance by each scrambled data is as bit sequence characteristic, utilize the accumulation of assessed value in the past to calculate described assessed value;
The assessed value of the described optimum bit sequence characteristic of utilization expression is upgraded the accumulation of the assessed value in described past; And
Utilization is calculated the assessed value about the scrambled data of described new data block through the accumulation of upgrading.
(remarks 3) is according to the method for scrambling described in remarks 2, wherein
Described assessed value is by the coefficient weighting with having the value in preset range.
(remarks 4) is according to the method for scrambling described in remarks 1, wherein
Described assessed value is to calculate when the maximum run length by each scrambled data is as bit sequence characteristic.
(remarks 5), according to the method for scrambling described in remarks 1, also comprises:
According to the first evaluation criteria, calculate the assessed value of each scrambled data;
When the difference between the assessed value calculating surpasses threshold value, the first evaluation criteria represents the assessed value of described optimum bit sequence characteristic described in selective basis; And
When the difference between the assessed value calculating is not more than described threshold value, according to second evaluation criteria different from described the first evaluation criteria calculate the assessed value of each scrambled data and from the assessed value calculating described in selective basis the second evaluation criteria represent the assessed value of described optimum bit sequence characteristic.
(remarks 6) is according to the method for scrambling described in remarks 5, wherein
The assessed value being represented by described the first evaluation criteria is the value of selecting from the first assessed value and the second assessed value, this first assessed value is when the DC balance by each scrambled data is as bit sequence characteristic, to utilize the accumulation of assessed value in the past to calculate, and this second assessed value is to calculate when the maximum run length by each scrambled data is as bit sequence characteristic, and
The assessed value being represented by described the second evaluation criteria from described the first assessed value select with described the second assessed value, the value different from the assessed value being represented by described the first evaluation criteria.
(remarks 7) is according to the method for scrambling described in remarks 6, wherein
When the DC balance by each scrambled data is as bit sequence characteristic, described the first assessed value is calculated in the accumulation of utilization assessed value in the past, described the first assessed value is by the coefficient weighting with having the value in preset range.
(remarks 8) is according to the method for scrambling described in remarks 6 or remarks 7, wherein, if the assessed value being represented by described the first evaluation criteria is to utilize the first evaluation criteria of the accumulation calculating of assessed value in the past when the DC balance by each scrambled data is as bit sequence characteristic, described method for scrambling also comprises:
The assessed value of the described optimum bit sequence characteristic of utilization expression is upgraded the accumulation of the assessed value in described past, and
Utilization is calculated the assessed value about the scrambled data of described new data block through the accumulation of upgrading.
(remarks 9), according to the method for scrambling described in remarks 1, comprising:
According to the first evaluation criteria, calculate the assessed value of each scrambled data;
When the difference between the assessed value calculating surpasses threshold value, the first evaluation criteria represents the assessed value of described optimum bit sequence characteristic described in selective basis;
When the difference between the assessed value calculating is not more than described threshold value, obtain random bit sequence;
When described random bit sequence is during corresponding to predicted value, select the scrambled data of described relatively frame as the scrambled data with the assessed value that represents described optimum bit sequence characteristic; And
When described random bit sequence does not correspond to described predicted value, select the scrambled data of described reference frame as the scrambled data with the assessed value that represents described optimum bit sequence characteristic.
(remarks 10) is according to the method for scrambling described in remarks 9, wherein
The assessed value being represented by described the first evaluation criteria is the value of selecting from the first assessed value and the second assessed value, this first assessed value is when the DC balance by each scrambled data is as bit sequence characteristic, to utilize the accumulation of assessed value in the past to calculate, and this second assessed value is to calculate when the maximum run length by each scrambled data is as bit sequence characteristic.
(remarks 11) is according to the method for scrambling described in remarks 10, wherein
When the DC balance by each scrambled data is as bit sequence characteristic, described the first assessed value is calculated in the accumulation of utilization assessed value in the past, described the first assessed value is by the coefficient weighting with having the value in preset range.
(remarks 12) is according to the method for scrambling described in remarks 10 or remarks 11, wherein, if the assessed value being represented by described the first evaluation criteria is to utilize the first evaluation criteria of the accumulation calculating of assessed value in the past when the DC balance by each scrambled data is as bit sequence characteristic, described method for scrambling also comprises:
The assessed value of the described optimum bit sequence characteristic of utilization expression is upgraded the accumulation of the assessed value in described past, and
Utilization is calculated the assessed value about the scrambled data of described new data block through the accumulation of upgrading.
(remarks 13) is according to the method for scrambling described in any one in remarks 1 to 12, wherein
The bit number of described head is 1 bit.
(remarks 14) a kind of communicator, comprising:
Head addition portion, this head addition portion is added the beginning of data block to form reference frame using fiducial value as head;
Scrambling portion, this scrambling portion is by being used motor synchronizing scrambler to generate the scrambled data of described reference frame;
Assessment detection unit, this assessment detection unit: by the scrambled data of correction sequence and described reference frame being added to generate the scrambled data of comparison frame, in this comparison frame, the value different from described fiducial value is used as head and added described data block to, according to evaluation criteria, calculating, about the assessed value of the bit sequence characteristic of the scrambled data of described reference frame with about described relatively another assessed value of the bit sequence characteristic of the scrambled data of frame, selects to represent the assessed value of optimum bit sequence characteristic for transmission from the assessed value calculating; And export described correction sequence or null sequence according to described selection; And
Adder, this adder is added and sends addition results by the scrambled data of described correction sequence or described null sequence and described reference frame,
Wherein, when selected assessed value is during corresponding to described relatively frame, described assessment detection unit offers the result of described selection described scrambling portion and described correction sequence is outputed to described adder, and the value that described scrambling portion preserves the shift register of described scrambler when the result of described selection is sent out is corrected to value definite when considering the completing of scrambled data of described relatively frame, and calibrated value is applied to the reference frame of new data block.
(remarks 15) is according to the communicator described in remarks 14, wherein
Described assessment detection unit utilizes the accumulation of assessed value in the past to calculate described assessed value when the DC balance by each scrambled data is as bit sequence characteristic, utilize the assessed value of the described optimum bit sequence characteristic of expression to upgrade the accumulation of the assessed value in described past, and utilize the accumulation through upgrading to calculate the assessed value about the scrambled data of described new data block.
(remarks 16) is according to the communicator described in remarks 15, wherein
Described assessment detection unit comes described assessed value weighting with the coefficient with the value in preset range.
(remarks 17) is according to the communicator described in remarks 14, wherein
Described assessment detection unit calculates described assessed value when the maximum run length by each scrambled data is as bit sequence characteristic.
(remarks 18) is according to the communicator described in remarks 14, wherein
Described assessment detection unit calculates the assessed value of each scrambled data according to the first evaluation criteria, when the difference between the assessed value calculating surpasses threshold value, described in selective basis, the first evaluation criteria represents the assessed value of described optimum bit sequence characteristic, and when the difference between the assessed value calculating is not more than described threshold value, according to second evaluation criteria different from described the first evaluation criteria calculate the assessed value of each scrambled data and from the assessed value calculating described in selective basis the second evaluation criteria represent the assessed value of described optimum bit sequence characteristic.
(remarks 19) is according to the communicator described in remarks 18, wherein
The assessed value being represented by described the first evaluation criteria is the value of selecting from the first assessed value and the second assessed value, this first assessed value is when the DC balance by each scrambled data is as bit sequence characteristic, to utilize the accumulation of assessed value in the past to calculate, and this second assessed value is to calculate when the maximum run length by each scrambled data is as bit sequence characteristic, and
The assessed value being represented by described the second evaluation criteria from described the first assessed value select with described the second assessed value, the value different from the assessed value being represented by described the first evaluation criteria.
(remarks 20) is according to the communicator described in remarks 19, wherein
When the DC balance by each scrambled data is as bit sequence characteristic, described the first assessed value is calculated in the accumulation of utilization assessed value in the past, described assessment detection unit comes described the first assessed value weighting with the coefficient with the value in preset range.
(remarks 21) is according to the communicator described in remarks 19 or remarks 20, wherein, if the assessed value being represented by described the first evaluation criteria is to utilize the first evaluation criteria of the accumulation calculating of assessed value in the past when the DC balance by each scrambled data is as bit sequence characteristic, so
The utilization of described assessment detection unit represents that the assessed value of described optimum bit sequence characteristic upgrades the accumulation of the assessed value in described past, and utilizes the accumulation through upgrading to calculate the assessed value about the scrambled data of new data block.
(remarks 22) is according to the communicator described in remarks 14, wherein
Described assessment detection unit: the assessed value of calculating each scrambled data according to the first evaluation criteria, when the difference between the assessed value calculating surpasses threshold value, described in selective basis, the first evaluation criteria represents the assessed value of described optimum bit sequence characteristic, when the difference between the assessed value calculating is not more than described threshold value, obtain random bit sequence, in described random bit sequence during corresponding to predicted value, select the scrambled data of described relatively frame as the scrambled data with the assessed value that represents described optimum bit sequence characteristic, and when described random bit sequence does not correspond to described predicted value, select the scrambled data of described reference frame as the scrambled data with the assessed value that represents described optimum bit sequence characteristic.
(remarks 23) is according to the communicator described in remarks 22, wherein
The assessed value being represented by described the first evaluation criteria is the value of selecting from the first assessed value and the second assessed value, this first assessed value is when the DC balance by each scrambled data is as bit sequence characteristic, to utilize the accumulation of assessed value in the past to calculate, and this second assessed value is to calculate when the maximum run length by each scrambled data is as bit sequence characteristic.
(remarks 24) is according to the communicator described in remarks 23, wherein
When the DC balance by each scrambled data is as bit sequence characteristic, described the first assessed value is calculated in the accumulation of utilization assessed value in the past, described assessment detection unit uses the coefficient with the value in preset range to described the first assessed value weighting.
(remarks 25) is according to the communicator described in remarks 23 or remarks 24, wherein, if the assessed value being represented by described the first evaluation criteria is to utilize the first evaluation criteria of the accumulation calculating of assessed value in the past when the DC balance by each scrambled data is as bit sequence characteristic, so
The utilization of described assessment detection unit represents that the assessed value of described optimum bit sequence characteristic upgrades the accumulation of the assessed value in described past, and utilizes the accumulation through upgrading to calculate the assessed value about the scrambled data of new data block.
(remarks 26) is according to the communicator described in any one in remarks 14 to 25, wherein
Described head addition portion is added a bit value as described head to described data block.
(remarks 27) a kind of program, serves as according to the communicator described in any one in remarks 14 to 26 computer.
{ industrial applicability }
The suitable line coding being applied in for example optical communication of the present invention.
Claims (18)
1. a method for scrambling, comprising:
Using fiducial value as head, add the beginning of data block to form reference frame;
By using motor synchronizing scrambler to generate the scrambled data of described reference frame;
By having the correction sequence of pseudo-random characteristics and the scrambled data of described reference frame and be added to generate the scrambled data of comparison frame, values different from described fiducial value in this comparison frame are used as the beginning that head has added described data block to;
According to evaluation criteria, calculating is about the assessed value of the bit sequence characteristic of the scrambled data of described reference frame with about described relatively another assessed value of the bit sequence characteristic of the scrambled data of frame;
From the assessed value calculating, select to represent the assessed value of optimum bit sequence characteristic for transmission;
When selected assessed value is during corresponding to described reference frame, send the scrambled data of described reference frame; And
When selected assessed value is during corresponding to described relatively frame, send by the scrambled data of described correction sequence and described reference frame being added to the scrambled data obtaining, the value that the shift register of described scrambler is preserved is corrected to the value of the state of the described shift register presenting while being illustrated in the scrambled data that generates described relatively frame, and calibrated value is applied to the reference frame of new data block.
2. method for scrambling according to claim 1, also comprises:
When the DC balance by each scrambled data is as bit sequence characteristic, utilize the accumulation of assessed value in the past to calculate described assessed value, the difference between the number that described DC balance is " 0 " and the number of " 1 ";
The assessed value of the described optimum bit sequence characteristic of utilization expression is upgraded the accumulation of the assessed value in described past; And
Utilization is calculated the assessed value about the scrambled data of described new data block through the accumulation of upgrading.
3. method for scrambling according to claim 2, wherein
Described assessed value is by the coefficient weighting with having the value in preset range.
4. method for scrambling according to claim 1, wherein
Described assessed value is to calculate when the maximum run length by each scrambled data is as bit sequence characteristic.
5. method for scrambling according to claim 1, also comprises:
According to the first evaluation criteria, calculate the assessed value of each scrambled data;
When the difference between the assessed value calculating surpasses threshold value, the first evaluation criteria represents the assessed value of described optimum bit sequence characteristic described in selective basis; And
When the difference between the assessed value calculating is not more than described threshold value, according to second evaluation criteria different from described the first evaluation criteria calculate the assessed value of each scrambled data and from the assessed value calculating described in selective basis the second evaluation criteria represent the assessed value of described optimum bit sequence characteristic.
6. method for scrambling according to claim 5, wherein
The assessed value being represented by described the first evaluation criteria is the value of selecting from the first assessed value and the second assessed value, this first assessed value is when the DC balance by each scrambled data is as bit sequence characteristic, to utilize the accumulation of assessed value in the past to calculate, and this second assessed value is to calculate when the maximum run length by each scrambled data is as bit sequence characteristic, and
The assessed value being represented by described the second evaluation criteria from described the first assessed value select with described the second assessed value, the value different from the assessed value being represented by described the first evaluation criteria.
7. method for scrambling according to claim 6, wherein
When the DC balance by each scrambled data is as bit sequence characteristic, described the first assessed value is calculated in the accumulation of utilization assessed value in the past, described the first assessed value is by the coefficient weighting with having the value in preset range, the difference between the number that described DC balance is " 0 " and the number of " 1 ".
8. method for scrambling according to claim 6, wherein, if the assessed value being represented by described the first evaluation criteria is to utilize the first evaluation criteria of the accumulation calculating of assessed value in the past when the DC balance by each scrambled data is as bit sequence characteristic, described method for scrambling also comprises:
The assessed value of the described optimum bit sequence characteristic of utilization expression is upgraded the accumulation of the assessed value in described past, and
Utilization is calculated the assessed value about the scrambled data of described new data block through the accumulation of upgrading.
9. method for scrambling according to claim 1, comprising:
According to the first evaluation criteria, calculate the assessed value of each scrambled data;
When the difference between the assessed value calculating surpasses threshold value, the first evaluation criteria represents the assessed value of described optimum bit sequence characteristic described in selective basis;
When the difference between the assessed value calculating is not more than described threshold value, obtain random bit sequence;
When described random bit sequence is during corresponding to predicted value as preset value, select the scrambled data of described relatively frame as the scrambled data with the assessed value that represents described optimum bit sequence characteristic; And
When described random bit sequence does not correspond to described predicted value, select the scrambled data of described reference frame as the scrambled data with the assessed value that represents described optimum bit sequence characteristic.
10. method for scrambling according to claim 9, wherein
The assessed value being represented by described the first evaluation criteria is the value of selecting from the first assessed value and the second assessed value, this first assessed value is when the DC balance by each scrambled data is as bit sequence characteristic, to utilize the accumulation of assessed value in the past to calculate, and this second assessed value is to calculate when the maximum run length by each scrambled data is as bit sequence characteristic.
11. method for scrambling according to claim 10, wherein
When the DC balance by each scrambled data is as bit sequence characteristic, described the first assessed value is calculated in the accumulation of utilization assessed value in the past, described the first assessed value is by the coefficient weighting with having the value in preset range.
12. method for scrambling according to claim 10, wherein, if the assessed value being represented by described the first evaluation criteria is to utilize the first evaluation criteria of the accumulation calculating of assessed value in the past when the DC balance by each scrambled data is as bit sequence characteristic, described method for scrambling also comprises:
The assessed value of the described optimum bit sequence characteristic of utilization expression is upgraded the accumulation of the assessed value in described past, and
Utilization is calculated the assessed value about the scrambled data of described new data block through the accumulation of upgrading.
13. method for scrambling according to claim 1, wherein
The bit number of described head is 1 bit.
14. 1 kinds of communicators, comprising:
Head addition portion, this head addition portion is added the beginning of data block to form reference frame using fiducial value as head;
Scrambling portion, this scrambling portion is by being used motor synchronizing scrambler to generate the scrambled data of described reference frame;
Assessment detection unit, this assessment detection unit: by thering is the correction sequence of pseudo-random characteristics and the scrambled data of described reference frame and be added to generate the scrambled data of comparison frame, values different from described fiducial value in this comparison frame are used as the beginning that head has added described data block to, according to evaluation criteria, calculating is about the assessed value of the bit sequence characteristic of the scrambled data of described reference frame with about described relatively another assessed value of the bit sequence characteristic of the scrambled data of frame, from the assessed value calculating, select to represent the assessed value of optimum bit sequence characteristic for transmission, and export described correction sequence or null sequence according to described selection, and
Adder, this adder is added and sends addition results by the scrambled data of described correction sequence or described null sequence and described reference frame,
Wherein, when selected assessed value is during corresponding to described relatively frame, described assessment detection unit offers the result of described selection described scrambling portion and described correction sequence is outputed to described adder, and the value that described scrambling portion preserves the shift register of described scrambler when the result of described selection is sent out is corrected to the value of the state of the described shift register presenting while being illustrated in the scrambled data that generates described relatively frame, and calibrated value is applied to the reference frame of new data block.
15. communicators according to claim 14, wherein
Described assessment detection unit utilizes the accumulation of assessed value in the past to calculate described assessed value when the DC balance by each scrambled data is as bit sequence characteristic, the assessed value of the described optimum bit sequence characteristic of utilization expression is upgraded the accumulation of the assessed value in described past, and utilize the accumulation through upgrading to calculate the assessed value about the scrambled data of described new data block, the difference between the number that described DC balance is " 0 " and the number of " 1 ".
16. communicators according to claim 14, wherein
Described assessment detection unit calculates described assessed value when the maximum run length by each scrambled data is as bit sequence characteristic.
17. communicators according to claim 14, wherein
Described assessment detection unit calculates the assessed value of each scrambled data according to the first evaluation criteria, when the difference between the assessed value calculating surpasses threshold value, described in selective basis, the first evaluation criteria represents the assessed value of described optimum bit sequence characteristic, and when the difference between the assessed value calculating is not more than described threshold value, according to second evaluation criteria different from described the first evaluation criteria calculate the assessed value of each scrambled data and from the assessed value calculating described in selective basis the second evaluation criteria represent the assessed value of described optimum bit sequence characteristic.
18. communicators according to claim 14, wherein
Described assessment detection unit: the assessed value of calculating each scrambled data according to the first evaluation criteria, when the difference between the assessed value calculating surpasses threshold value, described in selective basis, the first evaluation criteria represents the assessed value of described optimum bit sequence characteristic, when the difference between the assessed value calculating is not more than described threshold value, obtain random bit sequence, in described random bit sequence during corresponding to predicted value as preset value, select the scrambled data of described relatively frame as the scrambled data with the assessed value that represents described optimum bit sequence characteristic, and when described random bit sequence does not correspond to described predicted value, select the scrambled data of described reference frame as the scrambled data with the assessed value that represents described optimum bit sequence characteristic.
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| JP5814803B2 (en) * | 2012-01-16 | 2015-11-17 | 富士通株式会社 | Transmission circuit, reception circuit, transmission method and reception method |
| CN104426631B (en) * | 2013-09-06 | 2018-03-06 | 华为技术有限公司 | The method and device that data are handled |
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| US5438621A (en) * | 1988-11-02 | 1995-08-01 | Hewlett-Packard Company | DC-free line code and bit and frame synchronization for arbitrary data transmission |
| CN1823488A (en) * | 2003-07-15 | 2006-08-23 | 索尼株式会社 | Radio communication system, radio communication device, radio communication method, and computer program |
| CN101212392A (en) * | 2006-12-30 | 2008-07-02 | 上海瑞高信息技术有限公司 | Mobile multimedia broadcast satellite distribution data encapsulation and synchronization method |
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| US5022051A (en) * | 1988-11-02 | 1991-06-04 | Hewlett-Packard Company | DC-free line code for arbitrary data transmission |
| JPH0417422A (en) * | 1990-05-11 | 1992-01-22 | Matsushita Electric Ind Co Ltd | Atm signal transmitter |
| EP0511373B1 (en) * | 1990-11-13 | 1998-01-07 | Hewlett-Packard Company | Dc-free line code and bit and frame synchronization for arbitrary data transmission |
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| US5438621A (en) * | 1988-11-02 | 1995-08-01 | Hewlett-Packard Company | DC-free line code and bit and frame synchronization for arbitrary data transmission |
| CN1823488A (en) * | 2003-07-15 | 2006-08-23 | 索尼株式会社 | Radio communication system, radio communication device, radio communication method, and computer program |
| CN101212392A (en) * | 2006-12-30 | 2008-07-02 | 上海瑞高信息技术有限公司 | Mobile multimedia broadcast satellite distribution data encapsulation and synchronization method |
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