CN102446703A - Dual patterning method - Google Patents
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- CN102446703A CN102446703A CN2010105091687A CN201010509168A CN102446703A CN 102446703 A CN102446703 A CN 102446703A CN 2010105091687 A CN2010105091687 A CN 2010105091687A CN 201010509168 A CN201010509168 A CN 201010509168A CN 102446703 A CN102446703 A CN 102446703A
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Abstract
The invention provides a dual patterning method which comprises the following steps of: providing a substrate, and sequentially forming a first masking film layer and a second masking film layer on the substrate; carrying out anisotropic etching on the first masking film layer and the second masking film layer, and forming a first opening in the masking film layer and the second masking film layer, wherein the first opening exposes the surface of the substrate; carrying out partly side etching on the second masking film layer; forming a third masking film layer on the substrate, wherein the third masking film layer covers the first masking film layer and leads the second masking film layer to be exposed; removing the second masking film layer, and forming a second opening in the third masking film layer, wherein the second opening leads the first masking film layer to be exposed; by using the third masking film layer as the masking film, carrying out anisotropic etching on the first masking film layer under the second opening till exposing the substrate; and removing the third masking film layer. The dual patterning method provided by the invention has the advantages of avoiding the problem of non-uniform etching of the substrate and effectively improving the etching effect.
Description
Technical field
The present invention relates to technical field of semiconductors, more specifically, the present invention relates to a kind of double-patternization (double patterning) method.
Background technology
Semiconductor technology strides forward towards littler process node under the driving of Moore's Law constantly.Along with the continuous progress of semiconductor technology, the function of device is gradually become strong, but the semiconductor manufacture difficulty also grows with each passing day.And photoetching technique is a production technology the most key in the semiconductor fabrication process; Along with the semiconductor technology node enters into 65 nanometers, 45 nanometers; Even 32 lower nanometers; The ArF light source light lithography of existing 193nm can't satisfy the needs that semiconductor is made, and extreme ultraviolet light photoetching technique (EUV), multi-beam do not have the research focus that mask technique and nanometer embossing become photoetching candidate technologies of future generation.But above-mentioned photoetching candidate technologies of future generation still has inconvenience and defective, demands urgently further improving.
When the step that continues to extend forward when Moore's Law is irreversible; The double-pattern technology becomes the optimal selection of industry undoubtedly; Double-patternization technology only need be carried out very little change to existing photoetching infrastructure, just can fill up 45 nanometers effectively to 32 nanometers even the photoetching technique blank of minor node more.The principle of double-patternization technology with the highdensity circuitous pattern of a cover resolve into that two covers are discrete, the lower figure of density, then they are prepared on the wafer.Just disclosed a kind of double-patternization technology in the U.S. Pat 7709396, the technological process of said double-patternization technology such as Fig. 1 comprise to shown in Figure 4:
On substrate 100, form and include first graph layer 101 that a plurality of flagpole patterns and equidistance are arranged; The spacing and the wide sum of single flagpole pattern of said first graph layer, 101 each adjacent flagpole pattern are defined as pitch, and the zone between said flagpole pattern is defined as first opening 107;
Afterwards, on the said substrate 100 and first graph layer 101, form side wall layer 103, said side wall layer 103 evenly is formed at first graph layer, 101 both sides;
Then; The said side wall layer of anisotropic etching; Form second graph layer 105 in the both sides of first graph layer, 101 each flagpole pattern (promptly in first opening 107), said second graph layer 105 includes a plurality of sidewalls, and each oppose side wall is corresponding to a flagpole pattern of first graph layer 103;
Then, remove first graph layer; Like this, the position that former each flagpole pattern of first graph layer occupies has promptly constituted second opening 109, and each second opening 109 all is positioned at 105 of pair of sidewalls.
Behind the above-mentioned process implementing, originally included two sidewalls and two openings (first opening and second opening) in the zone of each pitch correspondence, further, said sidewall can be used as the mask of etched substrate.Like this, can under the condition of not changing lithographic equipment, the pitch minimum value of first graph layer be broken through the restriction of photoetching resolution, thereby effectively improve the integrated level of chip.
Yet said double-pattern technology still has problems.The size and dimension influence of said first graph layer, 101 oppose side walls is very big.If said first graph layer, 101 thickness are too little, then the sidewall cross section of dry etching side wall layer 103 back formation is triangular in shape, and this can influence the effect of sidewall as substrate 100 etch mask; And, be subject to the step covering power of side wall layer 103 if the thickness of said first graph layer 101 is excessive, and the sidewall cross-sectional width that dry etching side wall layer 103 backs form is difficult to accurate control, and this has just reduced the accuracy of sidewall as etch mask.
Summary of the invention
The problem that the present invention solves provides a kind of double-pattern method, improves the substrate etching uniformity.
For addressing the above problem, the invention provides a kind of double-pattern method, comprising:
Substrate is provided, is formed with first mask layer and second mask layer on the said substrate successively;
Said first mask layer of anisotropic etching and second mask layer form first opening in said first mask layer and second mask layer, said first opening exposes substrate surface;
Said second mask layer of side direction partial etching;
On said substrate, form the 3rd mask layer, said the 3rd mask layer covers first mask layer, and makes second mask layer expose;
Remove said second mask layer, in the 3rd mask layer, form second opening, said second opening exposes the mask layer of winning;
With the 3rd mask layer is mask, and first mask layer of anisotropic etching second opening below is until exposing substrate;
Remove said the 3rd mask layer.
Compared with prior art; The present invention has the following advantages: first mask layer as the etched substrate mask has the square-section; And its thickness can accurately be controlled, and this has improved the uniformity of first mask layer greatly, when etched substrate; First mask layer of said uniform thickness has been avoided the uneven problem of substrate etching, has effectively improved etching effect.
Description of drawings
Fig. 1 to Fig. 4 is the technological process of prior art double-pattern method.
Fig. 5 is the schematic flow sheet of double-pattern method of the present invention.
Fig. 6 to Figure 13 is the generalized section of substrate in each step of embodiment of double-pattern method of the present invention.
Embodiment
For make above-mentioned purpose of the present invention, feature and advantage can be more obviously understandable, does detailed explanation below in conjunction with the accompanying drawing specific embodiments of the invention.
Set forth a lot of details in the following description so that make much of the present invention, implement but the present invention can also adopt other to be different from alternate manner described here, so the present invention has not received the restriction of following disclosed specific embodiment.
Said as the background technology part, in existing double-pattern metallization processes, the influence of the size and dimension of the first graph layer oppose side wall is very big.If the said first graph layer thickness is too little, the sidewall cross section that then forms after the dry etching side wall layer is triangular in shape, and this can influence the effect of sidewall as the substrate etching mask; And, be subject to the step covering power of side wall layer if the thickness of said first graph layer is excessive, and the sidewall cross-sectional width that forms after the dry etching side wall layer is difficult to accurate control, and this has just reduced the accuracy of sidewall as etch mask.
To the problems referred to above, inventor of the present invention provides a kind of double-pattern method, and is as shown in Figure 5, and said double-pattern method comprises:
Execution in step S502 provides substrate, is formed with first mask layer and second mask layer on the said substrate successively;
Execution in step S504, said first mask layer of anisotropic etching and second mask layer form first opening in said first mask layer and second mask layer, and said first opening exposes substrate surface;
Execution in step S506, said second mask layer of side direction partial etching;
Execution in step S508 forms the 3rd mask layer on said substrate, said the 3rd mask layer covers first mask layer, and makes second mask layer expose;
Execution in step S510 removes said second mask layer, in the 3rd mask layer, forms second opening, and said second opening exposes the mask layer of winning;
Execution in step S512 is a mask with the 3rd mask layer, and first mask layer of anisotropic etching second opening below is until exposing substrate;
Execution in step S514 removes said the 3rd mask layer.
Below in conjunction with accompanying drawing, specify the double-pattern method of the specific embodiment of the invention.
As shown in Figure 6, substrate 601 is provided, said substrate 601 is a silicon-based substrate, for example is that n type silicon substrate, p type silicon substrate perhaps are the SOI substrate; Said substrate 601 also can be silicon, germanium, GaAs or silicon Germanium compound substrate; Said substrate 601 can also be the substrate that comprises the part of integrated circuit and other elements, or has the substrate of covering dielectric and metal film, specially explains at this, should too not limit protection scope of the present invention.
Adopt chemical vapor deposition, physical vapor deposition or other films to form technology and on said substrate 601, form first mask layer 603 and second mask layer 603 successively.In specific embodiment, said first mask layer 603 and second mask layer 605 comprise: polysilicon, amorphous silicon, silica, silicon nitride, silicon oxynitride, metal, metal oxide, metal nitride, amorphous carbon or other are easy to film forming material.In practical application, said first mask layer 603 and second mask layer 605 should have relatively large etching selection ratio.For example, when said substrate 601 was silicon, said first mask layer 603 adopted silica, and said second mask layer 605 adopts silicon nitride; Perhaps, when said substrate 601 was silica, said first mask layer 603 adopted silicon nitride, and said second mask layer 605 adopts polysilicon.
As shown in Figure 7; Said first mask layer 603 of anisotropic etching and second mask layer 605; In said first mask layer 603 and second mask layer 605, form first figure; Said first graphics package contains a plurality of first flagpole patterns 607, and 607 adjacent of first flagpole patterns are formed with first opening 609, and said first opening 609 exposes substrate 601 surfaces.
In specific embodiment; Said anisotropic etching using plasma etching technics; Said plasma etch process needs on said second mask layer 605, to form earlier the photoresist layer (not shown) that has with the identical figure of first figure, and said photoresist layer is promptly as the mask of anisotropic etching first mask layer 603 and second mask layer 605.
As shown in Figure 8, said second mask layer 605 of side direction partial etching makes the width of second mask layer, 605 first flagpole patterns reduce, thereby part first mask layer 603 under former second mask layer 605 is exposed.In specific embodiment, after the side direction etching, the width of said second mask layer 605 can be identical with the width of first opening 609.The degree of depth of said second mask layer, 605 side direction etchings is 10 nanometer to 50 nanometers, and corresponding, the width of second mask layer, 605 first flagpole patterns reduces 10 nanometer to 50 nanometers.And first flagpole pattern of said second mask layer 605 reduces along its bilateral symmetry.
In specific embodiment, after second mask layer 605 and first mask layer 603 are by plasma etching, can select to keep the photoresist layer on said second mask layer 605 or remove said photoresist layer.If said photoresist layer is not removed before the side direction etching; Be mask then, adopt isotropic dry etch technology or said second mask layer 605 of wet-etching technology partial etching, at this moment with said photoresist layer; The side direction etching only takes place in second mask layer 605, then removes said photoresist layer again; If said photoresist layer is removed before the side direction etching; Then there is not etch mask on second mask layer 605; In the side direction etching processing; It also can be by vertical etching, and said second mask layer, 605 first flagpole patterns should be less than the thickness of second mask layer 605, to guarantee that said second mask layer 605 can not removed fully after the side direction etching by the degree of depth of side direction etching.
Because first mask layer 603 and second mask layer 605 have bigger etching selection ratio, therefore, in said second mask layer, 605 side direction etchings, first mask layer 603 can't be etched, and promptly still is first figure.
As shown in Figure 9, on said substrate 601, form the 3rd mask layer 611, said the 3rd mask layer 611 surpasses the top of second mask layer 605, and first mask layer 603 and second mask layer 605 are covered fully.In specific embodiment, the thickness of said the 3rd mask layer 611 surpass first mask layer 603 and second mask layer, 605 thickness and, its thickness range is 20 nanometer to 300 nanometers.
In specific embodiment, said the 3rd mask layer 611 comprises: polysilicon, amorphous silicon, silica, silicon nitride, silicon oxynitride, metal, metal oxide, metal nitride, amorphous carbon or other are easy to film forming material.
In practical application, said the 3rd mask layer 603 should all have relatively large etching selection ratio with first mask layer 603 and second mask layer 605.For example, said first mask layer 603 adopts silica, and when said second mask layer 605 adopted silicon nitride, said the 3rd mask layer 611 adopted amorphous carbon; Perhaps, said first mask layer 603 adopts silicon nitride, and when said second mask layer 605 adopted polysilicon, said the 3rd mask layer 611 adopted amorphous carbon.
Shown in figure 10, return the 3rd mask layer 611 of carving said second mask layer 605 tops, make said second mask layer 605 expose.In specific embodiment, can adopt dry etching, wet etching or CMP process to return and carve said the 3rd mask layer 611.
Shown in figure 11, after second mask layer 605 exposes, be mask with the 3rd mask layer 611, remove said second mask layer 605.Like this, former second mask layer 605 positions in former the 3rd mask layer 611 have formed second opening 613, and said second opening 613 exposes the mask layer 603 of winning.
In specific embodiment, can adopt isotropic dry etching or wet-etching technology to remove said second mask layer 605.
Shown in figure 12, then, be mask still with said the 3rd mask layer 611, first mask layer 603 of said second opening of anisotropic etching 613 belows is until exposing substrate 601 surfaces.Said etching makes second opening 613 extend to first mask layer 603.Simultaneously, second opening 613 in said first mask layer 603 is divided into two parts with each first flagpole pattern of first mask layer 603, and this makes the width of first flagpole pattern be able to reduce.
Shown in figure 13; Remove said the 3rd mask layer; Only keep first mask layer 603 on the substrate 601, like this, first mask layer 603 of original first figure is transformed to second graph; First mask layer 603 of said second graph is made up of a plurality of second flagpole patterns 615, and 615 adjacent of two second flagpole patterns are formed with one first opening 609 or second opening 613.According to the difference of specific embodiment, said first opening 609 can have identical width or different widths with second opening 613.In the preferred embodiment, said first opening 609 has identical width with second opening 613, and like this, a plurality of second flagpole patterns 615 that comprise in the said second graph can be arranged on the substrate 601 by equidistance.Than first flagpole pattern, the width of said second flagpole pattern 615 reduces, and under the condition of not changing lithographic equipment, the pitch minimum value of first figure is broken through the restriction of photoetching resolution, thereby effectively improves the integrated level of chip.
Because said first mask layer 603 all has mask to cover when etching; Therefore; The cross section of second flagpole pattern of said first mask layer 603 is a rectangle, and thickness is comparatively even, and first mask layer 603 of said square-section can be used as the mask of subsequent etching substrate 601; In addition, said first mask layer 603 directly forms on substrate 601, need not to make side wall construction, and the thickness of said first mask layer 603 can accurately be controlled, and this has further improved the uniformity of first mask layer 603.When etched substrate 601, first mask layer 603 of said uniform thickness has been avoided the uneven problem of etching, has effectively improved etching effect.
Though the present invention discloses as above with preferred embodiment, the present invention is defined in this.Any those skilled in the art are not breaking away from the spirit and scope of the present invention, all can do various changes and modification, so protection scope of the present invention should be as the criterion with claim institute restricted portion.
Claims (14)
1. a double-pattern method is characterized in that, comprising:
Substrate is provided, is formed with first mask layer and second mask layer on the said substrate successively;
Said first mask layer of anisotropic etching and second mask layer form first opening in said first mask layer and second mask layer, said first opening exposes substrate surface;
Said second mask layer of side direction partial etching;
On said substrate, form the 3rd mask layer, said the 3rd mask layer covers first mask layer, and makes second mask layer expose;
Remove said second mask layer, in the 3rd mask layer, form second opening, said second opening exposes the mask layer of winning;
With the 3rd mask layer is mask, and first mask layer of anisotropic etching second opening below is until exposing substrate;
Remove said the 3rd mask layer.
2. double-pattern method as claimed in claim 1 is characterized in that, adopts chemical vapor deposition or physical vapor deposition on said substrate, to form first mask layer and second mask layer successively.
3. double-pattern method as claimed in claim 1 is characterized in that, said first mask layer comprises: polysilicon, amorphous silicon, silica, silicon nitride, silicon oxynitride, metal, metal oxide, metal nitride or amorphous carbon.
4. double-pattern method as claimed in claim 1 is characterized in that, said second mask layer comprises: polysilicon, amorphous silicon, silica, silicon nitride, silicon oxynitride, metal, metal oxide, metal nitride or amorphous carbon.
5. double-pattern method as claimed in claim 1 is characterized in that, the degree of depth of said second mask layer of said side direction partial etching is 10 nanometer to 50 nanometers.
6. double-pattern method as claimed in claim 1 is characterized in that, said second mask layer of said side direction partial etching comprises: adopt isotropic dry etch technology or said second mask layer of wet-etching technology partial etching.
7. double-pattern method as claimed in claim 1 is characterized in that, said the 3rd mask layer comprises: polysilicon, amorphous silicon, silica, silicon nitride, silicon oxynitride, metal, metal oxide, metal nitride or amorphous carbon.
8. double-pattern method as claimed in claim 1 is characterized in that, the thickness of said the 3rd mask layer is 20 nanometer to 300 nanometers.
9. double-pattern method as claimed in claim 1; It is characterized in that; Saidly remove said second mask layer; In the 3rd mask layer, form second opening, said second opening exposes the mask layer of winning to comprise: adopt isotropic dry etching or wet-etching technology to remove said second mask layer.
10. double-pattern method as claimed in claim 1 is characterized in that, said the 3rd mask layer that on said substrate, forms, and said the 3rd mask layer covers first mask layer, and makes second mask layer expose to comprise:
On said substrate, form the 3rd mask layer, the thickness of said the 3rd mask layer surpasses the second mask layer top;
Return and carve said the 3rd mask layer until exposing second mask layer.
11. double-pattern method as claimed in claim 10 is characterized in that, carves said the 3rd mask layer and comprises until exposing second mask layer for said time: adopt chemico-mechanical polishing, dry etching or wet-etching technology to return and carve said the 3rd mask layer.
12. double-pattern method as claimed in claim 1 is characterized in that, the width behind the said second mask layer side direction partial etching is identical with the width of first opening.
13. double-pattern method as claimed in claim 1 is characterized in that, said first mask layer adopts silica, and said second mask layer adopts silicon nitride, and said the 3rd mask layer adopts amorphous carbon.
14. double-pattern method as claimed in claim 1 is characterized in that, said first mask layer adopts silicon nitride, and said second mask layer adopts polysilicon, and said the 3rd mask layer adopts amorphous carbon.
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| CN102881565A (en) * | 2012-10-22 | 2013-01-16 | 上海集成电路研发中心有限公司 | Method for forming metal-oxide-metal (MOM) capacitor |
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| CN103681232A (en) * | 2012-09-04 | 2014-03-26 | 中芯国际集成电路制造(上海)有限公司 | Production method for semiconductor device |
| CN103794551A (en) * | 2012-11-05 | 2014-05-14 | 中国科学院微电子研究所 | Method for defining contacts through adoption of e-beam process |
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| CN103943469A (en) * | 2014-05-08 | 2014-07-23 | 上海华力微电子有限公司 | Self-aligning forming method for figure |
| CN105565252A (en) * | 2014-10-10 | 2016-05-11 | 中芯国际集成电路制造(上海)有限公司 | MEMS (Micro-Electro-Mechanical System) device, manufacturing method thereof and electronic device |
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| CN109216163A (en) * | 2017-06-29 | 2019-01-15 | 中芯国际集成电路制造(上海)有限公司 | The manufacturing method of semiconductor devices |
| CN110416067A (en) * | 2018-04-30 | 2019-11-05 | 台湾积体电路制造股份有限公司 | The manufacturing method of semiconductor device |
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