CN102412937B - Data interleaving method and device - Google Patents

Abstract

The invention discloses a data interleaving method and a data interleaving device, which are used for improving the interleaving performance of an interleaving process. In the invention, different interleaving patterns are respectively configured for two or more interleavers; and in the process of interleaving, the two or more interleavers perform interleaving operation on input data respectively according to the configured interleaving patterns thereof. By adopting the technical scheme of the invention, for parts (different in target positions) of data (same in defined initial positions) in two or more interleaving patterns, two bits (same in input sequence) after respectively being interleaved by the two or more interleavers can produce an interleaving gain, namely, the distance between the two bits is changed, thereby improving the interleaving performance of the interleaving process.

Description

A kind of deinterleaving method of data and device

Technical field

The present invention relates to communication technical field, relate in particular to a kind of deinterleaving method and device of data.

Background technology

HSDPA (High Speed Downlink Packet Access, high speed downlink packet access) the descending Radio Transmission Technology as a kind of enhancing was introduced in 3GPP (3rd Generation Partnership Project in 2002, third generation collaborative project) the 5th edition (Release 5, be called for short " R5 ") in and 3GPP the 6th edition, (Release 6, abbreviation " R6 ") in, carried out further improvement, due to the link adaptation techniques having adopted based on Adaptive Modulation and Coding, HARQ based on physical layer retransmission and soft merging (Hybrid automatic repeat request, mixed automatic retransfer request), quick multi-user's packet scheduling, the key technologies such as the short frame of 2ms, there is spectrum efficiency high, downlink transfer speed is large, the obvious advantage of the little grade of propagation delay time, thereby can provide effective twelve Earthly Branches to hold to Packet data service.

E-DCH (Enhanced Dedicated Transport Channel, enhancing special uplink channel) be called again HSUPA (High Speed Uplink Packet Access, high speed uplink packet access), it is the Radio Transmission Technology of another enhancing of introducing in Release 6 continue introduce HSDPA in Release 5 after of 3GPP, due to the up fast packet scheduling having adopted based on Node B (Node B), the key technologies such as Fast HARQ and the short frame of 2ms, it is high that E-DCH has spectrum efficiency, uplink transmission rate is fast, the obvious advantage of the little grade of propagation delay time, thereby more effectively support real-time game business, file is uploaded, the Packet data service application such as broadband multimedia services.

At present, at HS-DSCH (High Speed Downlink Shared Channel, high speed descending sharing channel) in code multiplexing process, the 2ms TTI of HS-DSCH (Transmission Time Interval, Transmission Time Interval) carry at most 1 data fast, each HS-DSCH data block of the multiplexing chain of input coding is mapped to the HS-DSCH subframe of 3 time slots after code multiplexing.The code multiplexing process of HS-DSCH mainly comprises following several step: transmission block increases the cutting apart of cyclic redundancy check information, bit scramble, encoding block, chnnel coding, HARQ (Hybrid automatic repeat request, mixed automatic retransfer request), physical channel segmentation, interweave, the mapping of 16QAM (Quadrature Amplitured Modulation, quadrature amplitude modulation) constellation rearrangement, physical channel.

While interweaving in the code multiplexing process of HS-DSCH, the interleaving process of each physical channel is independent.The bit sequence (being data) that is input to block interleaver is u _{p, 1}, u _{p, 2}, u _{p, 3}..., u _{p, U}wherein p is physical channel (PhCH, Physical Channel) number, if the modulation system that the code multiplexing process of HS-DSCH adopts is 16QAM modulation, U=1920, adopts the interleaver of two same sizes, is R2 * C2=32 * 30 at present, be line number R2=32, the interleaver of columns C2=30.The bit sequence of physical channel segmentation module output is cut apart between two between interleaver, bit u _{p, k}and u _{p, k+1}send to the first interleaver, bit u _{p, k+2}and u _{p, k+3}send to the second interleaver, the output bit sequence of two interleavers according to the order combination between two distributing, is specially bit v again _{p, k}and v _{p, k+1}from the first interleaver output, and bit v _{p, k+2}and v _{p, k+3}from the second interleaver output, k mod 4=1 herein, k is that 1, k is positive integer divided by 4 remainders, later bit sequence is by that analogy.

Visible, when adopting 16QAM modulation system, adopt the interleaver of two same sizes (R2 * C2=32 * 30), from the bit v of the first interleaver output _{p, k}and v _{p, k+1}because thering is through interweaving of the first interleaver the gain that interweaves, from the bit v of the second interleaver output _{p, k+2}and v _{p, k+3}because thering is through interweaving of the second interleaver the gain that interweaves.But because two interleavers interweave according to identical rule, so v _{p, k+2}with v _{p, k}between the gain that do not interweave, v _{p, k+3}with v _{p, k+1}between the gain that do not interweave, that is, and through after interweaving, u _{p, k}and u _{p, k+2}distance do not change.Similarly in the interlace operation of problem in E-DCH, also exist.

Summary of the invention

The embodiment of the present invention provides a kind of deinterleaving method and device of data, in order to improve the felt properties of interleaving process.

In order to solve the problems of the technologies described above, the embodiment of the present invention provides a kind of deinterleaving method of data, comprises the following steps:

For two or more interleavers configure respectively the different patterns that interweaves; And

When interweaving, described two or more interleavers carry out interlace operation according to the pattern that interweaves for its configuration to input data respectively.

The present invention also provides a kind of interlaced device, and described interlaced device comprises draws together two or more interleavers and configuration module, wherein:

Described interleaver, carries out interlace operation for the pattern that interweaves according to configuration to input data;

Described configuration module, is used to described two or more interleavers to configure respectively the different patterns that interweaves.

The technical scheme that adopts the embodiment of the present invention to provide, for two or more, interweave in pattern, the different part in target location of the data that definition initial position is identical, identical two bits of input sequence are respectively through after the interweaving of two or more interleavers, can produce the gain that interweaves, there is variation in the distance of these two bits, thereby can improve the felt properties of interleaving process.

Accompanying drawing explanation

Fig. 1 is the flow chart that interweaves carrying out in the first interleaver in the embodiment of the present invention;

Fig. 2 is the interlaced device block diagram of the embodiment of the present invention.

Embodiment

The embodiment of the present invention be take and is applied in HS-DSCH and E-DCH is example, but is not limited in the code multiplexing process that is applied in HS-DSCH and E-DCH, and other process or device that relates to a plurality of interleavers is all similar with it.

Below in conjunction with accompanying drawing, the embodiment of the present invention is done further and described.

Embodiment mono-

In embodiment mono-, the code multiplexing process of the HS-DSCH that the employing 16QAM of take modulates is example, in this process, adopt the interleaver of two same sizes to interweave to input bit, these two interleavers are R2 * C2=32 * 30, input bit is divided between two to two-way bit sequence, bit u between these two interleavers _{p, k}and u _{p, k+1}send to the first interleaver, bit u _{p, k+2}and u _{p, k+3}send to the second interleaver, the output bit sequence of two interleavers according to the order combination between two distributing, is specially bit v again _{p, k}and v _{p, k+1}from the first interleaver output, and bit v _{p, k+2}and v _{p, k+3}from the second interleaver output, k mod4=1 herein, later bit sequence is by that analogy.

In embodiment mono-, for these two interleavers configure respectively the different patterns that interweaves, wherein, the pattern that respectively interweaves be take and only the initial position of input bit sequence is defined into target location as example by row, in specific implementation, the pattern that interweaves that interleaver adopts can be defined into the initial position of input bit sequence target location or by cell, the initial position of input bit sequence is defined into target location by row by row, and in embodiment mono-, the pattern that interweaves of the first interleaver is as shown in table 1:

Table 1

If the list entries u of the first interleaver _{p, 1}, u _{p, 2}, u _{p, 3}..., u _{p, U}between being listed as in the first interleaver, after exchange, filtering filling bit is from the first interleaver output sequence v _{p, 1}, v _{p, 2}..., v _{p, U}.The interleaving process carrying out in the first interleaver as shown in Figure 1, comprises the following steps:

Step S101, by input bit sequence u _{p, 1}, u _{p, 2}, u _{p, 3}..., u _{p, U}y from the 0th row, the 0th row _{p, 1}start to write line by line matrix R2 * C2;

This matrix column from left to right be numbered 0,1,2 ..., C2-1; The row of this matrix is numbered 0,1,2 from top to bottom ..., R2-1.Matrix R2 * the C2 having write is:

$\left[\begin{array}{ccccc}{y}_{p,1}& y_{p,2}& y_{p,3}& ...& y_{p,C2}\\ y_{p,(C2+1)}& y_{p,(C2+2)}& y_{p,(C2+3)}& ...& y_{p,(2\×C2)}\\ .& .& .& & .\\ .& .& .& ...& .\\ .& .& .& & .\\ y_{p,((R2-1)\×C2+1)}& y_{p,((R2-1)\×C2+2)}& y_{p,((R2-1)\×C2+3)}& ...& y_{p,(R2\×C2)}\end{array}\right]$

Wherein, y _{p, k}=u _p, k, k=1,2 ..., U; If R2 * C2 > is U, at k=U+1, U+2 ..., during R2 * C2, in this matrix, add filling bit, even y _{p, k}=0 or make y _{p, k}=1.After exchanging according to the pattern that interweaves, in the output sequence of matrix, delete this filling bit.In embodiment mono-, due in HSDPA (High speed downlink packet access, high speed downlink packet access), for 16QAM, for each road interleaver, the length of list entries is 32 * 30, therefore without filling bit.

Step S102, according to pattern <P2 (j) > that interweaves shown in table 1 _{j ∈ 0,1 ..., C2-1}}row exchange between this matrix is listed as;

Wherein P2 (j) is the initial position of j exchange row.Bit after this row exchange is y ' _{p, k}, and matrix after the exchange of this row is:

$\left[\begin{array}{ccccc}{y^{\&prime;}}_{p,1}& {y^{\&prime;}}_{p,(R2+1)}& {y^{\&prime;}}_{p,(2\&times;R2+1)}& ...& {y^{\&prime;}}_{p,((C2-1)\&times;R2+1)}\\ {y^{\&prime;}}_{p,2}& {y^{\&prime;}}_{p,(R2+2)}& {y^{\&prime;}}_{p,(2\&times;R2+2)}& ...& {y^{\&prime;}}_{p,((C2-1)\&times;R2+2)}\\ .& .& .& & .\\ .& .& .& ...& .\\ .& .& .& & .\\ {y^{\&prime;}}_{p,R2}& {y^{\&prime;}}_{p,(2\&times;R2)}& {y^{\&prime;}}_{p,(3\&times;R2)}& ...& {y^{\&prime;}}_{p,(C2\&times;R2)}\end{array}\right]$

Step S103, exports by column to exchanging the bit of rear matrix.

Bit after exchange between R2x C2 matrix column, output sequence by column, i.e. input bit y during corresponding k > U _{p, k}being output as bit is y ' _{p, k}.Output bit sequence is v _{p, 1}, v _{p, 2}..., v _{p, U}, v wherein _{p, 1}for output subscript k be minimum bit y ' _{p, k}, v _{p, 2}for the subscript k exporting is time little bit y ' _{p, k}, the like.

The interleaving process carrying out in the second interleaver is identical with the interleaving process carrying out in the first interleaver, be only according to the pattern difference that interweaves.After obtaining the first interleaved sequence of the first interleaver output and the second interleaved sequence of the second interleaver output, by the first interleaved sequence and the second interleaved sequence according to the order combination between two distributing.

Due in the present embodiment, only require that the first interleaver is different with the pattern that interweaves that the second interleaver adopts, therefore, for two, interweave in pattern, the different part in the target location of the identical data of definition initial position is (for embodiment mono-, for exchanging the different part in target location corresponding to initial position of row in two patterns that interweave, identical two bits of input sequence are respectively through after the interweaving of two interleavers, can produce the gain that interweaves), identical two bits of input sequence are respectively through after the interweaving of two interleavers, can produce the gain that interweaves, there is variation in the distance of these two bits.For example, what at the first interleaver, adopt interweaves in pattern, initial position is that the target location of 0 row is still 0, and interweaving in pattern of adopting at the second interleaver, the target location of the row that initial position is 0 is 30, visible, the bit of the bit of the first interleaver output and the output of the second interleaver is carried out in conjunction with time, the initial position of two interleavers output is 0 be listed in and interweave after, having there is variation in distance, has produced the gain that interweaves.

In the present embodiment, the pattern that interweaves that two interleavers are adopted does not need concrete restriction, but, in order all to there is the gain that interweaves between the bit that two interleavers are exported, these two different interweaving in pattern, should guarantee the row that each initial position is identical, its target location is not identical as far as possible.

And due to not concrete restriction of pattern that interweave that two interleavers are adopted, therefore, the storage overhead bringing in order to reduce storage to interweave pattern, in the present embodiment, can only preserve the pattern that interweaves that an interleaver adopts, and be used as with the distortion of this pattern that interweaves the pattern that interweaves that another interleaver adopts.In embodiment mono-, the pattern that interweaves that the first interleaver adopts is the pattern that interweaves shown in table 1, and the pattern that interweaves that the second interleaver adopts can obtain according to the distortion of the pattern that interweaves shown in table 1, the mode of carrying out this distortion has a lot, for example, adopt the pattern that interweaves shown in following several mode his-and-hers watches 1 to be out of shape:

Mode one

The pattern that interweaves of the second interleaver is the backward of the pattern that interweaves of the first interleaver, and the pattern that interweaves shown in table 1 being carried out to corresponding deformation, to obtain the pattern that interweaves of the second interleaver as shown in table 2:

Table 2

Mode two

Generating the interweaving during pattern of the second interleaver, first the pattern that interweaves of the first interleaver is carried out to backward arrangement, then the first half of the pattern that interweaves after backward is arranged and latter half exchange, the pattern that interweaves of the second interleaver obtaining is as shown in table 3:

Table 3

Mode three

The pattern that interweaves of the second interleaver is that the first half of the pattern that interweaves and the latter half of the first interleaver exchanges, and the pattern that interweaves shown in table 1 being carried out to corresponding deformation, to obtain the pattern that interweaves of the second interleaver as shown in table 4:

Table 4

Visible, because the pattern that interweaves obtaining according to above-mentioned variety of way is to be out of shape and to obtain through simple processing on the basis of the pattern that interweaves shown in table 1, do not need other buffer memory to store this pattern that interweaves, saved storage overhead, and, because this deformation process is very simple, can't increase because of this deformation process the complexity of interleaving treatment.

When specific implementation, yet can according to the pattern that interweaves of storage, not be out of shape and generate another pattern that interweaves, but directly preserve two patterns that interweave, these two patterns that interweave can configure as required, as long as guarantee that two patterns that interweave are different.For example, the pattern that interweaves that makes the second interleaver is a random alignment of the pattern that interweaves of the first interleaver, i.e. 1～30 random alignment, but should guarantee that two patterns that interweave are not identical.In the situation that directly two of preservations interweave pattern, need to increase certain storage overhead, but because the required memory space of intersection chart sample body is little, therefore, the storage overhead of its increase can not cause the burden that system is larger yet.

Embodiment bis-

In embodiment bis-, the code multiplexing process of the HS-DSCH that the employing 64QAM of take modulates is example, in this process, adopt the interleaver of three same sizes to interweave to input bit, these three interleavers are R2 * C2=32 * 30, input bit is divided into three tunnel sequences, bit u between these three interleavers _{p, k}and u _{p, k+1}send to the first interleaver, bit u _{p, k+2}and u _{p, k+3}send to the second interleaver, bit u _{p, k+4}and u _{p, k+5}send to the 3rd interleaver, each road sequence interweaves respectively, and the output bit sequence of three interleavers carries out combination according to the order of distributing again, is specially bit v _{p, k}and v _{p, k+1}from the first interleaver output, bit v _{p, k+2}and v _{p, k+3}from the second interleaver output, bit v _{p, k+4}and v _{p, k+5}from the first interleaver output, later bit sequence by that analogy.

In embodiment bis-, equally, as long as guarantee that the pattern that interweaves of each interleaver employing is not identical, so, for the different part in target location corresponding to initial position of exchange row in three any two patterns that interweave that interweave in pattern, identical two bits of input sequence through after the interweaving of two interleavers, can produce the gain that interweaves respectively, the situation that adopts same interlace pattern compared with each interleaver, can obtain the effect that better interweaves.

Visible, when adopting two or more interleavers to interweave, as long as adopt the mutually different pattern that interweaves, just can obtain the effect that better interweaves.In addition, if guarantee all to have the gain that interweaves between each bit, need to guarantee in this two or more different interweaving in pattern, should be as far as possible by the identical data definition of initial position to different target locations.

Embodiment tri-

In embodiment tri-, the E-DCH that adopts 4PAM to modulate of take is example, in this process, adopts the interleaver that the identical size of two-way is R2x30, and wherein R2 is for meeting

smallest positive integral.Input bit enters two-way interleaver successively.U _{p, k}enter first via interleaver, u _{p, k+1}enter the second road interleaver.Through after the interweaving of two-way interleaver, from two interleavers, read bit successively and export, be i.e. v _{p, k}from first interleaver, v _{p, k+1}from second interleaver, wherein k mod 2=1.Such as the length bit sequence that is 60, its index is followed successively by: 1, 2, ..., 60, wherein index is { 1, 3, 5, 7, 9, 11, 13, 15, 17, 19, 21, 23, 25, 27, 29, 31, 33, 35, 37, 39, 41, 43, 45, 47, 49, 51, 53, 55, 57, the sequence of 59} enters the first interleaver, index is { 2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 26, 28, 30, 32, 34, 36, 38, 40, 42, 44, 46, 48, 50, 52, 54, 56, 58, the bit of 60} enters the second road interleaver.

If two interleavers adopt same interlace pattern as shown in table 1, through after the interweaving of first via interleaver, the corresponding index of output bit is: { 1, 41, 21, 11, 31, 51, 7, 27, 47, 17, 37, 57, 3, 23, 43, 13, 33, 53, 9, 29, 49, 39, 19, 59, 25, 5, 15, 45, 55, 35}, through after the interweaving of the second road interleaver, the corresponding index of output bit is: { 2, 42, 22, 12, 32, 52, 8, 28, 48, 18, 38, 58, 4, 24, 44, 14, 34, 54, 10, 30, 50, 40, 20, 60, 26, 6, 16, 46, 56, 36}, , by the output bit of two interleavers carry out in conjunction with after the index of the bit sequence that obtains be: { 1, 2, 41, 42, 21, 22, 11, 12, 31, 32, 51, 52, 7, 8, 27, 28, 47, 48, 17, 18, 37, 38, 57, 58, 3, 4, 23, 24, 43, 44, 13, 14, 33, 34, 53, 54, 9, 10, 29, 30, 49, 50, 39, 40, 19, 20, 59, 60, 25, 26, 5, 6, 15, 16, 45, 46, 55, 56, 35, 36}.

Visible, through after the interweaving of two interleavers, list entries index is the gain that do not interweave between k and the input bit of k+1, that is, list entries index is that 1,2 bit, list entries index are the gain that all do not interweave of 41,42 ratio top grade.

If and make the first interleaver adopt the as shown in table 1 pattern that interweaves, and the second interleaver adopts the as shown in table 2 pattern that interweaves, and making length as above is that the bit that the index of 60 bit sequence is odd number is inputted the first interleaver, the index of the output bit sequence of the first interleaver is { 1, 41, 21, 11, 31, 51, 7, 27, 47, 17, 37, 57, 3, 23, 43, 13, 33, 53, 9, 29, 49, 39, 19, 59, 25, 5, 15, 45, 55, 35}, and the bit that the index of the bit sequence that this length is 60 is even number is inputted the second interleaver, the index of the output bit sequence of the second interleaver is { 36, 56, 46, 16, 6, 26, 60, 20, 40, 50, 30, 10, 54, 34, 14, 44, 24, 4, 58, 38, 18, 48, 28, 8, 52, 32, 12, 22, 42, 2}., the output bit of two interleavers is carried out in conjunction with after the index of the bit sequence that obtains be: { 1,36,41,56,21,46,11,16,31,6,51,26,7,60,27,20,47,40,17,50,37,30,57,10,3,54,23,34,43,14,13,44,33,24,53,4,9,58,29,38,49,18,39,48,19,28,59,8,25,52,5,32,15,12,45,22,55,42,35,2}.

Visible, two interleavers are interweaving during pattern shown in employing table 1 and table 2 respectively, and the bit that when each is inputted, index is adjacent has all interweaved out, can obtain larger interweave gain and the effect that better interweaves.When specific implementation, as long as make two interleavers adopt respectively the different patterns that interweaves.

Interlaced device in the embodiment of the present invention as shown in Figure 2, comprises two or more interleavers and configuration module, wherein:

These two or more interleavers, carry out interlace operation for the pattern that interweaves according to configuration to input data;

Configuration module, is used to these two or more interleavers to configure respectively the different patterns that interweaves.

In this configuration module, can comprise the second memory cell, the different pattern that interweaves configuring respectively for save as these two or more interleavers simultaneously.

But the storage overhead bringing in order to reduce storage to interweave pattern, in this interlaced device, in the time of can be different, save as the different pattern that interweaves that these two or more interleavers configure respectively, but only save as the pattern that interweaves that one of them interleaver configures, therefore, this configuration module can comprise the first memory cell and dispensing unit, wherein:

The first memory cell, for saving as first of one of them interleaver configuration pattern that interweaves;

Dispensing unit, generates the different with it patterns that interweaves and configures to other interleavers for first pattern that interweaves of preserving according to the first memory cell.

In sum, the technical scheme that adopts the embodiment of the present invention to provide, for two or more, interweave in pattern, the different part in target location of the data that definition initial position is identical, identical two bits of input sequence are respectively through after the interweaving of two or more interleavers, can produce the gain that interweaves, there is variation in the distance of these two bits, thereby can improve the felt properties of interleaving process.And this scheme realizes simple, can increase storage overhead simultaneously.

Obviously, those skilled in the art can carry out various changes and modification and not depart from the spirit and scope of the present invention the present invention.Like this, if within of the present invention these are revised and modification belongs to the scope of the claims in the present invention and equivalent technologies thereof, the present invention is also intended to comprise these changes and modification interior.

Claims (10)

1. a deinterleaving method for data, is characterized in that, comprises the following steps:

For two or more interleavers configure respectively the different patterns that interweaves; And

When interweaving, described two or more interleavers carry out interlace operation according to the pattern that interweaves for its configuration to input data respectively;

Described input data are split into two-way or the above bit sequence of two-way, two-way after cutting apart or bit sequence more than two-way are sent to corresponding interleaver and interweave, and the bit sequence of two or more interleaver outputs carries out combination according to the order of distributing again, wherein, described two or more interleavers have same size.

2. the method for claim 1, it is characterized in that, describedly configure respectively the different patterns that interweaves and specifically comprise for two or more interleavers: be first one of them interleaver configuration first pattern that interweaves, and according to this first interweave pattern generation with it the different pattern that interweaves configure to other interleavers.

3. method as claimed in claim 2, is characterized in that, the pattern that interweaves of described generation comprises: this first pattern that interweaves is carried out backward and arranges the pattern that interweaves obtain.

4. method as claimed in claim 2, is characterized in that, the pattern that interweaves of described generation comprises: first this first pattern that interweaves is carried out to backward arrangement, then the pattern that interweaves that obtains of the first half of the pattern that interweaves after backward is arranged and latter half exchange.

5. method as claimed in claim 2, is characterized in that, the pattern that interweaves of described generation comprises: this first first half and latter half that interweaves pattern is exchanged to the pattern that interweaves obtaining.

6. the method as described in arbitrary claim in claim 1 to 5, is characterized in that, is respectively interweaving in pattern, and the data definition that initial position is identical arrives different target locations.

7. the method as described in arbitrary claim in claim 1 to 5, is characterized in that, described interlace operation carries out in the code multiplexing process of high speed descending sharing channel or enhancing special uplink channel.

8. an interlaced device, is characterized in that, described interlaced device comprises two or more interleavers and configuration module, wherein:

Described interleaver, carries out interlace operation for the pattern that interweaves according to configuration to input data; Described input data are split into two-way or the above bit sequence of two-way, two-way after cutting apart or bit sequence more than two-way are sent to corresponding interleaver and interweave, and the bit sequence of two or more interleaver outputs carries out combination according to the order of distributing again, and described two or more interleavers have same size;

Described configuration module, is used to described two or more interleavers to configure respectively the different patterns that interweaves.

9. device as claimed in claim 8, is characterized in that, described configuration module also comprises the first memory cell and dispensing unit, wherein:

Described the first memory cell, for saving as first of one of them interleaver configuration pattern that interweaves;

Described dispensing unit, generates the different with it patterns that interweaves and configures to other interleavers for first pattern that interweaves of preserving according to described the first memory cell.

10. device as claimed in claim 8, is characterized in that, described configuration module also comprises the second memory cell, the different pattern that interweaves configuring respectively for save as described two or more interleavers simultaneously.

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