CN102384999B - A kind of high-speed transmission event detection method and circuit - Google Patents
A kind of high-speed transmission event detection method and circuit Download PDFInfo
- Publication number
- CN102384999B CN102384999B CN201010268513.2A CN201010268513A CN102384999B CN 102384999 B CN102384999 B CN 102384999B CN 201010268513 A CN201010268513 A CN 201010268513A CN 102384999 B CN102384999 B CN 102384999B
- Authority
- CN
- China
- Prior art keywords
- voltage
- signal
- current
- pmos
- current signal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Landscapes
- Manipulation Of Pulses (AREA)
- Dc Digital Transmission (AREA)
Abstract
The embodiment of the invention discloses a kind of high-speed transmission event detection method and circuit, pass through due to first in the embodiment of the present invention, the voltage signal of input can be converted to current signal by two voltage current adapters, by the differential voltage signal of input just, whether the voltage difference of negative signal is greater than the judgement of the reference voltage level of input, whether the current value being converted into the current signal of output is greater than the current value exporting reference current signal, only need more once in each comparer, thus under equal comparator circuit condition, improve the speed of the processing signals of comparer.
Description
Technical field
The present invention relates to Data Detection field, be specifically related to a kind of high-speed transmission event detection method and circuit.
Background technology
High-speed transfer event detector is widely used in USB (universal serial bus) (USB, Universal SeriesBus) receiving equipment, for carrying out noise elimination process to the data of input USB receiving equipment.High-speed transfer event detector, according to the amplitude of the differential signal voltage detected in USB interface, judges that the signal that the differential signal line in USB interface transmits is noise or valid data.When the amplitude of differential signal voltage is less than minimum reception amplitude, high-speed transfer event detector is closed or shielding differential data receiver, prevents noise to be converted to mathematical logic signal through receiver and enters subsequent conditioning circuit; When the amplitude of differential signal voltage is greater than minimum reception amplitude, what high-speed transfer event detector was judged differential signal line transmits is valid data, then high-speed transfer event detector allows this differential signal to be input to receiver.
Prior art high speed transmission events detecting device comprises: 2 differential amplifiers and 2 comparers.Wherein, the reference high voltage signal of a differential amplifier differential amplification input and the low reference voltage signal of input, export a reference high voltage signal amplified and a low reference voltage signal amplified; The differential signal of another differential amplifier differential amplification input, exports the differential signal amplified; A comparer compares the differential signal of input and the reference high voltage signal of amplification, and when differential signal is respectively all lower than the reference high voltage signal amplified, this comparer exports as high; Another comparer compares the differential signal of input and the low reference voltage signal of amplification, and when differential signal is respectively all higher than the low reference voltage signal amplified, this comparer exports as high; When the output of two comparers is all high, the differential signal that this detecting device detects is useful signal, otherwise is noise.
By finding the research of prior art, in prior art, comparer compares the voltage of each signal in the differential signal of input and the reference high voltage (or the low reference voltage of amplifying) amplified, need in each comparer to carry out respectively comparing for twice, reduce the processing speed of comparer.
Summary of the invention
Embodiments provide a kind of high-speed transmission event detection method and circuit, can detection speed be improved.
The embodiment of the present invention provides a kind of high-speed transfer event detection circuit, comprising:
First voltage current adapter, for the differential voltage signal of input is converted to differential current signal, wherein, described differential current signal comprises: positive current signal and negative current signal;
Second voltage current adapter, for the reference voltage signal of input is converted to reference difference current signal, described reference difference current signal comprises: positive reference current signal and negative reference current signal; Wherein, the first voltage current adapter and the second voltage current adapter have the common mode value of identical Voltage to current transducer coefficient and identical output difference current;
First comparer, for the size of the current value of more described positive current signal and described positive reference current signal;
Second comparer, for the size of the current value of more described negative current signal and described positive reference current signal;
Output circuit, for when the current value of positive reference current signal is less than the current value of positive current signal, or when the current value of positive reference current signal is less than the current value of negative current signal, export the first magnitude of voltage, described first magnitude of voltage represents that the differential voltage signal of described input is useful signal.
The embodiment of the present invention also provides a kind of high-speed transmission event detection method, comprising:
The differential voltage signal of input is converted to differential current signal, and wherein, described differential current signal comprises: positive current signal and negative current signal;
The reference voltage signal of input is converted to reference difference current signal, and described reference difference current signal comprises: positive reference current signal and negative reference current signal; Wherein, the differential voltage signal of input is converted to differential current signal, is converted to reference difference current signal with the reference voltage signal of input, has the common mode value of identical Voltage to current transducer coefficient and identical output difference current;
The size of the current value of more described positive current signal and described positive reference current signal; The size of the current value of more described negative current signal and described positive reference current signal;
When the current value of positive reference current signal is less than the current value of positive current signal, or when the current value of positive reference current signal is less than the current value of negative current signal, export the first magnitude of voltage, described first magnitude of voltage represents that the differential voltage signal of input is the voltage of useful signal.
Pass through due to first in the embodiment of the present invention, the voltage signal of input can be converted to current signal by two voltage current adapters, and the current value of current signal exported and the voltage of positive signal of the differential voltage signal of input and the difference of the voltage of negative signal have linear relationship, thus by the differential voltage signal of input just, whether the voltage difference of negative signal is greater than the judgement of the reference voltage level of input, whether the current value being converted into the current signal of output is greater than the current value exporting reference current signal, only need more once in each comparer, thus under equal comparator circuit condition, improve the speed of the processing signals of comparer.
Accompanying drawing explanation
In order to be illustrated more clearly in the technical scheme in the embodiment of the present invention, below the accompanying drawing used required in describing embodiment is briefly described, apparently, accompanying drawing in the following describes is only some embodiments of the present invention, for those of ordinary skill in the art, under the prerequisite not paying creative work, other accompanying drawing can also be obtained according to these accompanying drawings.
Fig. 1 is a kind of high-speed transfer event detection circuit schematic diagram that the embodiment of the present invention provides;
Fig. 2 is the circuit diagram of a kind of high-speed transfer event detection circuit that the embodiment of the present invention provides;
Fig. 3 is the oscillogram at the corresponding check point place of a kind of high-speed transfer event detection circuit that the embodiment of the present invention provides;
Fig. 4 is the general flow chart that the embodiment of the present invention provides a kind of high-speed transmission event detection method.
Embodiment
The embodiment of the present invention provides a kind of high-speed transmission event detection method and circuit.Below be described in detail respectively.
Be illustrated in figure 1 a kind of high-speed transfer event detection circuit schematic diagram that the embodiment of the present invention provides, comprise: the first voltage current adapter 1, second voltage current adapter 2, first comparer 3, second comparer 4, with output circuit 5, wherein, the first voltage current adapter 1 is identical with the second voltage current adapter 2 structure.
Wherein, the first voltage current adapter 1, for the differential voltage signal of input is converted to differential current signal, wherein, described differential current signal comprises: positive current signal and negative current signal;
Wherein, as shown in Figure 1, the positive current signal that the first voltage current adapter 1 exports can be input to the inverting input of the first comparer 3, and the negative current signal that the first voltage current adapter 1 exports can be input to the inverting input of the second comparer 4.
Second voltage current adapter 2, for the reference voltage signal of input is converted to reference difference current signal, described reference difference current signal comprises: positive reference current signal and negative reference current signal;
Wherein, as shown in Figure 1, the positive reference current signal that the second voltage current adapter 2 exports, or negative reference current signal, be input to the in-phase input end of first and second comparer respectively.
First voltage current adapter and the second voltage current adapter have the common mode value of identical Voltage to current transducer coefficient and identical output difference current.
Also it should be noted that, first voltage current adapter, specifically according to the voltage difference of the positive/negative voltage signal of differential voltage signal and the differential current signal after changing, there is linear relationship, the differential voltage signal of input is converted to differential current signal, and, second voltage current adapter, can be specifically according to the voltage difference of reference voltage signal and the ground signalling of input with change after reference difference current signal there is linear relationship, the reference voltage signal of input is converted to reference difference current signal.If first and second voltage current adapter to voltage and current conversion adopt nonlinear relationship, be also can realize of the present invention.
First comparer 3, for the size of the current value of more described positive current signal and described positive reference current signal;
Second comparer 4, for the size of the current value of more described negative current signal and described positive reference current signal;
Output circuit 5, for when the current value of positive reference current signal is less than the current value of positive current signal, or when the current value of positive reference current signal is less than the current value of negative current signal, export output first magnitude of voltage, described first magnitude of voltage represents that the differential voltage signal of input is the voltage of useful signal.
It is to be appreciated that when the comparative result in the first comparer 3, second comparer 4 is other situation, exports in output circuit 5 and represent that the differential voltage signal of input is the voltage of noise.The differential voltage signal of the expression input exported in output circuit 5 is the voltage of useful signal, can be high voltage, thus control USB receiving equipment shielding noise, receive useful signal.
A kind of high-speed transfer event detection circuit that the embodiment of the present invention provides, due to first, the voltage signal of input can be converted to current signal by two voltage current adapters, and the current value of current signal (comprising: positive current signal and negative current signal) exported and the voltage of positive signal of differential voltage signal of input and the difference of the voltage of negative signal have linear relationship, thus by the differential voltage signal of input just, whether the voltage difference of negative signal is greater than the judgement of the reference voltage level of input, whether the current value being converted into the current signal (comprising: positive current signal and negative current signal) of output is greater than the current value exporting reference current signal, only need more once in each comparer, thus under equal comparator circuit condition, improve the speed of the processing signals of comparer.
Further, output circuit 5 is also for when the current value of positive reference current signal is not less than the current value of positive current signal, or when the current value of positive reference current signal is not less than the current value of negative current signal, export the second magnitude of voltage, described second magnitude of voltage represents that the differential voltage signal of described input is noise;
High-speed transfer event detection circuit shown in Fig. 1 also comprises: the input end of filtering circuit 6 is connected with output circuit 5 output terminal, during for being less than or equal to time period Vt for the time interval of adjacent two the first magnitudes of voltage when output, the second magnitude of voltage exported in this time interval is converted to the first magnitude of voltage to export, wherein, described time period Vt is the upset used time of effective differential signal.
Filtering circuit specifically may be used for when input differential voltage signal change to low from height time, step-down after the time lengthening time Td of output, when input voltage from low change to high time, output voltage be height; Wherein, time Td is greater than Tc flip-flop transition of differential voltage signal.
It will be appreciated that, the value that Td is set be a bit larger tham differential voltage signal flip-flop transition Tc reason be: the flip-flop transition ignoring differential voltage signal, when differential signal is detected as useful signal in the non-toggle time, then this differential signal is also identified valid data within flip-flop transition.Can describe in detail in subsequent embodiment.
Be illustrated in figure 2 the another kind of high-speed transfer event detection circuit that the embodiment of the present invention provides, the circuit that this circuit and Fig. 1 provide is similar, all comprises: the first voltage current adapter 1, second voltage current adapter 2, first comparer 3, second comparer 4, and output circuit 5; Also filtering circuit 6 can be comprised.The testing circuit that Fig. 2 provides is a kind of realizing circuit more specifically.
Wherein, first voltage current adapter 1 comprises: metal oxide semiconductor field effect transistor (MOS, Metal Oxide Semiconductor Field Effect Transistor) pipe M1, M2, M3, M4, M5, M12, M22, wherein, M1, M2, M3 are that P type MOSFET manages (abbreviation PMOS), and M4, M5, M12, M22 are N-type MOS field effect transistor (abbreviation NMOS tube).The source electrode of PMOS M1 is connected with power vd D, the drain electrode of PMOS M1 is connected with the source electrode of PMOS M2, M3 respectively, the drain electrode of PMOS M2, M3 respectively corresponding and NMOS tube M4, M5 leakage, grid is connected, NMOS tube M4 and M12 connects into current mirror, and NMOS tube M5 and M22 connects into current mirror.In differential voltage signal, positive voltage signal D+ and negative voltage signal D-inputs this first voltage current adapter from the grid of PMOS M2, M3 respectively, positive output electric current I dp is mirrored to the drain electrode of NMOS tube M12 through NMOS tube M4, and negative output current Idm is mirrored to the drain electrode of NMOS tube M22 through NMOS tube M5.PMOS M1 is input to by selecting suitable bias voltage biasl, make the first voltage current adapter can control to change the differential voltage signal of input, the differential output current that differential voltage signal D+, D-after being processed by the first voltage current adapter 1 are corresponding can represent with following formula (1), (2):
Idp＝Icv+gm*(Vdp-Vdm) (1)
Idm＝Icv+gm*(Vdm-Vdp) (2)
Wherein, gm is the mutual conductance of voltage current adapter, also can be called the Voltage to current transducer coefficient of voltage current adapter, is determined by the physical parameter size of PMOS M2, M3.Icv is that voltage current adapter exports the common mode value of difference current, namely PMOS M1 electric current 1/2nd.
Second voltage current adapter 2 comprises: PMOS M6, M7, M8, NMOS tube M9, M10, M11, M21, bias voltage is input to the grid of PMOS M6, the source electrode of PMOS M6 is connected with power supply, the drain electrode of PMOS M6 is connected with the source electrode of PMOS M7, M8 respectively, the drain electrode of PMOS M7, M8 respectively corresponding and NMOS tube M9, M10 leakage, grid is connected, the grounded-grid of PMOS M8, and the grid of PMOS M7 is for inputting described reference voltage signal; The current mirror of PMOS M10, M11, NMOS tube M21 composition, is mirrored to the drain electrode of NMOS tube M11, M21 respectively by the positive reference current signal flowing through NMOS tube M10.Then change the reference current signal of output as shown in the formula shown in (3) by the second voltage current adapter 2:
Iref＝Icv+gm*(Vref-0) (3)
Wherein, the voltage signal of the input end input of the second voltage current adapter is respectively reference voltage signal Vref and ground signalling.
First comparer 3 comprises: PMOS M13, M14, M15, M16, M17, M18, NMOS tube M19, M20, PMOS M13, M14, M15, M16, M17, the source electrode of M18 connects power supply, the leakage of PMOS M15, the drain electrode of grid and PMOS M13, the grid of PMOS M14, the grid of PMOS M18 is connected, as the in-phase input end of comparer, the leakage of PMOS M16, the drain electrode of grid and PMOS M14, the grid of PMOS M13, the grid of PMOS M17 is connected, as the inverting input of comparer, the leakage of NMOS tube M19, the drain electrode of grid and PMOS M17, the grid of NMOS tube M20 is connected, NMOS tube M19, the source ground of M20, the drain electrode of PMOS M18 is connected the output terminal as the first comparer with the drain electrode of NMOS tube M20.PMOS M13 and M14 forms positive feedback structure, for accelerating the first comparer 3 reversal rate.The drain electrode of PMOS M18 is connected the output terminal as the first comparer with the drain electrode of NMOS tube M20, is connected with the input end of output circuit.
Second comparer 4 comprises: PMOS M23, M24, M25, M26, M27, M28, and NMOS tube M29, M30.It should be noted that the second comparer 4 is identical with the circuit structure in the first comparer 3, and the MOS crystal field effects pipe of correspondence is measure-alike, illustrating can with reference to the explanation of the first comparer 3.The current signal of the input end input of the second comparer 4 is different from the input end input current signal of the first comparer 3, second comparer 4 input end input be the negative current signal of differential current signal, the first comparer 3 input end input be the positive current signal of differential current signal.
Output circuit 5 has can right and wrong gate circuit, export as low (when namely the current value of reference current signal is less than the current value of positive current signal) to the first comparer 3, export as low (when namely the current value of reference current signal is less than the current value of negative current signal) with the second comparer 4, carry out NAND operation, export as high voltage, this high-speed transfer event detection circuit is judged, and differential voltage signal is useful signal, otherwise be noise signal, thus control USB receiving equipment receive data.
Further, due to the upset of the differential voltage signal of the high-speed transfer event detection circuit of input, cause the following period of time in signal upset, the signal inputted during this period of time can be judged as noise by testing circuit.Specify in usb protocol, the upset duration of differential voltage signal must not more than 2 nanoseconds (ns).In order to avoid such erroneous judgement, this high-speed transfer event detection circuit can also comprise: filtering circuit 6.
Still with reference to Fig. 2, this filtering circuit 6 can comprise: three phase inverters I1, I2 and I3, PMOS M31, NMOS tube M32, electric capacity C1, and current source Iss.The input end of phase inverter I1 is connected with the output terminal of output circuit 5, the output terminal of phase inverter I1 is connected with the grid of PMOS M31 and NMOS tube 32 respectively, the source electrode of PMOS M31 is connected with power vd D, the drain electrode of PMOS M31 is connected with the drain electrode of NMOS tube M32, the source electrode of NMOS tube M32 through current source Iss to ground, one end of electric capacity C1 is connected with the drain electrode of NMOS tube M32, one end ground connection, the drain electrode of NMOS tube M32 is also connected with the input end of phase inverter I2, the output terminal of phase inverter I2 is connected with the input end of phase inverter I3, the output terminal of phase inverter I3 is the output terminal (SQ_OUT) of filtering circuit 6.When the input end (Z) of phase inverter I1 is input as high voltage, PMOS M31 conducting, electric current charges to electric capacity C1 through PMOS M31, and the conducting resistance of PMOS M31 is enough little, makes the voltage of the input end of I2 (CX) rise to height immediately.When input Z voltage from high to low time, NMOS tube M32 conducting, electric capacity C1 through NMOS tube M32 and current source Iss to discharge, discharge time, Td was determined by the capacitance of electric capacity C1 and the size of current of current source Iss, when the voltage drop at CX place is to the turn threshold Vt of phase inverter I2, I2 exports as high, the low-voltage of the output terminal SQ_OUT output of phase inverter I3.In order to ensure the upset of differential voltage signal during this period of time in, the Output rusults of SQ_OUT can not be affected, can discharge time of control capacitance C1, make in differential voltage signal upset during this period of time, the voltage of CX is still greater than the turn threshold Vt of phase inverter I2.
Wherein, the charge-discharge characteristic of electric capacity is represented by following formula (4):
C1*(VDD-Vt)＝Iss*Td (4)
Make Td discharge time of electric capacity be greater than Tc flip-flop transition (Td > Tc) of differential voltage signal, i.e. [C1* (VDD-Vt)/Iss] > Tc, then circuit has required filtering feature.
In order to more know the circuit that understanding is illustrated in fig. 2, with reference to the oscillogram shown in figure 3.Fig. 3 (A) is depicted as the oscillogram of the voltage signal of input high-speed transfer event detection circuit, and the magnitude of voltage of the reference voltage signal of input is less than the absolute value of the forward voltage of differential voltage signal and the voltage difference of negative voltage (i.e. Vref < | Vdp-Vdm|).
Fig. 3 (B) is the differential current signal oscillogram that the first voltage current adapter 1 exports, and the reference current signal oscillogram that the second voltage current adapter 2 exports.Is the output waveform figure of first and second comparer as shown in 3 (C), if | Vdp-Vdm| > Vref, then according to the derivation of formula (1) to (3), known Idp > Iref, then the first comparator output terminal (CP_DP) exports as low-voltage, if Idm > is Iref, then the second comparator output terminal (CP_DM) exports as low-voltage.
Fig. 3 (D) is the oscillogram of output circuit 5 output terminal (Z) output voltage.In output circuit 5, NAND operation is done to the signal of input, can the waveform of easy understand Fig. 3 (D) from Fig. 3 (C).The oscillogram of input end (CX) input voltage that Fig. 3 (E) is I2, when the input end (Z) of phase inverter I1 is input as high voltage, M31 conducting, electric current charges to C1 through M31, the conducting resistance of M31 is enough little, makes the voltage of the input end of I2 (CX) rise to height immediately.When the voltage inputting Z from high to low time, M32 conducting, discharge time, Td can control within the Tc time, and voltage does not also drop to the turn threshold Vt lower than phase inverter I2, thus can filter the impact of differential voltage signal upset on testing circuit.As output terminal (SQ_OUT) output waveform figure that Fig. 3 (F) is testing circuit, voltage is the differential voltage signal that high expression detects is useful signal, and voltage is that low expression detects as noise.
Be illustrated in figure 4 a kind of high-speed transmission event detection method that the embodiment of the present invention provides, the method comprises:
Step 401: the differential voltage signal of input is converted to differential current signal, wherein, described differential current signal comprises: positive current signal and negative current signal;
Step 402: the reference voltage signal of input is converted to reference difference current signal, described reference difference current signal comprises: positive reference current signal and negative reference current signal; Wherein, the differential voltage signal of input is converted to differential current signal, is converted to reference difference current signal with the reference voltage signal of input, has the common mode value of identical Voltage to current transducer coefficient and identical output difference current;
Step 403: the size of the current value of more described positive current signal and described positive reference current signal; The size of the current value of more described negative current signal and described positive reference current signal;
Step 404: when the current value of positive reference current signal is less than the current value of positive current signal, or when the current value of positive reference current signal is less than the current value of negative current signal, export the first magnitude of voltage, the first magnitude of voltage represents that the differential voltage signal of input is the voltage of useful signal.
Wherein, when other situation of comparative result formula in step 403, the method can also comprise:
Step 405: when the current value of positive reference current signal is not less than the current value of positive current signal, or when the current value of positive reference current signal is not less than the current value of negative current signal, export the second magnitude of voltage, the second magnitude of voltage represents that the differential voltage signal of described input is noise.
A kind of high-speed transmission event detection method that the embodiment of the present invention provides, the voltage signal of input is converted to current signal, and the current value of current signal (comprising: positive current signal and negative current signal) exported and the voltage of positive signal of differential voltage signal of input and the difference of the voltage of negative signal have linear relationship, thus by the differential voltage signal of input just, whether the voltage difference of negative signal is greater than the judgement of the reference voltage level of input, whether the current value being converted into the current signal (comprising: positive current signal and negative current signal) of output is greater than the current value exporting reference current signal, only need more once in each comparer, thus under equal comparator circuit condition, improve the speed of the processing signals of comparer.
Further, the method can also comprise:
Step 406: when the time interval of adjacent two the first magnitudes of voltage exported is less than or equal to time period Vt, the second magnitude of voltage exported in this time interval is converted to the first magnitude of voltage and exports, wherein, described time period Vt is the upset used time of effective differential signal.
The detailed description of a kind of high-speed transmission event detection method that Fig. 4 is provided also can referring to figs. 1 in Fig. 3 about the explanation in a kind of high-speed transfer event detection circuit, do not repeat herein.
Being described in detail the embodiment of the present invention above, applying embodiment herein to invention has been elaboration, the explanation of above embodiment just understands method and apparatus of the present invention for helping; Meanwhile, for one of ordinary skill in the art, according to thought of the present invention, all will change in specific embodiments and applications, in sum, this description should not be construed as limitation of the present invention.
Claims (10)
1. a high-speed transfer event detection circuit, is characterized in that, comprising:
First voltage current adapter, for the differential voltage signal of input is converted to differential current signal, wherein, described differential current signal comprises: positive current signal and negative current signal;
Second voltage current adapter, for the reference voltage signal of input is converted to reference difference current signal, described reference difference current signal comprises: positive reference current signal and negative reference current signal; Wherein, the first voltage current adapter and the second voltage current adapter have the common mode value of identical Voltage to current transducer coefficient and identical output difference current;
First comparer, for the size of the current value of more described positive current signal and described positive reference current signal;
Second comparer, for the size of the current value of more described negative current signal and described positive reference current signal;
Output circuit, for when the current value of positive reference current signal is less than the current value of positive current signal, or when the current value of positive reference current signal is less than the current value of negative current signal, export the first magnitude of voltage, described first magnitude of voltage represents that the differential voltage signal of described input is useful signal.
2. high-speed transfer event detection circuit according to claim 1, it is characterized in that, described output circuit is also for when the current value of positive reference current signal is not less than the current value of positive current signal, or when the current value of positive reference current signal is not less than the current value of negative current signal, export the second magnitude of voltage, described second magnitude of voltage represents that the differential voltage signal of described input is noise;
Described high-speed transfer event detection circuit also comprises:
Filtering circuit, for when the time interval of adjacent two the first magnitudes of voltage exported is less than or equal to time period Vt, the second magnitude of voltage exported in this time interval is converted to the first magnitude of voltage to export, wherein, described time period Vt is the upset used time of effective differential signal.
3. high-speed transfer event detection circuit according to claim 1, it is characterized in that, described first voltage current adapter specifically comprises: PMOS M1, M2, M3, NMOS tube M4, M5, M12, M22, bias voltage is input to the grid of PMOS M1, the source electrode of PMOS M1 is connected with power supply, the drain electrode of PMOS M1 respectively with PMOS M2, the source electrode of M3 connects, the drain electrode of PMOS M2 is connected with the drain electrode of NMOS tube M4, the drain electrode of PMOS M3 is connected with the drain electrode of NMOS tube M5, PMOS M2, the grid of M3 is for inputting described differential voltage signal, NMOS tube M4, M12 connects into current mirror, NMOS tube M5, M22 connects into current mirror, NMOS tube M12, M4, M5, the source electrode of M22 all holds VSS to be connected with ground.
4. high-speed transfer event detection circuit according to claim 1, it is characterized in that, described second voltage current adapter specifically comprises: PMOS M6, M7, M8, NMOS tube M9, M10, M11, M21, bias voltage is input to the grid of PMOS M6, the source electrode of PMOS M6 is connected with power supply, the drain electrode of PMOS M6 respectively with PMOS M7, the source electrode of M8 connects, the drain electrode of PMOS M7 is connected with the drain electrode of NMOS tube M9, the drain electrode of PMOS M8 is connected with the drain electrode of NMOS tube M10, the grounded-grid of PMOS M8, the grid of PMOS M7 is for inputting described reference voltage signal, the current mirror of NMOS tube M10, M11, NMOS tube M21 composition, is mirrored to the drain electrode of NMOS tube M11, M21 respectively by the positive reference current signal flowing through NMOS tube M10, NMOS tube M9, M10, M11 all hold VSS to be connected with ground with the source electrode of M21.
5. high-speed transfer event detection circuit according to claim 1, it is characterized in that, described first comparer specifically comprises: PMOS M13, M14, M15, M16, M17, M18, NMOS tube M19, M20, PMOS M13, M14, M15, M16, M17, the source electrode of M18 connects power supply, the leakage of PMOS M15, the drain electrode of grid and PMOS M13, the grid of PMOS M14, the grid of PMOS M18 is connected, as the in-phase input end of comparer, the leakage of PMOS M16, the drain electrode of grid and PMOS M14, the grid of PMOS M13, the grid of PMOS M17 is connected, as the inverting input of comparer, the leakage of NMOS tube M19, the drain electrode of grid and PMOS M17, the grid of NMOS tube M20 is connected, NMOS tube M19, the source ground of M20, the drain electrode of PMOS M18 is connected the output terminal as the first comparer with the drain electrode of NMOS tube M20.
6. high-speed transfer event detection circuit according to claim 5, is characterized in that, described second comparer is identical with the structure of described first comparer.
7. high-speed transfer event detection circuit according to claim 1, is characterized in that, described output circuit specifically comprises: NAND gate circuit.
8. high-speed transfer event detection circuit according to claim 2, is characterized in that, described filtering circuit specifically comprises: three phase inverter I1,12 and 13, PMOS M31, NMOS tube M32, electric capacity C1 and current source, wherein, the input end of phase inverter 11 is connected with the output terminal of described output circuit, the output terminal of phase inverter 11 is connected with the grid of PMOS M31 and NMOS tube M32 respectively, the source electrode of PMOS M31 is connected with power supply, the drain electrode of PMOS M31 is connected with the drain electrode of NMOS tube M32, the source electrode of NMOS tube M32 through current source to ground, one end of electric capacity C1 is connected with the drain electrode of NMOS tube M32, one end ground connection, the drain electrode of NMOS tube M32 is also connected with the input end of phase inverter 12, the output terminal of phase inverter 12 is connected with the input end of phase inverter I3, the output terminal of phase inverter I3 is the output terminal of described filtering circuit.
9. a high-speed transmission event detection method, is characterized in that, comprising:
The differential voltage signal of input is converted to differential current signal, and wherein, described differential current signal comprises: positive current signal and negative current signal;
The reference voltage signal of input is converted to reference difference current signal, and described reference difference current signal comprises: positive reference current signal and negative reference current signal; Wherein, the differential voltage signal of input is converted to differential current signal, is converted to reference difference current signal with the reference voltage signal of input, has the common mode value of identical Voltage to current transducer coefficient and identical output difference current;
The size of the current value of more described positive current signal and described positive reference current signal; The size of the current value of more described negative current signal and described positive reference current signal;
When the current value of positive reference current signal is less than the current value of positive current signal, or when the current value of positive reference current signal is less than the current value of negative current signal, export the first magnitude of voltage, described first magnitude of voltage represents that the differential voltage signal of input is the voltage of useful signal.
10. detection method according to claim 9, is characterized in that, described method also comprises:
When the current value of positive reference current signal is not less than the current value of positive current signal, or when the current value of positive reference current signal is not less than the current value of negative current signal, export the second magnitude of voltage, described second magnitude of voltage represents that the differential voltage signal of described input is noise;
When the time interval of adjacent two the first magnitudes of voltage exported is less than or equal to time period Vt, the second magnitude of voltage exported in this time interval is converted to the first magnitude of voltage and exports, wherein, described time period Vt is the upset used time of effective differential signal.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201010268513.2A CN102384999B (en) | 2010-08-30 | 2010-08-30 | A kind of high-speed transmission event detection method and circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201010268513.2A CN102384999B (en) | 2010-08-30 | 2010-08-30 | A kind of high-speed transmission event detection method and circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN102384999A CN102384999A (en) | 2012-03-21 |
| CN102384999B true CN102384999B (en) | 2015-08-19 |
Family
ID=45824621
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201010268513.2A Expired - Fee Related CN102384999B (en) | 2010-08-30 | 2010-08-30 | A kind of high-speed transmission event detection method and circuit |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN102384999B (en) |
Families Citing this family (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104280189B (en) * | 2014-08-19 | 2017-08-29 | 深圳市理邦精密仪器股份有限公司 | A kind of pressure sensor failure hardware detection method and apparatus |
| CN104749424A (en) * | 2015-03-05 | 2015-07-01 | 青岛鼎信通讯股份有限公司 | Voltage and current vector relation based on residual current detection method |
| CN105591634B (en) * | 2015-12-11 | 2018-03-30 | 中国航空工业集团公司西安航空计算技术研究所 | A kind of high speed signal detection method and circuit |
| CN111239476B (en) * | 2018-11-29 | 2022-11-22 | 瑞昱半导体股份有限公司 | Signal detector and signal detection method |
| CN113014198B (en) * | 2021-03-31 | 2022-12-13 | 华为数字能源技术有限公司 | Photovoltaic system |
| CN116488623B (en) * | 2023-06-25 | 2023-10-20 | 广芯微电子(苏州)有限公司 | Current comparator |
Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1069152A (en) * | 1991-07-26 | 1993-02-17 | 三星电子株式会社 | Slew rate speed-up circuit |
| GB2318419A (en) * | 1996-10-18 | 1998-04-22 | Nec Corp | Window comparator circuit |
| CN1334987A (en) * | 1998-12-18 | 2002-02-06 | 艾利森电话股份有限公司 | Level shift circuit |
| CN1405761A (en) * | 2002-10-17 | 2003-03-26 | 威盛电子股份有限公司 | Fixed delay-width delay comparing apparatus |
| CN1777026A (en) * | 2004-11-17 | 2006-05-24 | 恩益禧电子股份有限公司 | Voltage comparator circuit with symmetric circuit topology |
| CN1910818A (en) * | 2004-01-13 | 2007-02-07 | 皇家飞利浦电子股份有限公司 | High speed comparator |
| CN101192805A (en) * | 2006-11-30 | 2008-06-04 | 松下电器产业株式会社 | PWM drive apparatus and method for correcting output offset thereof |
| CN101262213A (en) * | 2007-03-07 | 2008-09-10 | 恩益禧电子股份有限公司 | Input signal detecting circuit |
-
2010
- 2010-08-30 CN CN201010268513.2A patent/CN102384999B/en not_active Expired - Fee Related
Patent Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1069152A (en) * | 1991-07-26 | 1993-02-17 | 三星电子株式会社 | Slew rate speed-up circuit |
| GB2318419A (en) * | 1996-10-18 | 1998-04-22 | Nec Corp | Window comparator circuit |
| CN1334987A (en) * | 1998-12-18 | 2002-02-06 | 艾利森电话股份有限公司 | Level shift circuit |
| CN1405761A (en) * | 2002-10-17 | 2003-03-26 | 威盛电子股份有限公司 | Fixed delay-width delay comparing apparatus |
| CN1910818A (en) * | 2004-01-13 | 2007-02-07 | 皇家飞利浦电子股份有限公司 | High speed comparator |
| CN1777026A (en) * | 2004-11-17 | 2006-05-24 | 恩益禧电子股份有限公司 | Voltage comparator circuit with symmetric circuit topology |
| CN101192805A (en) * | 2006-11-30 | 2008-06-04 | 松下电器产业株式会社 | PWM drive apparatus and method for correcting output offset thereof |
| CN101262213A (en) * | 2007-03-07 | 2008-09-10 | 恩益禧电子股份有限公司 | Input signal detecting circuit |
Non-Patent Citations (1)
| Title |
|---|
| 基于USB总线的高速数据采集系统设计;张翼颉;《中国优秀硕士学位论文全文数据库信息科技辑》;20081115(第11期);I140-618 * |
Also Published As
| Publication number | Publication date |
|---|---|
| CN102384999A (en) | 2012-03-21 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN102384999B (en) | A kind of high-speed transmission event detection method and circuit | |
| CN102638317B (en) | Signal loss detection circuit and method and amplifier | |
| EP3734414B1 (en) | Signal detector | |
| TWI425772B (en) | Envelope detetor and associated method | |
| CN103036538A (en) | Circuit and method for correcting offset voltage of comparator | |
| CN204595077U (en) | A kind of zero cross detection circuit with phase compensation | |
| CN104868880B (en) | Clock generating circuit | |
| CN102629856B (en) | Low-voltage differential signal receiver | |
| CN114636854A (en) | Detection circuit and detection method for differential signal and electronic equipment | |
| CN107483044A (en) | A kind of baseline drift voltage correction circuit for network interface chip | |
| CN103604975A (en) | An anti-interference low-voltage detection circuit | |
| CN103762963A (en) | Comparison circuit high in speed | |
| CN110958031B (en) | RS485 receiver circuit, integrated circuit and transceiver | |
| US6060890A (en) | Apparatus and method for measuring the length of a transmission cable | |
| CN102346720B (en) | Transmission system and method of serial data | |
| CN103941144A (en) | Reference voltage source leakage detection circuit | |
| CN202602615U (en) | Control circuit of rail-to-rail enable signals and electric level conversion circuit | |
| CN204206141U (en) | A kind of MLVDS driver with constant differential output voltage | |
| CN108449077A (en) | High-speed internal hysteresis type comparator | |
| CN110912842B (en) | Envelope detection circuit | |
| CN115348129A (en) | CAN transceiver receiving circuit | |
| CN101610140A (en) | Signal amplitude detection circuit and method | |
| CN113395090B (en) | BMC signal receiving circuit for USB PD communication and implementation method thereof | |
| CN202903860U (en) | Differential signal detection apparatus | |
| CN204272060U (en) | The bilateral bus interface threshold comparator circuit trimmed |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CF01 | Termination of patent right due to non-payment of annual fee | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20150819 Termination date: 20160830 |