CN102347761B - Dynamic delay, and phase-frequency detector (PFD) and phase lock loop adopting same - Google Patents
Dynamic delay, and phase-frequency detector (PFD) and phase lock loop adopting same Download PDFInfo
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- CN102347761B CN102347761B CN201010240678.9A CN201010240678A CN102347761B CN 102347761 B CN102347761 B CN 102347761B CN 201010240678 A CN201010240678 A CN 201010240678A CN 102347761 B CN102347761 B CN 102347761B
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Abstract
The invention discloses a dynamic delay, and a phase-frequency detector (PFD) and a phase lock loop adopting the dynamic delay. The dynamic delay comprises a phase inverter and a plurality of current branches, wherein the grounding end of the phase inverter is respectively connected with one ends of the current branches, one ends of the current branches which are not connected with the phase inverter are grounded, the current branches comprise main current branches and auxiliary current branches, an on-off controller for controlling the on-off state of the circuit is arranged in the auxiliary current branches, the control end of the on-off controller is connected with the output end of the phase reverser, and the output pulse of the phase reverser is used for controlling the state of the on-off controller. The dead region elimination is realized through the practical dynamic control on the PFD reset pulse, the influence caused by process deviation is overcome, the complete consistency of the delay path is realized through the symmetrical NAND gate, and the state after the system lock can be continuously maintained through the adoption of a latch.
Description
Technical field
The present invention relates to technical field of integrated circuits, relate in particular to a kind of dynamic deferred device and adopt phase frequency detector and the phase-locked loop of this delayer.
Background technology
Phase-locked loop (Phase Locked Loop, PLL) be a kind of phase place negative feed back control system, can make the frequency of controlled oscillator and phase place and input signal keep determining relation, and can suppress noise in input signal and the phase noise of voltage controlled oscillator.As shown in Figure 1, at present more conventional PLL is conventionally by phase frequency detector (Phase Frequency Detector, PFD), charge pump (Charge Pump, CP), loop filter (Loop Filter, LPF), voltage controlled oscillator (Voltage Control Oscillator, VCO) and the system that forms of a plurality of modules such as frequency divider (FrequencyDivider, FD).
The standard of weighing PLL performance is the size of the phase noise of frequency domain, and the phase noise of pll system almost has contribution in each module of its composition, affect larger low frequency phase noise and be mainly derived from the relatively low analog module of operating frequency, i.e. PFD, CP and LPF etc.Wherein, the problem of PFD module maximum is exactly " dead band " phenomenon; LPF module is because the restriction of decay factor cannot make VCO obtain level and smooth control voltage.
Summary of the invention
The technical problem to be solved in the present invention is to provide a kind of dynamic deferred device and adopts phase frequency detector and the phase-locked loop of this delayer, realizes the generation of avoiding " dead band " phenomenon in phase-locked loop.
For solving the problems of the technologies described above, a kind of dynamic deferred device of the present invention, comprise: inverter and many current branch, the earth terminal of inverter is connected with one end of many current branch respectively, one end ground connection not being connected with inverter of many current branch, current branch comprises primary current leg and auxiliary current branch, in auxiliary current branch, be provided with the on-off controller of control circuit break-make, the control end of this on-off controller is connected with the output of inverter, is controlled the state of on-off controller by the output pulse of inverter.
Further, current branch is the branch road that current source is set;
The electric current of the current source arranging in primary current leg is: x
*inverter for removing the operating current in dead band; The electric current of the current source arranging in auxiliary current branch is: y
*inverter for removing the operating current in dead band; Wherein, the value that x and y is set makes the electric current sum of the auxiliary current branch of main circuit branch road and conducting, and to be inverter remove dead band operating current, 0 < x < 1 and 0 < y < 1.
Further, the ON time that configures the on-off controller in auxiliary current branch is (1-x-m*y)
*go dead band time of delay, wherein, m is the branch road number of on-off controller place current branch, m>=0.
Further, a kind of phase frequency detector, comprising: dynamic deferred device, arithmetic logic unit and at least two triggers, and the output of variable delay device is connected respectively the reset terminal of trigger and the output of arithmetic logic unit with input, wherein:
Dynamic deferred device, comprise: inverter and many current branch, the earth terminal of inverter is connected with one end of many current branch respectively, one end ground connection not being connected with inverter of many current branch, current branch comprises primary current leg and auxiliary current branch, in auxiliary current branch, be provided with the on-off controller of control circuit break-make, the control end of this on-off controller is connected with the output of inverter, is controlled the state of on-off controller by the output pulse of inverter.
Further, on the output of trigger, connect latch and transmission gate, respectively output signal;
Latch comprises the inverter of cascade, and the inverter link of cascade is as the output of latch, and the not connected one end of the inverter of cascade is connected to the output of trigger.
Further, arithmetic logic unit comprises a plurality of NAND gate, and the input of a plurality of NAND gate is connected respectively to the output of trigger, and the output of a plurality of NAND gate interconnects, and is connected to the input of the inverter in dynamic deferred device.
Further, the current branch in dynamic deferred device is the branch road that current source is set;
The electric current of the current source arranging in primary current leg is: x
*inverter for removing the operating current in dead band; The electric current of the current source arranging in auxiliary current branch is: y
*inverter for removing the operating current in dead band; Wherein, the value that x and y is set makes the electric current sum of the auxiliary current branch of main circuit branch road and conducting, and to be inverter remove dead band operating current, 0 < x < 1 and 0 < y < 1.
Further, a kind of phase-locked loop, comprising: connected phase frequency detector, charge pump and loop filter successively, and phase frequency detector comprises: dynamic deferred device, wherein:
Dynamic deferred device, comprise: inverter and many current branch, the earth terminal of inverter is connected with one end of many current branch respectively, one end ground connection not being connected with inverter of many current branch, current branch comprises primary current leg and auxiliary current branch, in auxiliary current branch, be provided with the on-off controller of control circuit break-make, the control end of this on-off controller is connected with the output of inverter, is controlled the state of on-off controller by the output pulse of inverter.
Further, loop filter comprises: passive filter and resonant circuit, resonant circuit is in parallel with passive filter.
Further, phase-locked loop also comprises signal attenuation resistance, and this signal attenuation resistance is connected between passive filter and the input of loop filter.
In sum, the present invention, by the dynamic control to PFD reset pulse reality, realizes and removes dead band, overcomes the impact of process deviation, and it is in full accord that symmetric form NAND gate realizes delay path, and the use of latch can continue hold mode after system lock; Optimal design to original low pass filter, can realize the level and smooth control to the control voltage of follow-up VCO circuit, increases by one group of resonant circuit and can realize the significantly decay spuious to system, and systematic function is effectively provided.The present invention has improved the performance of whole pll system effectively, has higher practical value, and power consumption is lower, and circuit structure is relatively simple.
Accompanying drawing explanation
Fig. 1 is the schematic diagram of phase-locked loop systems in prior art;
Fig. 2 is the schematic diagram of PFD of the prior art;
Fig. 3 is the schematic diagram of charge pump CP in prior art;
Fig. 4 is the schematic diagram of the PFD of present embodiment;
Fig. 5 is the schematic diagram of the dynamic deferred device that adopts in the PFD of present embodiment;
Fig. 6 is the schematic diagram of the inverter that adopts in dynamic deferred device in present embodiment;
Fig. 7 is the break-make schematic diagram of dynamic deferred each current branch of device in present embodiment;
Fig. 8 is the schematic diagram of dynamic deferred device output pulse width in present embodiment;
Fig. 9 is the schematic diagram of the LPF of present embodiment;
Figure 10 is the schematic diagram of the resonant circuit amplitude-frequency response that arranges in the LPF of present embodiment;
Figure 11 is the schematic diagram of amplitude-frequency response of the LPF of present embodiment.
Embodiment
In present embodiment, in the PFD of PLL, adopt dynamic deferred device, can overcome according to default time of delay the PFD dead band phenomenon causing due to technique, temperature etc.; And in original passive LPF, integrate a resonant circuit, can for the frequency of input clock, greatly suppress the spurious signal that input is brought into, optimization system performance.
Below in conjunction with accompanying drawing, embodiment is elaborated.
Fig. 2 is the structure of existing PFD, comprising: two triggers, a delayer, one and door, an inverter and a transmission gate, the data input pin of the first trigger (clk) connects reference signal f
ref, the clk of the second trigger connects feedback signal f
bthe output of the first trigger (Q) end connect respectively inverter and with an input of door, the Q end of the second trigger connect respectively transmission gate input and with another input of door, with the input of the output connection delay device of door, the output of extension device connects respectively reset (rst) end of the first trigger and the second trigger.
The input of PFD is by reference signal f
reffeedback signal f with phase-locked loop systems
bform, PFD compares respectively the phase place of these two signals and frequency, according to phase difference, exports corresponding pulse duration." dead band " phenomenon of PFD can worsen lock function and the noiseproof feature of PLL, and " dead band " is mainly by up and d
nexcessive and charge pump (CP) switch of the load capacitance of two paths of signals is (as the S in Fig. 3
upwith S
dn) opening speed spend slow causing so that there is PFD and cannot react real work situation in the situation that the phase difference of two-way input signal is very little.
In addition, up and d
ntwo paths of signals is through inconsistent with the time of delay to the reset signal of trigger of door generation, also can cause nonlinear operation, the method solving is, in the reset path of trigger, delayer is set, and produces an intrinsic inhibit signal, to eliminate the non-linear phenomena of PFD.
PFD in Fig. 2 is a kind of Single-end output structure, because the conducting of the PMOS of rear class charge pump (positive channel metal-oxide-semiconductor field) switch is Low level effective, therefore, the output at PFD adopts inverter (inverter) to form up as the input signal of charge pump; Accordingly, d
nend, in order to mate with the time of delay of up signal arrival CP switch, adopts transmission gate (transmission) as the delay unit of this road signal.
Fig. 4 is the PFD of present embodiment, adopts dynamic deferred device to replace the delayer in Fig. 2, and this dynamic deferred device can overcome the sudden change of delay, improves due to up and d
nthe circuit nonlinear operation situation that causes of delay difference.And, adopt two symmetrical NAND gate (NAND) staggered form to connect, substitute original one and door (AND), the path of having avoided arriving due to two input signals that restriction single and self circuit structure of door occurs output is different, because the difference in path delay can form the non-linear of circuit output characteristic.
In addition, for the output signal of two triggers (DFF) in Fig. 2, improve up and d
non two paths of signals, adopt respectively a latch (4T_latch, in Fig. 4 in the dotted line ring shown in) mode in parallel with transmission gate to realize the input of subordinate's circuit.Wherein, latch adopts the form of two inverter cascades, form two ends parts, input is connected with the output of DFF, output is as the output of PFD, add latch can guarantee on the one hand can continue lock-out state after PLL locking and saltus step no longer occurs, after PLL locking, can maintain the state of locking; On the other hand original Single-end output has been become difference output (up with
, dn with
), for the more accurate circuit of design provides simple and practical scheme.
Fig. 5 is the dynamic deferred device (variable delay) that present embodiment adopts, dynamic deferred device comprises inverter (invert), the input of inverter is connected with the output F of NAND gate (NAND), the output of inverter is connected with the reset terminal of trigger, the earth terminal S end of inverter connects current branch, current branch comprises primary current leg and auxiliary current branch, in auxiliary current branch, be provided with on-off controller, the control end of on-off controller is connected with the output of inverter, by inverter output signal, controlled the on off operating mode of auxiliary current branch, main, the equal ground connection in one end not being connected with S end of auxiliary current branch.
As shown in Figure 6, exemplified the inverter adopting in a kind of dynamic deferred device of present embodiment, comprise two NMOS pipes (negative channel metal-oxide-semiconductor field), the grid of these two NMOS pipes is connected respectively with drain electrode, the source S end of one of them NMOS pipe M2 is as the earth terminal S end of inverter, and the source electrode of another NMOS pipe M1 is as the power end of inverter.
Dynamic deferred device need to produce a time of delay, therefore, adopt one can control time constant inverter realize, specific works process is:
The time constant of inverter is:
Wherein, V
outfor the output voltage amplitude of inverter, C
lfor load capacitance, I
outfor the operating current of inverter, from formula (1), can find out, in output voltage amplitude and load capacitance, constant in the situation that, by changing operating current, can realize the modification to the time constant of inverter.
In the situation that pll system can lock, (go dead band time of delay) td carries out emulation to removing the time of delay that PFD dead band needs, and as the time of delay of dynamic deferred device, by formula (1), calculates corresponding inverter operating current I
out1(be called inverter for removing the operating current in dead band), each current source current of setting dynamic deferred device in Fig. 5 is:
I
main＝x*I
out1 (2)
I
0＝I
1＝...I
k＝...I
n＝y*I
out1 (3)
Wherein, n > 1, y=(1-x)/(k+1); K=n/2 when n is even number; Otherwise, k=(n+1)/2,0 < x < 1 and 0 < y < 1
In addition, I
mainaccount for I
out1major part, x is set conventionally and is greater than 0.5, due to I
mainbranch road is path always, x is set and is greater than 0.5 and can guarantees that circuit can work in all cases.
On-off controller in auxiliary current branch can adopt transistor, sets each on-off controller S in Fig. 5 by the suitable value to transistor size
0, S
1, S
2... S
k... S
noN time be respectively: T
s0=x*td, T
s1=(1-x-y) * td......T
sk=(1-x-k*y) * td......T
sn=(1-x-n*y) * td; After pll system locking, the width td of the reset pulse that inverter produces can be by switch S
0, S
1... S
kconducting, and S
k+1... S
ncannot conducting and remain open.
In the manner described above configuration after, the current lead-through situation of each current source of dynamic deferred device as shown in Figure 7, at output voltage pulse V
out_tdeffect under, due to restriction ，Ge road current source actual time S that has electric current within the time of td of each switch conduction time
i_Ii(i=0 ... .k) as shown in the figure.Therefore within the burst length of td, the total output current of negater circuit is shown in (b) in Fig. 8, by emulation, show, this switching time the stability that has guaranteed delay time td is set, and then eliminate the dead band phenomenon that PFD circuit exists.
The more important thing is, while causing change the time of delay of dynamic deferred device due to some extraneous factor, this dynamic deferred device can dynamically keep the stability of td.If reseting pulse width diminishes (being less than td), the short of width of now pulse is to meet a part of switch (S
n... S
k, S
k-1, S
k-2...) triggered time of needing, these switches all cannot conducting, so total current diminishes, as shown in (a) in Fig. 8.Now known according to formula (1), the operating current of inverter diminishes and can make its time constant become large, so circuit will become large to readjusting the time of delay of inverter (reseting pulse width).When becomeing greater to, the time constant of dynamic deferred device is greater than after td, now pulse duration is enough to make all conductings of most of switch, total output current becomes large and now according to the known inverter time constant of formula (1), diminishes as shown in (c) in Fig. 8, and reset pulse is adjusted again.Such adjustment process will be stabilized in td the time of delay that be continued until inverter.From the above analysis, this dynamic deferred device can effectively suppress the change of resetting time, thereby overcomes PFD " dead band ".
Fig. 9 be in present embodiment, be applied in pll system can fully filtering spurious signal filter, comprising: passive filter and resonant circuit.Passive filter is comprised of resistance capacitance, and it is input as the output signal CP of charge pump in PLL
out, pass through resistance R
0be connected to D point, resistance R
1with capacitor C
1series connection after and capacitor C
2be parallel-connected to D point (the two parallel branch other ends are ground connection all), resistance R
3be connected in D point and output point V
cbetween, at V
cplace connects a ground capacity C
3; Resonant circuit is parallel to capacitor C
3afterwards, by inductance L
4and capacitor C
4be composed in series capacitor C
4other end ground connection.
Passive filter can adopt three rank passive filters or second order passive filter etc., and in Fig. 7, three elements shown in circular fine dotted line frame form traditional second order passive filter; Element in Fig. 9 in rectangle frame forms three traditional rank passive filters.
Figure 10 is the amplitude-frequency response of resonant circuit, can find out that resonant circuit only has stronger attenuation to the signal of single frequency, and do not change the signal amplitude of other frequencies, but, common low pass filter is that all frequency signals more than passband are decayed to it, and present embodiment by the amplitude-frequency response of the filter obtaining after passive low pass filter and resonant circuit cascade as shown in figure 11.
Filter effect shown in Figure 11 has met the needs that pll system " should be controlled to VCO the low-pass filtering of voltage; can greatly suppress again the noise that input reference frequency is introduced " just, not only can also there is larger attenuation for certain frequency to High frequency filter, and pass through L
4and C
4reasonable value resonant circuit can be set be operated on the frequency needing.
In addition, R
0a very little resistance, by so less resistance of connecting before the present low pass filter of simulation hair, can effectively reduce the amplitude that CP in PLL discharges and recharges the current impulse of formation, thereby form relatively mild control voltage, can not cause VCO to occur the phenomenons such as overload.
Side circuit described in foregoing invention is a limited part in application, other embodiments also include but not limited to constituting with a certain functional block described in upper module, certain several functional block or repertoire piece, and the invention is not restricted to these examples, claimed range by right illustrates, within being included in all changes within the content of claim equalization and the scope of claim or variation the interest field that the present invention requires.
Claims (8)
1. a dynamic deferred device, comprise: inverter and many current branch, the earth terminal of described inverter is connected with one end of described many current branch respectively, one end ground connection not being connected with described inverter of described many current branch, described many current branch comprise primary current leg and auxiliary current branch, in described auxiliary current branch, be provided with the on-off controller of control circuit break-make, the control end of this on-off controller is connected with the output of described inverter, is controlled the state of described on-off controller by the output pulse of described inverter;
Wherein, described current branch is the branch road that current source is set;
The electric current of the current source arranging in described primary current leg is: x* inverter for removing the operating current in dead band; The electric current of the current source arranging in described auxiliary current branch is: y* inverter for removing the operating current in dead band; Wherein, the value that x and y be set makes the electric current sum of the auxiliary current branch of described primary current leg and conducting, and to be described inverter remove dead band operating current, 0 < x < 1 and 0 < y < 1.
2. dynamic deferred device as claimed in claim 1, is characterized in that:
The ON time that configures the on-off controller in described auxiliary current branch is gone dead band time of delay for (1-x-m*y) *, and wherein, m is the branch road number of described on-off controller place current branch, m >=0.
3. a phase frequency detector, comprising: dynamic deferred device, arithmetic logic unit and at least two triggers, and the output of described dynamic deferred device is connected respectively the reset terminal of described trigger and the output of described arithmetic logic unit with input, wherein:
Described dynamic deferred device comprises: inverter and many current branch, the earth terminal of described inverter is connected with one end of described many current branch respectively, one end ground connection not being connected with described inverter of described many current branch, described many current branch comprise primary current leg and auxiliary current branch, in described auxiliary current branch, be provided with the on-off controller of control circuit break-make, the control end of this on-off controller is connected with the output of described inverter, is controlled the state of described on-off controller by the output pulse of described inverter;
Wherein, the current branch in described dynamic deferred device is the branch road that current source is set;
The electric current of the current source arranging in described primary current leg is: x* inverter for removing the operating current in dead band; The electric current of the current source arranging in described auxiliary current branch is: y* inverter for removing the operating current in dead band; Wherein, the value that x and y be set makes the electric current sum of the auxiliary current branch of described primary current leg and conducting, and to be described inverter remove dead band operating current, 0 < x < 1 and 0 < y < 1.
4. phase frequency detector as claimed in claim 3, is characterized in that:
On the output of described trigger, connect latch and transmission gate, respectively output signal;
Described latch comprises the inverter of cascade, and the inverter link of described cascade is as the output of described latch, and the not connected one end of the inverter of described cascade is connected to the output of described trigger.
5. the phase frequency detector as described in claim 3 or 4, is characterized in that:
Described arithmetic logic unit comprises a plurality of NAND gate, and the input of described a plurality of NAND gate is connected respectively to the output of described trigger, and the output of described a plurality of NAND gate interconnects, and is connected to the input of the inverter in described dynamic deferred device.
6. a phase-locked loop, comprising: connected phase frequency detector, charge pump and loop filter successively, and described phase frequency detector comprises: dynamic deferred device, wherein:
Described dynamic deferred device comprises: inverter and many current branch, the earth terminal of described inverter is connected with one end of described many current branch respectively, one end ground connection not being connected with described inverter of described many current branch, described many current branch comprise primary current leg and auxiliary current branch, in described auxiliary current branch, be provided with the on-off controller of control circuit break-make, the control end of this on-off controller is connected with the output of described inverter, is controlled the state of described on-off controller by the output pulse of described inverter;
Wherein, the current branch in described dynamic deferred device is the branch road that current source is set;
The electric current of the current source arranging in described primary current leg is: x* inverter for removing the operating current in dead band; The electric current of the current source arranging in described auxiliary current branch is: y* inverter for removing the operating current in dead band; Wherein, the value that x and y be set makes the electric current sum of the auxiliary current branch of described primary current leg and conducting, and to be described inverter remove dead band operating current, 0 < x < 1 and 0 < y < 1.
7. phase-locked loop as claimed in claim 6, is characterized in that, described loop filter comprises: passive filter and resonant circuit, described resonant circuit is in parallel with described passive filter.
8. phase-locked loop as claimed in claim 7, is characterized in that, this phase-locked loop also comprises signal attenuation resistance, and this signal attenuation resistance is connected between described passive filter and the input of described loop filter.
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| CN103152035B (en) * | 2013-03-27 | 2016-04-13 | 武汉大学 | A kind of programmable delay multi-way control signals phase frequency detector for phase-locked loop |
| CN103986464B (en) * | 2014-05-22 | 2017-08-29 | 无锡中科微电子工业技术研究院有限责任公司 | A kind of cycle of phase-locked loop parameter self-calibrating device and method |
| CN105306023B (en) * | 2014-06-16 | 2017-12-01 | 力旺电子股份有限公司 | Pulse delay circuit |
| CN107112890B (en) * | 2014-10-27 | 2019-08-09 | 德克萨斯仪器股份有限公司 | Circuit, DC-DC converting system and the integrated circuit of dead time delay with temperature, technique and voltage compensation |
| CN108365750B (en) * | 2018-03-12 | 2020-04-03 | 昌芯(西安)集成电路科技有限责任公司 | Buck type DC/DC converter circuit with anti-ringing module circuit |
| CN110868211B (en) * | 2019-11-29 | 2022-05-24 | 电子科技大学 | Crystal oscillator vibration-proof compensation device and method based on binary coding |
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| CN1960184A (en) * | 2006-05-16 | 2007-05-09 | 威盛电子股份有限公司 | Phase frequence detector capable of reducing dead zone range |
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| US7042972B2 (en) * | 2003-04-09 | 2006-05-09 | Qualcomm Inc | Compact, low-power low-jitter digital phase-locked loop |
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| CN1960184A (en) * | 2006-05-16 | 2007-05-09 | 威盛电子股份有限公司 | Phase frequence detector capable of reducing dead zone range |
| CN101282116A (en) * | 2007-04-04 | 2008-10-08 | 阿尔特拉公司 | Phase frequency detectors generating minimum pulse widths |
| CN101409554A (en) * | 2007-10-11 | 2009-04-15 | 北京朗波芯微技术有限公司 | Loop filter circuit for charge pump phase-locked loop |
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