CN102344110B - Quad flat non-leaded package structure and method of micro electro mechanical system device - Google Patents
Quad flat non-leaded package structure and method of micro electro mechanical system device Download PDFInfo
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- CN102344110B CN102344110B CN201110336991.7A CN201110336991A CN102344110B CN 102344110 B CN102344110 B CN 102344110B CN 201110336991 A CN201110336991 A CN 201110336991A CN 102344110 B CN102344110 B CN 102344110B
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/48145—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/1015—Shape
- H01L2924/10155—Shape being other than a cuboid
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
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Abstract
The invention discloses a quad flat non-leaded (QFN) package structure and a quad flat non-leaded package method of a micro electro mechanical system (MEMS) device. The structure comprises a substrate, an application specific integrated circuit (ASIC) chip, an MEMS chip and a plastic material, wherein the ASIC chip is adhered to the substrate; the MEMS chip is adhered to the ASIC chip; the substrate, the ASIC chip and the MEMS chip are packaged and a lead on the substrate is exposed by the plastic material; a micro bonding pad on the ASIC chip is connected with a lead on the substrate through a lead wire; a micro bonding pad on the MEMS chip is connected with the micro bonding pad on the ASIC chip through a lead wire; and on the ASIC chip, the micro bonding pad which is connected with the micro bonding pad on the MEMS chip is different from the micro bonding pad which is connected with the lead on the substrate. In the invention, the ASIC chip and the MEMS chip are packaged into an MEMS device with the ASIC chip by using a stacking mode; the method has the advantages of small product size, simple manufacturing process, superior performance and high heat dissipation performance; the conventional QFN production and manufacturing process can be utilized; and another choice is provided for packaging of the MEMS device.
Description
Technical field
The present invention relates to micro-electromechanical system field, particularly relate to square flat pin-free packaging structure and the method for mems device.
Background technology
MEMS (Micro Electro Mechanical systems, MEMS (micro electro mechanical system)) technology is based upon the 21 century cutting edge technology on micrometer/nanometer technology (micro/nanotechnology) basis, refers to the technology designing micrometer/nanometer material, process, manufacture, measure and control.Mechanical component, optical system, driver part, electric-control system can be integrated into the microsystem of an integral unit by it.MEMS (micro electro mechanical system) can not only gather, process and transmission information or instruction, according to obtained information independence ground or can also take action according to the instruction of outside.The manufacturing process that it adopts microelectric technique and micro-processing technology to combine, produce various excellent performance, cheap, microminiaturized transducer, actuator, driver and micro-system, relative to traditional machinery, their size is less, thickness is thinner, and the automation of system, intellectuality and reliability level are higher.The application of MEMS is quite wide, and the market demand is powerful, is just becoming the focus that industry falls over each other to research and develop.
In MEMS product, due to the scope of application of various product and the difference of applied environment, it encapsulates the unified form of also neither one, suitable encapsulation should be selected according to concrete service condition, meanwhile, in the manufacture process of MEMS product, encapsulation can only single carrying out and can not simultaneously producing in enormous quantities, therefore be encapsulated in MEMS product total cost and occupy 70%-80%, encapsulation technology has become the bottleneck in MEMS production.Current MEMS package technology is mostly developed by integrated antenna package technical development, but due to the complexity of its applied environment, make it have again very large particularity compared with integrated antenna package, simply integrated antenna package directly can not be removed package of MEMS device.How to realize the low cost of MEMS, small size, high reliability packaging, and make it gradually to form standard set technique, become the focus of research and development MEMS package technology in industry.
In recent years, MEMS package technology has made great progress, there is numerous MEMS package technology, great majority research all concentrates on the different packaging technologies of special applications, although the nuance distinguished between different method for packing is very difficult, usually can be divided into the encapsulation level that 3 basic: (1) wafer-level package; (2) wafer level packaging; (3) system in package.QFN (Quad Flat Non-leaded Package, quad flat non-pin package) be packaging technology more advanced in semiconductor packages in recent years, belong to the one of wafer-level package technology, it is using plastics as encapsulant, the product of encapsulation is square, the pin apportion that is also square is arranged in base bottom surrounding, and there is heat dissipation metal district at matrix center.Product size after encapsulation is little, power path is short, electrical property is good, thermal diffusivity is good, reliability is high, be applicable to the high-end precise electronic product field such as mobile phone, communication, number, automotive electronics performance and volume being had to strict demand, its main technique has: wafer back part grinding → wafer cuts into single chips → chip and base plate bonding → wire bonding → plastic packaging → lettering → cutting (chip is separated from one another with chip) → capture (chip is separated from substrate) → test → pack shipment.Typical encapsulating structure as depicted in figs. 1 and 2.Substrate mainly comprises pin 1 and metal welding crystalline region 3.Integrated circuit bare chip 5 is adhered on the metal welding crystalline region 3 of substrate by adhesive glue 7.Pin 1 on substrate is connected by lead-in wire 11 bonding with the mini-pads 9 on integrated circuit bare chip 5, completes electric interconnection.By plastic packaging material 13, whole matrix is encapsulated again.
Usual MEMS will realize specific function to be needed by ASIC (Application Specific IntergratedCircuits, application-specific integrated circuit (ASIC)) chip, and because the technique that manufactures MEMS is with to manufacture the technique difference of ASIC larger, cannot manufacture in CMOS (Complementary Metal Oxide Semiconductor, complementary metal oxide semiconductors (CMOS)) wafer manufacturing process simultaneously.
Summary of the invention
The embodiment of the present invention provides a kind of quad flat non-pin package QFN structure of micro-electromechanical system (MEMS) device, the MEMS that there is asic chip in order to provide one, the advantage that product size is little to possess, manufacturing process simple, superior performance, thermal diffusivity are good, comprising:
Substrate;
Be pasted on the application-specific integrated circuit ASIC chip on described substrate;
Be pasted on the MEMS chip on described asic chip;
Encapsulate described substrate, asic chip, MEMS chip the plastic packaging material of pin on exposed described substrate;
Mini-pads on described asic chip is connected with the pin on described substrate by lead-in wire; Mini-pads in described MEMS chip is connected with the mini-pads on described asic chip by lead-in wire; On described asic chip, the mini-pads be connected with mini-pads in described MEMS chip is different from the mini-pads be connected with pin on described substrate, wherein, described MEMS chip has upper cover plate and lower shoe, groove is established on the one side in described lower shoe front or both sides, mini-pads in described MEMS chip is arranged evenly in described groove, and described upper cover plate and lower shoe are thinned to target thickness.
In an embodiment, described asic chip is pasted on described substrate by adhesive; Described MEMS chip is pasted on the viscous crystal region on described asic chip by adhesive.
In an embodiment, described substrate is established metal welding crystalline region, described asic chip is pasted on the metal welding crystalline region on described substrate by adhesive.
In an embodiment, described adhesive is non-conductive high conductivity material.
In an embodiment, described adhesive is epoxide resin material.
In an embodiment, described MEMS chip has upper cover plate and lower shoe, and described lower shoe has the front of mini-pads in exposed described MEMS chip.
In an embodiment, described substrate is lead frame or printed circuit board (PCB).
In an embodiment, described lead-in wire is gold thread, copper cash or silver-colored line.
The embodiment of the present invention also provides a kind of quad flat non-pin package QFN method of micro-electromechanical system (MEMS) device, the MEMS that there is asic chip in order to provide one, the advantage that product size is little to possess, manufacturing process simple, superior performance, thermal diffusivity are good, comprising:
One substrate strip is provided, described substrate strip has the substrate of multiple same structures of array arrangement;
The upper cover plate of MEMS wafer and lower shoe are distinguished thinning, by the thinning back side of ASIC wafer; Described MEMS wafer is established the MEMS chip of multiple same structures of array arrangement; Described ASIC wafer is established the asic chip of multiple same structures of array arrangement, the back side of described ASIC wafer and described ASIC wafer are provided with the vis-a-vis of mini-pads;
Described MEMS wafer is cut into multiple MEMS chip, described ASIC wafer is cut into multiple asic chip;
Asic chip is affixed on substrate, MEMS chip is affixed on asic chip, be heating and curing after obtaining the matrix pasted;
By lead-in wire, the mini-pads in MEMS chip is connected with the mini-pads on asic chip, the mini-pads on asic chip is connected with the pin on substrate; Wherein on asic chip, the mini-pads be connected with mini-pads in MEMS chip is different from the mini-pads be connected with pin on substrate;
Pin with plastic packaging material enclosing substrate and on exposed substrate;
Substrate strip after encapsulating is cut into single packaging body separated from one another.
In an embodiment, described that the upper cover plate of MEMS wafer and lower shoe is thinning respectively, after the thinning back side of ASIC wafer, first by adhesive printing to the back side of MEMS wafer lower shoe after thinning and the back side of ASIC wafer, again described MEMS wafer is cut into multiple MEMS chip, described ASIC wafer is cut into multiple asic chip; The back side of wherein said lower shoe and described lower shoe are provided with the vis-a-vis of mini-pads;
Described asic chip is affixed on substrate, MEMS chip is affixed on asic chip, comprising:
By described substrate strip preheating, the asic chip with adhesive is affixed to the metal welding crystalline region on substrate, the MEMS chip with adhesive is affixed to the viscous crystal region on asic chip.
In an embodiment, described that the upper cover plate of MEMS wafer and lower shoe is thinning respectively, after the thinning back side of ASIC wafer, first by adhesive printing to the back side of MEMS wafer lower shoe after thinning and the back side of ASIC wafer, again described MEMS wafer is cut into multiple MEMS chip, described ASIC wafer is cut into multiple asic chip; The back side of wherein said lower shoe and described lower shoe are provided with the vis-a-vis of mini-pads;
Described asic chip is affixed on substrate, MEMS chip is affixed on asic chip, comprising:
Stick adhesive tape at the back side of described substrate strip, the back side of described substrate strip is connected the vis-a-vis of mini-pads on asic chip with pin in described substrate strip; Asic chip with adhesive is affixed to the hollow region in the middle of substrate, the MEMS chip with adhesive is affixed to the viscous crystal region on asic chip;
The adhesive tape at the back side of substrate strip also, after pin on exposed substrate, is first removed, then the substrate strip after encapsulating is cut into single packaging body separated from one another by described plastic packaging material enclosing substrate.
In an embodiment, described described MEMS wafer is cut into multiple MEMS chip, after described ASIC wafer is cut into multiple asic chip, first the substrate in described substrate strip is put glue respectively;
Described asic chip is affixed on substrate, MEMS chip is affixed on asic chip, comprising:
Asic chip is affixed to the metal welding crystalline region on substrate;
Viscous crystal region point glue on asic chip, affixes to the viscous crystal region on asic chip by MEMS chip; Or by adhesive printing to the back side of MEMS chip lower shoe, the back side of described lower shoe and described lower shoe are provided with the vis-a-vis of mini-pads, the MEMS chip with adhesive is affixed to the viscous crystal region on asic chip.
In an embodiment, described lower shoe front or both sides establish groove, the mini-pads in described MEMS chip is arranged evenly in described groove.
In an embodiment, described MEMS wafer is cut into multiple MEMS chip, comprising:
Adopt two cutter cutting process that described MEMS wafer is cut into multiple MEMS chip, wherein the first cutter is wide cutter, and the second cutter is narrow cutter.
In an embodiment, the depth degree of cutting of described first cutter is identical with the degree of depth of described groove, and described second cutter wears whole MEMS wafer for cutting; Or the depth degree of cutting of described first cutter is greater than the degree of depth of described groove and is less than the degree of depth of whole MEMS wafer, and described second cutter wears whole MEMS wafer for cutting.
In an embodiment, described ASIC wafer is cut into multiple asic chip, comprising:
Adopt single solution for diverse problems technique that described ASIC wafer is cut into multiple asic chip; Or adopt two cutter cutting process that described ASIC wafer is cut into multiple asic chip, wherein the first cutter is wide cutter, and the second cutter is narrow cutter.
The quad flat non-pin package QFN structure of the micro-electromechanical system (MEMS) device of the embodiment of the present invention and method, adopt stacking mode, asic chip and MEMS chip are encapsulated as the MEMS with asic chip, there is the advantage that product size is little, manufacturing process simple, superior performance, thermal diffusivity are good, and existing QFN manufacturing process can be utilized, the encapsulation for MEMS provides another kind of and selects.
Accompanying drawing explanation
In order to be illustrated more clearly in the embodiment of the present invention or technical scheme of the prior art, be briefly described to the accompanying drawing used required in embodiment or description of the prior art below, apparently, accompanying drawing in the following describes is only some embodiments of the present invention, for those of ordinary skill in the art, under the prerequisite not paying creative work, other accompanying drawing can also be obtained according to these accompanying drawings.In the accompanying drawings:
Fig. 1, Fig. 2 are the schematic diagram of QFN encapsulating structure in prior art;
Fig. 3 is by schematic diagram thinning for MEMS wafer in the embodiment of the present invention;
Fig. 4 is by schematic diagram thinning for ASIC wafer in the embodiment of the present invention;
Fig. 5 be in the embodiment of the present invention by adhesive printing to the schematic diagram at the back side of the MEMS chip lower shoe after thinning;
Fig. 6 be in the embodiment of the present invention by adhesive printing to the schematic diagram at the back side of the asic chip after thinning;
Fig. 7 is the schematic diagram cutting MEMS wafer in the embodiment of the present invention;
Fig. 7-1, Fig. 7-2 cut depth degree schematic diagram for the first cutter when MEMS wafer in the embodiment of the present invention is cut;
Fig. 7-3, Fig. 7-4 cut depth degree schematic diagram for the second cutter when MEMS wafer in the embodiment of the present invention is cut;
Schematic top plan view when Fig. 7-5 is MEMS wafer cutting in the embodiment of the present invention;
Fig. 8 is the schematic diagram cutting ASIC wafer in the embodiment of the present invention;
Fig. 9 is the schematic diagram of an instantiation of the matrix pasted in the embodiment of the present invention;
Figure 10 is the schematic diagram of an instantiation of the matrix connected of going between in the embodiment of the present invention;
Figure 11, Figure 12 are the schematic diagram of a specific embodiment of the QFN structure of MEMS in the embodiment of the present invention;
Figure 13, Figure 14 are the schematic diagram of another specific embodiment of the QFN structure of MEMS in the embodiment of the present invention.
Embodiment
For making the object of the embodiment of the present invention, technical scheme and advantage clearly understand, below in conjunction with accompanying drawing, the embodiment of the present invention is described in further details.At this, schematic description and description of the present invention is for explaining the present invention, but not as a limitation of the invention.
Figure 11 and Figure 12 is the schematic diagram of a specific embodiment of the QFN structure of MEMS in the embodiment of the present invention.Figure 13 and Figure 14 is the schematic diagram of another specific embodiment of the QFN structure of MEMS in the embodiment of the present invention.With reference to figures 11 to Figure 14, in the embodiment of the present invention, the QFN structure of MEMS can comprise:
Substrate;
Be pasted on the asic chip 20 on substrate;
Be pasted on the MEMS chip 10 on asic chip 20;
Encapsulating substrate, asic chip 20, MEMS chip 10 plastic packaging material 28 of pin 18 on exposed substrate;
Mini-pads 16 on asic chip 20 is connected with the pin 18 on substrate by lead-in wire 26; Mini-pads 14 in MEMS chip 10 is connected with the mini-pads 16 on asic chip 20 by lead-in wire 24; Wherein, on asic chip 20, the mini-pads be connected with mini-pads 14 in MEMS chip 10 is different from the mini-pads be connected with pin on substrate 18.
During concrete enforcement, substrate be provided be distributed in around or or some pins 18 on both sides or four limits, some pins 18 are connected with each other by interconnect.Substrate is provided with front and back, and the one side that on substrate, pin 18 is connected with mini-pads 16 on asic chip 20 is front, and relative face is the back side.The one side that asic chip 20 is provided with mini-pads 16 is front, and one side on the other side is the back side.The surrounding in asic chip 20 front can establish some mini-pads 16, and the front of asic chip 20 is also provided with the viscous crystal region for pasting MEMS chip 10.MEMS chip 10 has upper cover plate and lower shoe, and the one side that lower shoe is provided with mini-pads 14 is front, and one side on the other side is the back side.The front of MEMS chip 10 lower shoe can exposed some mini-pads 14, in an embodiment, groove 30 can be established in one side or the both sides in the front of MEMS chip 10 lower shoe, it is such as the groove of strip, mini-pads 14 in MEMS chip 10 is arranged evenly in groove 30, can not destroy the circuit layer structure in MEMS chip like this when carrying out MEMS chip 10 reduction processing.
During concrete enforcement, asic chip 20 is pasted on substrate by adhesive 12; MEMS chip 10 is pasted on the viscous crystal region on asic chip 20 by adhesive 12.As is illustrated by figs. 11 and 12, in an embodiment, substrate can establish metal welding crystalline region 22, asic chip 20 is pasted on the metal welding crystalline region 22 on substrate by adhesive 12.Substrate shown in Figure 13 and Figure 14 there is no metal welding crystalline region 22.
During concrete enforcement, adhesive 12 can be non-conductive high conductivity material, such as, can be epoxide resin material.Substrate can be lead frame (Lead frame), can also be PCB (Printed Circuit Board, printed circuit board (PCB)).Lead-in wire 24,26 can be gold thread, copper cash or silver-colored line.
The embodiment of the present invention also provides a kind of QFN method of MEMS, and its handling process can comprise:
Step 1, provide a substrate strip, described substrate strip has the substrate of multiple same structures of array arrangement;
Step 2, the upper cover plate of MEMS wafer and lower shoe is thinning respectively, by the thinning back side of ASIC wafer; Described MEMS wafer is established the MEMS chip of multiple same structures of array arrangement; Described ASIC wafer is established the asic chip of multiple same structures of array arrangement, the back side of described ASIC wafer and described ASIC wafer are provided with the vis-a-vis of mini-pads; Front, the back side of the front of ASIC wafer, the back side and asic chip are consistent; Fig. 3 is by schematic diagram thinning for MEMS wafer, in Fig. 3, the upper cover plate of MEMS chip 10 and lower shoe is thinned to target thickness respectively; Fig. 4 is by schematic diagram thinning for ASIC wafer, by the thinning back side of asic chip 20 in Fig. 4;
Step 3, described MEMS wafer is cut into multiple MEMS chip, described ASIC wafer is cut into multiple asic chip; Fig. 7 is the schematic diagram of cutting MEMS wafer; Fig. 7-5 is schematic top plan view when MEMS wafer is cut; Fig. 8 is the schematic diagram of cutting ASIC wafer;
Step 4, asic chip is affixed on substrate, MEMS chip is affixed on asic chip, be heating and curing after obtaining the matrix pasted; Fig. 9 is the schematic diagram of an instantiation of the matrix pasted;
Step 5, by lead-in wire the mini-pads in MEMS chip is connected with the mini-pads on asic chip, the mini-pads on asic chip is connected with the pin on substrate; Wherein on asic chip, the mini-pads be connected with mini-pads in MEMS chip is different from the mini-pads be connected with pin on substrate; Figure 10 is the schematic diagram of an instantiation of the matrix that lead-in wire connects;
Step 6, with plastic packaging material enclosing substrate and pin on exposed substrate;
Step 7, by encapsulating after substrate strip cut into single packaging body separated from one another.
During concrete enforcement, each substrate in substrate strip is provided with front and back, and the one side that on substrate, pin is connected with mini-pads on asic chip is front, and relative face is the back side.Front, the back side of the front of substrate strip, the back side and substrate are consistent.Substrate strip can be leadframe strip, also can be printed circuit board (PCB).
During concrete enforcement, asic chip is affixed on substrate, MEMS chip is affixed on asic chip and have numerous embodiments.
In an embodiment, can the upper cover plate of MEMS wafer and lower shoe distinguished thinning, after the thinning back side of ASIC wafer, first by adhesive printing to the back side of MEMS wafer lower shoe after thinning and the back side of ASIC wafer, again MEMS wafer is cut into multiple MEMS chip, ASIC wafer is cut into multiple asic chip; Wherein the back side of MEMS wafer lower shoe and MEMS wafer lower shoe are provided with the vis-a-vis of mini-pads; Front, the back side of the front of MEMS wafer lower shoe, the back side and MEMS chip lower shoe are consistent.As shown in Figure 5, adhesive 12 is printed the back side to MEMS chip 10 lower shoe after thinning; As shown in Figure 6, adhesive 12 is printed the back side to the asic chip 20 after thinning.
During enforcement, on the full wafer wafer after can utilizing printing machine that adhesive printing is extremely thinning, the back side of MEMS wafer printing lower shoe, ASIC wafer printed back.Wherein adhesive can be non-conductive high conductivity material, as epoxide resin material.
In this embodiment, asic chip is affixed on substrate, MEMS chip is affixed on asic chip, can comprise: by substrate strip preheating, asic chip with adhesive is affixed to the metal welding crystalline region on substrate, the MEMS chip with adhesive is affixed to the viscous crystal region on asic chip.Bonder can be utilized during enforcement by substrate strip preheating, the asic chip with adhesive is affixed to the metal welding crystalline region on substrate.Fig. 9 is the schematic diagram of the matrix pasted in this embodiment.Figure 10 is that the matrix pasted in this embodiment carries out going between the schematic diagram after connecting.
In another embodiment, shown in same Fig. 5, Fig. 6, can the upper cover plate of MEMS wafer and lower shoe distinguished thinning, after the thinning back side of ASIC wafer, first by adhesive printing to the back side of MEMS wafer lower shoe after thinning and the back side of ASIC wafer, again MEMS wafer is cut into multiple MEMS chip, ASIC wafer is cut into multiple asic chip.
In this embodiment, substrate does not have metal welding Jin Qu, tape technique and band technique of removing photoresist need be introduced, that is: asic chip is affixed on substrate, MEMS chip is affixed on asic chip, can comprise: stick adhesive tape at the back side of substrate strip; Asic chip with adhesive is affixed to the hollow region in the middle of substrate, the MEMS chip with adhesive is affixed to the viscous crystal region on asic chip.After the pin with plastic packaging material enclosing substrate and on exposed substrate, first the adhesive tape at the back side of substrate strip is removed, such as, with going sealing-tape machine, the adhesive tape at the back side of substrate strip can be removed, then the substrate strip after encapsulating is cut into single packaging body separated from one another.
Chip attach mode is except adopting the mode of above-mentioned wafer brush coating, in another embodiment, also can adopt the mode of a glue, that is: MEMS wafer can cut into multiple MEMS chip, after ASIC wafer is cut into multiple asic chip, first the substrate in substrate strip is put glue respectively;
In this embodiment, asic chip is affixed on substrate, MEMS chip is affixed on asic chip, can comprise:
Asic chip is affixed to the metal welding crystalline region on substrate;
Viscous crystal region point glue on asic chip, affixes to the viscous crystal region on asic chip by MEMS chip; Or MEMS chip also can adopt the mode of brush coating, that is: by adhesive printing to the back side of MEMS chip lower shoe, the MEMS chip with adhesive is affixed to the viscous crystal region on asic chip; Wherein the back side of MEMS chip lower shoe and MEMS chip lower shoe are provided with the vis-a-vis of mini-pads; Front, the back side of the front of MEMS wafer lower shoe, the back side and MEMS chip lower shoe are consistent.
During concrete enforcement, MEMS chip lower shoe front or both sides can establish groove, the mini-pads in MEMS chip is arranged evenly in groove.As shown in Figure 3,4, when the upper cover plate of MEMS wafer and lower shoe are thinned to target thickness respectively, because mini-pads is positioned at groove, the circuit layer structure of wafer can not time thinning, be destroyed.
During concrete enforcement, because MEMS wafer is sealed between lower shoe and upper cover plate, structure sensitive own is fragile, very easily cause when carrying out wafer cutting and break, therefore, when MEMS wafer is cut into multiple MEMS chip, can adopt two cutter cutting process, the first cutter is wide cutter, and the second cutter is narrow cutter.Wherein, the depth degree of cutting of the first cutter can be identical with the degree of depth of groove, namely cuts into the wafer degree of depth for being switched to bottom portion of groove, as shown in Fig. 7-1; The depth degree of cutting of the first cutter also can be greater than the degree of depth of groove and be less than the degree of depth of whole MEMS wafer, namely cuts into a bottom portion of groove part, as shown in Fig. 7-2; Second cutter wears whole MEMS wafer for cutting, if the back side of MEMS wafer lower shoe is with adhesive, namely the second cutter should cut the glue-line wearing printing, as shown in Fig. 7-3,7-4.
During concrete enforcement, when ASIC wafer being cut into multiple asic chip, single solution for diverse problems technique can be adopted, also can adopt two cutter cutting process.As with two cutter cutting process then the first cutter be wide cutter, the second cutter is narrow cutter.
During concrete enforcement, wire bonder can be utilized to be connected with the mini-pads on asic chip by the mini-pads in MEMS chip, be connected by the mini-pads on asic chip with the pin on substrate, lead-in wire can be gold thread, copper cash or silver-colored line.
In sum, the quad flat non-pin package QFN structure of the micro-electromechanical system (MEMS) device of the embodiment of the present invention and method, adopt stacking mode, asic chip and MEMS chip are encapsulated as the MEMS with asic chip, there is the advantage that product size is little, manufacturing process simple, superior performance, thermal diffusivity are good, and existing QFN manufacturing process can be utilized, the encapsulation for MEMS provides another kind of and selects.
Above-described specific embodiment; object of the present invention, technical scheme and beneficial effect are further described; be understood that; the foregoing is only specific embodiments of the invention; the protection range be not intended to limit the present invention; within the spirit and principles in the present invention all, any amendment made, equivalent replacement, improvement etc., all should be included within protection scope of the present invention.
Claims (15)
1. a quad flat non-pin package QFN structure for micro-electromechanical system (MEMS) device, is characterized in that, comprising:
Substrate;
Be pasted on the application-specific integrated circuit ASIC chip on described substrate;
Be pasted on the MEMS chip on described asic chip;
Encapsulate described substrate, asic chip, MEMS chip the plastic packaging material of pin on exposed described substrate;
Mini-pads on described asic chip is connected with the pin on described substrate by lead-in wire; Mini-pads in described MEMS chip is connected with the mini-pads on described asic chip by lead-in wire; On described asic chip, the mini-pads be connected with mini-pads in described MEMS chip is different from the mini-pads be connected with pin on described substrate;
Wherein, described MEMS chip has upper cover plate and lower shoe, described lower shoe front or both sides establish groove, the mini-pads in described MEMS chip is arranged evenly in described groove, and described upper cover plate and lower shoe are thinned to target thickness.
2. the QFN structure of MEMS as claimed in claim 1, it is characterized in that, described asic chip is pasted on described substrate by adhesive; Described MEMS chip is pasted on the viscous crystal region on described asic chip by adhesive.
3. the QFN structure of MEMS as claimed in claim 2, it is characterized in that, described substrate is established metal welding crystalline region, described asic chip is pasted on the metal welding crystalline region on described substrate by adhesive.
4. the QFN structure of MEMS as claimed in claim 2 or claim 3, it is characterized in that, described adhesive is non-conductive high conductivity material.
5. the QFN structure of MEMS as claimed in claim 4, it is characterized in that, described adhesive is epoxide resin material.
6. the QFN structure of MEMS as claimed in claim 1, it is characterized in that, described lower shoe has the front of mini-pads in exposed described MEMS chip.
7. the QFN structure of MEMS as claimed in claim 1, it is characterized in that, described substrate is lead frame or printed circuit board (PCB).
8. the QFN structure of MEMS as claimed in claim 1, it is characterized in that, described lead-in wire is gold thread, copper cash or silver-colored line.
9. a quad flat non-pin package QFN method for micro-electromechanical system (MEMS) device, is characterized in that, comprising:
One substrate strip is provided, described substrate strip has the substrate of multiple same structures of array arrangement;
The upper cover plate of MEMS wafer and lower shoe are distinguished thinning, by the thinning back side of ASIC wafer; Described MEMS wafer is established the MEMS chip of multiple same structures of array arrangement; Described ASIC wafer is established the asic chip of multiple same structures of array arrangement, the back side of described ASIC wafer and described ASIC wafer are provided with the vis-a-vis of mini-pads, establish groove on the one side in described lower shoe front or both sides, the mini-pads in described MEMS chip is arranged evenly in described groove;
Described MEMS wafer is cut into multiple MEMS chip, described ASIC wafer is cut into multiple asic chip;
Asic chip is affixed on substrate, MEMS chip is affixed on asic chip, be heating and curing after obtaining the matrix pasted;
By lead-in wire, the mini-pads in MEMS chip is connected with the mini-pads on asic chip, the mini-pads on asic chip is connected with the pin on substrate; Wherein on asic chip, the mini-pads be connected with mini-pads in MEMS chip is different from the mini-pads be connected with pin on substrate;
Pin with plastic packaging material enclosing substrate and on exposed substrate;
Substrate strip after encapsulating is cut into single packaging body separated from one another.
10. method as claimed in claim 9, it is characterized in that, described that the upper cover plate of MEMS wafer and lower shoe is thinning respectively, after the thinning back side of ASIC wafer, first by adhesive printing to the back side of MEMS wafer lower shoe after thinning and the back side of ASIC wafer, again described MEMS wafer is cut into multiple MEMS chip, described ASIC wafer is cut into multiple asic chip; The back side of wherein said lower shoe and described lower shoe are provided with the vis-a-vis of mini-pads;
Described asic chip is affixed on substrate, MEMS chip is affixed on asic chip, comprising:
By described substrate strip preheating, the asic chip with adhesive is affixed to the metal welding crystalline region on substrate, the MEMS chip with adhesive is affixed to the viscous crystal region on asic chip.
11. methods as claimed in claim 9, it is characterized in that, described that the upper cover plate of MEMS wafer and lower shoe is thinning respectively, after the thinning back side of ASIC wafer, first by adhesive printing to the back side of MEMS wafer lower shoe after thinning and the back side of ASIC wafer, again described MEMS wafer is cut into multiple MEMS chip, described ASIC wafer is cut into multiple asic chip; The back side of wherein said lower shoe and described lower shoe are provided with the vis-a-vis of mini-pads;
Described asic chip is affixed on substrate, MEMS chip is affixed on asic chip, comprising:
Stick adhesive tape at the back side of described substrate strip, the back side of described substrate strip is connected the vis-a-vis of mini-pads on asic chip with pin in described substrate strip; Asic chip with adhesive is affixed to the hollow region in the middle of substrate, the MEMS chip with adhesive is affixed to the viscous crystal region on asic chip;
The adhesive tape at the back side of substrate strip also, after pin on exposed substrate, is first removed, then the substrate strip after encapsulating is cut into single packaging body separated from one another by described plastic packaging material enclosing substrate.
12. methods as claimed in claim 9, is characterized in that, described described MEMS wafer are cut into multiple MEMS chip, after described ASIC wafer is cut into multiple asic chip, first the substrate in described substrate strip are put glue respectively;
Described asic chip is affixed on substrate, MEMS chip is affixed on asic chip, comprising:
Asic chip is affixed to the metal welding crystalline region on substrate;
Viscous crystal region point glue on asic chip, affixes to the viscous crystal region on asic chip by MEMS chip; Or by adhesive printing to the back side of MEMS chip lower shoe, the back side of described lower shoe and described lower shoe are provided with the vis-a-vis of mini-pads, the MEMS chip with adhesive is affixed to the viscous crystal region on asic chip.
13. methods as described in claim 10,11 or 12, is characterized in that, described MEMS wafer is cut into multiple MEMS chip, comprising:
Adopt two cutter cutting process that described MEMS wafer is cut into multiple MEMS chip, wherein the first cutter is wide cutter, and the second cutter is narrow cutter.
14. methods as claimed in claim 13, is characterized in that, the depth degree of cutting of described first cutter is identical with the degree of depth of described groove, and described second cutter wears whole MEMS wafer for cutting; Or the depth degree of cutting of described first cutter is greater than the degree of depth of described groove and is less than the degree of depth of whole MEMS wafer, and described second cutter wears whole MEMS wafer for cutting.
15. methods as described in claim 10,11 or 12, is characterized in that, described ASIC wafer is cut into multiple asic chip, comprising:
Adopt single solution for diverse problems technique that described ASIC wafer is cut into multiple asic chip; Or adopt two cutter cutting process that described ASIC wafer is cut into multiple asic chip, wherein the first cutter is wide cutter, and the second cutter is narrow cutter.
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| US9209152B2 (en) * | 2013-04-19 | 2015-12-08 | Infineon Technologies Ag | Molding material and method for packaging semiconductor chips |
| CN104091765A (en) * | 2014-07-14 | 2014-10-08 | 深迪半导体(上海)有限公司 | Packaging method targeted for MEMS inertial device semiconductor |
| US9527727B2 (en) * | 2014-09-26 | 2016-12-27 | Stmicroelectronics (Malta) Ltd | Packages for semiconductor devices and methods for assembling same |
| CN104465595B (en) * | 2014-12-02 | 2017-04-05 | 天水华天科技股份有限公司 | CSP type MEMS package parts and production method based on custom lead-frame |
| CN104779223A (en) * | 2015-04-10 | 2015-07-15 | 华进半导体封装先导技术研发中心有限公司 | Fingerprint identification chip packaging structure provided with unilateral groove and manufacturing method |
| CN105253851B (en) * | 2015-09-14 | 2017-03-22 | 合肥芯福传感器技术有限公司 | Chip-level system sensor and preparation method thereof |
| CN106335868A (en) * | 2016-08-31 | 2017-01-18 | 歌尔股份有限公司 | Packaging structure of MEMS (Micro Electro Mechanical Systems) chip integration |
| CN107797049B (en) * | 2017-09-28 | 2021-09-28 | 北京时代民芯科技有限公司 | IC chip back observation sample and manufacturing method thereof |
| CN108996467A (en) * | 2018-08-08 | 2018-12-14 | 宁波琻捷电子科技有限公司 | Sensor-packaging structure and method |
| CN110248298A (en) * | 2019-05-13 | 2019-09-17 | 苏州捷研芯纳米科技有限公司 | Silicon microphone and its processing method |
| CN110708623B (en) * | 2019-09-18 | 2020-12-18 | 潍坊歌尔微电子有限公司 | Microphone calibration method and microphone packaging structure |
| CN111099555B (en) * | 2019-12-17 | 2023-06-16 | 北京航天控制仪器研究所 | Manufacturing method of glass cavity suitable for wafer level vacuum packaging |
| CN112811387B (en) * | 2021-01-19 | 2023-12-26 | 潍坊歌尔微电子有限公司 | Waterproof barometer processing technology and waterproof barometer |
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