CN102339641B - Error checking and correcting verification module and data reading-writing method thereof - Google Patents
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Abstract
The invention discloses an error checking and correcting (ECC) verification module and a data reading-writing method of the module, so as to solve the technical defect of low flexibility in present ECC verification modules. The verification module comprises: an ECC circuit used for ECC treatment of an ECC code word so as to obtain an error checked and corrected data set; a latch used for storing the error checked and corrected data set and updating the received input data to corresponding data positions in the checked and corrected data set, thus forming a data set to be written in; a verification circuit used for real-time verification of the data set to be written in and for generation of a verification bit corresponding to the data set to be written in; a write buffer used for writing the data set to be written in and a corresponding verification bit thereof into a storage medium. The embodiment of the invention realizes reading data from a main array or writing data into the main array in ECC code words, so that the control is easier and the data writing operation is speeded up.
Description
Technical field
Invention relates to nonvolatile memory, particularly relates to the method that error detection/correction (Error Checking andCorrecting, ECC) correction verification module and this module read and write data.
Background technology
Along with the develop rapidly of integrated circuit, the integrated level of semiconductor memory is more and more higher, and capacity is also increasing.Thing followed problem is that the reliability of semiconductor memory and yield rate face serious challenge, such as signal to noise ratio (S/N ratio) reduces along with the increase of integrated level, the reduction of the memory node quantity of electric charge makes storage cell more easily by the impact of cosmic rays, and the process deviation under deep sub-micron technique and fault in material cause the reduction etc. of storer yield rate.
Error correcting code be a kind of not only can detect mistake and also can Wrong localization position and and then correct a mistake one class coding, be a kind of important fault-tolerant technique in semiconductor memory.Hamming code is a kind of conventional error correcting code, because it is simple, be easy to the features such as realization, is able to widespread use in memory.
According to the theory of Hamming code, in Hamming code, the number of check bit need meet following relation:
2
k>=m+k+1 (formula 1)
Wherein:
K is check bit number;
M is data bit number.
As can be seen from above-mentioned formula 1, the ratio of data bit more at most shared by check bit is lower, that is adopts the area overhead of ECC circuit less.Such as, the data bit of 1 byte (byte) needs the check bit of 4 bits, and the area overhead of storage array is 50%; The data bit of 4 bytes then needs the check bit of 6 bits, and the area overhead of storage array is 18.8%.
It is the nonvolatile memory with ECC circuit carrying out data transmission in units of byte for external interface, in order to the problem reducing memory area expense can be solved in prior art, generally adopt the ECC code word of multibyte data position, enable check bit take less ratio.
But realizing in process of the present invention, when inventor finds that memory inside is read and write, what prior art adopted is the ECC code word of multibyte data position, especially when internally storage array writes new data, as page (Page with larger mikey, as 128KB) operate, if input data volume is discontented with one page (the current right and wrong of this situation are usually shown in), then the write time can be increased, greatly reduce storage dirigibility, extremely waste the space of write operation, and unnecessary erase/program operations can reduce the serviceable life of storer greatly in operating process.
Summary of the invention
Technical matters to be solved by this invention is the technology needing to provide a kind of ECC correction verification module and this module to read and write data, to solve the low technological deficiency of existing ECC correction verification module dirigibility.
In order to solve the problems of the technologies described above, the invention provides a kind of error detection/correction (ECC) correction verification module, comprising error detection/correction circuit, latch, checking circuit and write buffer, wherein:
Described error detection/correction circuit, for carrying out error detection/correction process to ECC code word, obtains the data group after error detection/correction;
Described latch, for storing the data group after described error detection/correction, by the corresponding data position in the data group after received input Data Update to described error detection/correction, forms data group to be written;
Described checking circuit, for verifying in real time described data group to be written, generates the check bit corresponding to described data group to be written; And
Described write buffer, for being written to described data group to be written and its corresponding check bit in storage medium.
Preferably, described error detection/correction circuit carries out described error detection/correction process for adopting the data group of the check bit of described ECC code word to described ECC code word.
Preferably, described latch is used in units of predetermined length, receive described input data.
Preferably, described latch be used in units of predetermined length by the corresponding data position in the data group after described input Data Update to described error detection/correction, form described data group to be written.
Preferably, described latch is used in units of byte, receive described input data, and/or with byte unit by the corresponding data position in the data group after described input Data Update to described error detection/correction.
Preferably, described write buffer is used for described data group to be written and its corresponding check bit being written in described storage medium with the form of ECC code word.
Preferably, described write buffer is used for the new ECC code word that buffer memory is formed by described data group to be written and its corresponding check bit, and is written in described storage medium by the described new ECC code word identified by flag;
Wherein, each described new ECC code word is respectively to having flag, and this flag plays the effect from described write buffer to the write-enable of described storage medium.
Preferably, when the data volume that described write buffer is used for being formed in described new ECC code word exceedes self-capacity, upgrade by the new ECC code word exceeded from start address.
Preferably, the capacity of described write buffer equals the capacity of described storage medium one page.
In order to solve the problems of the technologies described above, the invention allows for a kind of method of read data of error detection/correction (ECC) correction verification module as above, the method comprises:
Receive the read operation request of user;
Described error detection/correction circuit, according to described read operation request, obtains corresponding ECC code word from storage medium;
Described error detection/correction circuit carries out error detection/correction process to described ECC code word, obtains and data group after exporting error detection/correction.
Preferably, export the step of the data group after described error detection/correction, comprising:
The data group after described error detection/correction is exported in units of predetermined length.
Preferably, in units of described predetermined length, export the step of the data group after described error detection/correction, comprising:
The data group after described error detection/correction is exported in units of byte.
In order to solve the problems of the technologies described above, the invention allows for a kind of method writing data of error detection/correction (ECC) correction verification module as above, the method comprises:
The write operation requests receiving user and the input data that will write;
Described error detection/correction circuit obtains corresponding ECC code word according to described write operation requests from storage medium, and carries out error detection/correction process to described ECC code word, obtains the data group after error detection/correction and sends to described latch;
Data group after error detection/correction described in described latch stores, by the corresponding data position in the data group after described input Data Update to described error detection/correction, forms data group to be written and sends to described checking circuit and write buffer;
Described checking circuit verifies in real time to described data group to be written, generates the check bit corresponding to described data group to be written and sends to described write buffer; And
Described data group to be written and its corresponding check bit are written in described storage medium by described write buffer.
Preferably, described error detection/correction circuit carries out the step of described error detection/correction process to described ECC code word, comprising:
Described error detection/correction circuit adopts the data group of the check bit of described ECC code word to described ECC code word to carry out described error detection/correction process.
Preferably, described latch, by the corresponding data position in the data group after described input Data Update to described error detection/correction, forms the step of described data group to be written, comprising:
Described latch by the corresponding data position in the data group after described input Data Update to described error detection/correction, forms described data group to be written in units of predetermined length.
Preferably, described latch, by the step of the corresponding data position in the data group after described input Data Update to described error detection/correction, comprising:
Described latch with byte unit by the corresponding data position in the data group after described input Data Update to described error detection/correction.
Preferably, described data group to be written and its corresponding check bit are written to the step in described storage medium by described write buffer, comprising:
Described data group to be written and its corresponding check bit are written in described storage medium with the form of ECC code word by described write buffer.
Preferably, described data group to be written and its corresponding check bit to be written to the step in described storage medium by described write buffer with the form of ECC code word, comprising:
The new ECC code word that described write buffer buffer memory is formed by described data group to be written and its corresponding check bit, and the described new ECC code word identified by flag is written in described storage medium;
Wherein, each described new ECC code word is respectively to having flag, and this flag plays the effect from described write buffer to the write-enable of described storage medium.
Preferably, described write buffer, when the data volume that described new ECC code word is formed exceedes self-capacity, upgrades by the new ECC code word exceeded from start address.
Compared with prior art, embodiments of the invention to achieve in units of ECC code word from storage array read data or write data in storage arrays, effectively reducing the ratio that check bit takies storage array capacity, while saving the area overhead of check bit in storage array, modular structure and control simpler, the characteristic of storer by byte access is not affected while reading and writing data in units of ECC code word, improve the dirigibility of storage and the utilization ratio of storage space, accelerate the speed of data write operation, decrease simultaneously and perform the impact of read-write operation on the serviceable life of storer in units of page.
Other features and advantages of the present invention will be set forth in the following description, and, partly become apparent from instructions, or understand by implementing the present invention.Object of the present invention and other advantages realize by structure specifically noted in instructions, claims and accompanying drawing and obtain.
Accompanying drawing explanation
Accompanying drawing is used to provide a further understanding of the present invention, and forms a part for instructions, together with embodiments of the present invention for explaining the present invention, is not construed as limiting the invention.In the accompanying drawings:
Fig. 1 is the composition schematic diagram of embodiment of the present invention ECC correction verification module;
Fig. 2 is the composition schematic diagram of the data group to be written in the embodiment of the present invention;
Fig. 3 is the schematic flow sheet of the embodiment of the present invention two ECC correction verification module read data;
Fig. 4 is the schematic flow sheet that the embodiment of the present invention three ECC correction verification module writes data.
Embodiment
Describe embodiments of the present invention in detail below with reference to drawings and Examples, to the present invention, how application technology means solve technical matters whereby, and the implementation procedure reaching technique effect can fully understand and implement according to this.
Embodiment one, a kind of error detection/correction (ECC) correction verification module 10, comprise write buffer (Writebuffer) 110, error detection/correction circuit (Decoder_ECC) 120, latch (Latch) 130 and checking circuit (Encoder_ECC) 140, as shown in Figure 1, in the process (being represented by dotted lines data trend in figure) of read data:
Error detection/correction circuit 120, for obtaining the ECC code word in storage array (Main Array) 100, and adopt the check bit in this ECC code word to carry out error detection/correction to the data group (the present embodiment forms with 4 bytes) in this ECC code word, obtain correct data group (the data group hereinafter also referred to after error detection/correction) and send to outside output port 200; ECC code word comprises ECC data group (data set) and check bit;
Outside output port 200 is connected with this error detection/correction circuit 120, and with byte (byte) for unit exports the data group after this error detection/correction (byte output), the output signal in figure illustrates with Dout.
In the present embodiment, this output port 200 is one or four select a MUX, to realize the data group exported in units of byte after the error detection/correction of 32.In other embodiments, output port 200 also can be the data group export error detection/correction in units of other length after, and technical scheme of the present invention exports the data group after error detection/correction be referred to as " part export " by this in units of predetermined length.
In other embodiments, if the byte that data group comprises is other quantity, then can select corresponding MUX according to this quantity, such as a data group comprises 8 bytes, and eight now just can be selected to select a MUX as this output port 200.In a word, when output port 200 selects MUX, the type of this MUX selected, the ratio accounting for data group according to the data length that once can export is determined.
In the present embodiment shown in Fig. 1, an ECC code word has 38 (bit), and comprise data group (ECC data set) and check bit, wherein data group is 32, and check bit is 6.Data group is 1 byte (byte) with 8, has 4 bytes.Below as non-special declaration, in the following each embodiment of the application, 1 data group comprises 4 bytes, and 1 byte packet is containing 8, and corresponding check bit is 6.
Error detection/correction (ECC) correction verification module 10 shown by above-described embodiment, as shown in Figure 1, in the process (representing that data are moved towards with solid line in figure) writing data:
Error detection/correction circuit 120, for obtaining ECC code word according to read operation instruction from storage array (Main Array) 100, error detection/correction process (namely adopting the check bit in this ECC code word to carry out error detection/correction process to the data group in this ECC code word) is carried out to this ECC code word, obtains correct data group (the data group hereinafter referred to as after error detection/correction) and send to latch 130; ECC code word comprises data group (ECC data set) and check bit; Wherein, from storage array 100, obtain the address of this ECC code word according to this read operation instruction, can determine according to the operational order writing data;
Latch 130, be connected with this error detection/correction circuit 120 and an input port 300, for under the control of the first enable signal Load_cd, store the data group after this error detection/correction, and under the control of address signal A [1:0] and the second enable signal Load_din, the input data inputted by this input port 300 are updated to the corresponding data position in the data group after this error detection/correction in units of byte, form data group to be written and send to this write buffer 110 and checking circuit 140; Wherein this address signal A [1:0] determines input data to be written on that byte location of data group, when this first enable signal Load_cd is enable, allows the data group after by error detection/correction to be stored in this latch 130; When this second enable signal Load_din is enable, allow input data to be stored in this latch 130;
Checking circuit 140, is connected with this latch 130, for verifying in real time this data group to be written, generating the check bit corresponding to this data group to be written and sending to this write buffer 110;
Write buffer 110, be connected with this latch 130 and checking circuit 140, for the data group to be written that this latch 130 of buffer memory sends, and the check bit corresponding to this data group to be written that this checking circuit 140 sends, this data group to be written and its corresponding check bit are written in storage array 100 with the form of ECC code word;
Wherein, above-mentioned input port 300, for receiving input data in units of byte, illustrates with Din in figure.In the present embodiment, this input port 300 is in units of byte, receive input data, in other embodiments, input port 300 also can be in units of other length, receive input data, and this input receiving input data in units of predetermined length is referred to as " part input " by technical scheme of the present invention.Above-mentioned latch 130 also can be by the corresponding data position in the data group after input Data Update to this error detection/correction in units of other predetermined length.
As shown in Figure 2, in an embody rule of the present embodiment, this input port 300 have received the external data of a byte, the external data of this byte is written in second byte of the ECC data group after an error detection/correction by latch 130, the ECC data group that such generation one is new, wherein first in this new ECC data group, three and four bytes, for first of the ECC data group after this error detection/correction, three and four bytes (namely read from storage array 100 and treat the byte of write-back), second byte in this new ECC data group, by this input port 300 reception to be written byte.
As shown in Figure 2, in an embody rule of the present embodiment, this input port 300 have received the input data of a byte, the input data of this byte are written in second byte d2 of the data group after an error detection/correction by latch 130, the data group that such generation one is new, wherein first in this new data group, three and four bytes are (respectively with d1 in figure, d3 and d4 illustrates), for first of the data group after this error detection/correction, three and four bytes (namely read from storage array 100 and treat the byte of write-back), second byte in this new data group, by this input port 300 reception to be written byte.
In the present embodiment, because the data groups of 32 need 6 bit check positions, therefore in the present embodiment, this check bit that checking circuit 140 generates is 6.
The method of embodiment two, a kind of error detection/correction (ECC) correction verification module read data, this ECC correction verification module comprises error detection/correction circuit, and as shown in Figure 3, the method mainly comprises the steps:
Step S310, receives the read operation request of user;
Step S320, error detection/correction circuit, according to this read operation request, obtains corresponding ECC code word from storage array (or other storage mediums);
Step S330, error detection/correction circuit adopts the check bit in this ECC code word to carry out error detection/correction process to the data group in this ECC code word, obtains the data group after error detection/correction and sends to outside output port;
Step S340, external output port exports the data group after this error detection/correction in units of byte.
Embodiment three, a kind of error detection/correction (ECC) correction verification module write the method for data, and this ECC correction verification module comprises error detection/correction circuit, latch, checking circuit and write buffer, and as shown in Figure 4, the method comprises:
Step S410, the write operation requests receiving user and the input data that will write;
Step S420, this error detection/correction circuit, according to this write operation requests, obtains corresponding ECC code word from storage array (or other storage mediums);
Step S430, carries out error detection/correction process (namely adopting the check bit in this ECC code word to carry out error detection/correction process to the data group in this ECC code word) to this ECC code word, obtains the data group after error detection/correction and sends to latch;
Step S440, data group after this error detection/correction of this latch stores, by the corresponding data position (byte more corresponding in new data set in units of byte or other predetermined length) in the data group after aforesaid input Data Update to error detection/correction, obtain data group to be written and send to checking circuit and write buffer; This data group to be written namely for being upgraded the new data group that the data group after error detection/correction is formed in units of byte by input data;
Step S450, this checking circuit verifies in real time to data group to be written, generates the check bit corresponding to this data group to be written and sends to write buffer; And
Step S460, this data group to be written and its corresponding (namely being generated by checking circuit) check bit are written in this storage array with the form of ECC code word by this write buffer.
In the present embodiment, these input data, under the effect of address signal A [1:0] and the second enable signal Load_din, are updated to the relevant position in the data group after this error detection/correction by this latch in units of byte, form this data group to be written.
In embodiments of the invention, the capacity of write buffer is general comparatively large, usually consistent with the capacity of page in storage array, can the multiple ECC code word of buffer memory.In write buffer, data group to be written its corresponding (namely being generated by checking circuit) check bit forms new ECC code word together.Each ECC code word (comprising the ECC code word that this is new) in write buffer is to there being a bit-identify position, this flag plays the effect from write buffer to the write-enable storage array, be equivalent to the switch of storage array neutrality line (bitline), represent out when flag is 1 in the present embodiment (can write), when being 0, represent pass (can not write).From write buffer, data are write in storage array, just can directly be undertaken by flag, be about to by the identified ECC code word write storage array of flag, and in units of page, data need not be write in storage array in other words by whole page (page).So, significantly reduce the erasable number of times of the storage array of unchanged data space, avoid frequent erasable storage array, avoid the non-essential life consumption of storage array, make storage array have longer serviceable life.In embodiments of the invention, the width of write buffer is equal with the width of storage array, once can write at most one page (page) data volume.
In embodiments of the invention, perform write operation step, first data are write in write buffer, when being then written in storage array, corresponding operation information comprises: instruction+full address+data (code word), the one page (page) only in corresponding stored array of instruction wherein; Data are no more than one page under normal circumstances, but in order to the demand (such as some data real-time update) that compatibility is different, when the data volume (being formed by some new ECC code words) that write buffer stores exceedes self-capacity (the present embodiment gets one page that write buffer capacity is storage array), the data exceeded (new ECC code word) (may not be minimum or most significant digit) from the start address of write buffer are upgraded former data.
Embodiments of the invention comprise a data group and corresponding check bit with an ECC code word, and data group comprises 4 bytes, a byte be 8bits is that example is described, do not form the restriction to ECC code word or byte, ECC code word specifically comprises how many bytes or a byte packet containing how many bits, and comprising how many data bit and how many check bit in this ECC code word accordingly, the present invention is not limited.
Technical scheme of the present invention, by data volume in units of the ECC code word of page, completes the read-write of data.Technical solution of the present invention is applicable to the nonvolatile memory that external interface carries out data transmission in units of byte, especially EEPROM.Adopt the data bit of some bytes and corresponding check bit to form an ECC code word, and read and write in units of ECC code word, reduce the area overhead of ECC circuit, control also simpler.
When the data of a small amount of byte of storer stochastic inputs (data volume is less than page), memory inside only needs the ECC code word corresponding to those bytes to write, compared with writing data with prior art in units of page, considerably reduce the erasable number of times of storer, effectively extend the serviceable life of storer.
Although the embodiment disclosed by the present invention is as above, the embodiment that described content just adopts for the ease of understanding the present invention, and be not used to limit the present invention.Technician in any the technical field of the invention; under the prerequisite not departing from the spirit and scope disclosed by the present invention; any amendment and change can be done what implement in form and in details; but scope of patent protection of the present invention, the scope that still must define with appending claims is as the criterion.
Claims (8)
1. error detection/correction (ECC) correction verification module, is characterized in that, comprises error detection/correction circuit, latch, checking circuit and write buffer, wherein:
Described error detection/correction circuit, for carrying out error detection/correction process to ECC code word, obtains the data group after error detection/correction;
Described latch, for storing the data group after described error detection/correction, by the corresponding data position in the data group after received input Data Update to described error detection/correction, forms data group to be written;
Described checking circuit, for verifying in real time described data group to be written, generates the check bit corresponding to described data group to be written; And
Described write buffer, for being written in storage medium by described data group to be written and its corresponding check bit;
Wherein, described latch is used in units of predetermined length, receive described input data, by the corresponding data position in the data group after described input Data Update to described error detection/correction in units of predetermined length, forms described data group to be written; Wherein, described latch is used in units of byte, receive described input data, and/or with byte unit by the corresponding data position in the data group after described input Data Update to described error detection/correction;
Described write buffer is used for being written in described storage medium with the form of ECC code word by described data group to be written and its corresponding check bit;
Described write buffer is used for the new ECC code word that buffer memory is formed by described data group to be written and its corresponding check bit, and is written in described storage medium by the described new ECC code word identified by flag;
Wherein, each described new ECC code word is respectively to having flag, and this flag plays the effect from described write buffer to the write-enable of described storage medium.
2. module according to claim 1, is characterized in that:
Described error detection/correction circuit carries out described error detection/correction process for adopting the data group of the check bit of described ECC code word to described ECC code word.
3. module according to claim 1, is characterized in that:
When the data volume that described write buffer is used for being formed in described new ECC code word exceedes self-capacity, upgrade by the new ECC code word exceeded from start address.
4. module according to claim 3, is characterized in that:
The capacity of described write buffer equals the capacity of described storage medium one page.
5. a method for the read data of error detection/correction as claimed in claim 1 (ECC) correction verification module, it is characterized in that, the method comprises:
Receive the read operation request of user;
Described error detection/correction circuit, according to described read operation request, obtains corresponding ECC code word from storage medium;
Described error detection/correction circuit carries out error detection/correction process to described ECC code word, obtains and data group after exporting error detection/correction;
Wherein, export the step of the data group after described error detection/correction, comprising:
The data group after described error detection/correction is exported in units of predetermined length; In units of described predetermined length, export the step of the data group after described error detection/correction, comprising: in units of byte, export the data group after described error detection/correction.
6. the method writing data of error detection/correction as claimed in claim 1 (ECC) correction verification module, it is characterized in that, the method comprises:
The write operation requests receiving user and the input data that will write;
Described error detection/correction circuit obtains corresponding ECC code word according to described write operation requests from storage medium, and carries out error detection/correction process to described ECC code word, obtains the data group after error detection/correction and sends to described latch;
Data group after error detection/correction described in described latch stores, by the corresponding data position in the data group after described input Data Update to described error detection/correction, forms data group to be written and sends to described checking circuit and write buffer;
Described checking circuit verifies in real time to described data group to be written, generates the check bit corresponding to described data group to be written and sends to described write buffer; And
Described data group to be written and its corresponding check bit are written in described storage medium by described write buffer;
Wherein, described latch is by the corresponding data position in the data group after described input Data Update to described error detection/correction, form the step of described data group to be written, comprise: described latch by the corresponding data position in the data group after described input Data Update to described error detection/correction, forms described data group to be written in units of predetermined length; Described latch, by the step of the corresponding data position in the data group after described input Data Update to described error detection/correction, comprising: described latch with byte unit by the corresponding data position in the data group after described input Data Update to described error detection/correction;
Wherein, described data group to be written and its corresponding check bit are written to the step in described storage medium by described write buffer, comprising:
Described data group to be written and its corresponding check bit are written in described storage medium with the form of ECC code word by described write buffer;
Wherein, described data group to be written and its corresponding check bit to be written to the step in described storage medium by described write buffer with the form of ECC code word, comprising:
The new ECC code word that described write buffer buffer memory is formed by described data group to be written and its corresponding check bit, and the described new ECC code word identified by flag is written in described storage medium;
Wherein, each described new ECC code word is respectively to having flag, and this flag plays the effect from described write buffer to the write-enable of described storage medium.
7. method according to claim 6, is characterized in that, described error detection/correction circuit carries out the step of described error detection/correction process to described ECC code word, comprising:
Described error detection/correction circuit adopts the data group of the check bit of described ECC code word to described ECC code word to carry out described error detection/correction process.
8. method according to claim 6, is characterized in that:
When the data volume that the described new ECC code word of described write buffer reception is formed exceedes self-capacity, upgrade by the new ECC code word exceeded from start address.
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| CN102831028B (en) * | 2012-09-07 | 2016-01-20 | 苏州国芯科技有限公司 | Based on ECC error correction method and the system of data bus |
| CN103631669B (en) * | 2013-12-03 | 2016-06-22 | 中国科学院微电子研究所 | A kind of write-back method of error correction SRAM |
| CN105023616A (en) * | 2014-04-30 | 2015-11-04 | 深圳市中兴微电子技术有限公司 | Method for storing and retrieving data based on Hamming code and integrated random access memory |
| KR102662417B1 (en) * | 2017-01-11 | 2024-04-30 | 에스케이하이닉스 주식회사 | Semiconductor device |
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