CN102339255B - Nand writing balance processing method - Google Patents
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Abstract
The invention discloses a Nand writing balance processing method which comprises the following operating processes: (1) a certain logic block is in a buffer state, the logic block corresponds to two physical blocks, wherein the first physical block is used as an old data block to be read in firstly; a page mapping relationship between the logic block and the first physical block is one-to-one mapping; the second physical block is used as a buffer block to be read in later, and a page mapping relationship between the logic block and the second physical block is random mapping; (2) according to a write buffer algorithm, the page mapping relationship is established; (3) in the write operation process of the physical blocks, if the buffer block which corresponds to the physical block is overwritten, the housekeeping operation process is triggered; the write operation on the physical operation is finished; meanwhile, the corresponding relationship between the logic block and the buffer block is released. According to the Nand writing balance processing method, the two algorithms of page mapping and block mapping are combined so that the high efficiency of read-write performance is ensured while the occupied memory is substantially reduced.
Description
Technical field
The present invention relates to a kind of Nand and write Balance Treatment method.
Background technology
A Nand Flash chip is comprised of many (Block), a piece is comprised of a lot of pages (Page) again, each piece or page have certain erasable number of times, and therefore, prolongation Nand Flash serviceable life, the simplest way was write balance exactly.Write balance, english is Wear-leveling, manages to make each piece to have identical erasing times, every page and all has the identical indegree of writing.Therefore, the sector of file system will be mapped in different Physical Page in a certain way.Writing balanced algorithm is a kind of basic research topic, and wherein most important content is mapping relations.Follow according to mapping relations, the current popular balanced algorithm of writing can be divided into two classes: page mapping and piece mapping.
Page mapping algorithm: by an array in internal memory, set up page and the relation of penetrating of sector.While searching certain sector, by this array, find corresponding page.Random Maps is also in this mapping of being changed by array.When certain sector, again write fashionablely, need to change the content of mapping array, meanwhile, page originally should reclaim as invalid page.The shortcoming of such algorithm is that EMS memory occupation is large, needs idle arrangement simultaneously, when writing continuously, due to not free, arranges, and can cause writing slower and slower.
Piece mapping algorithm: the physical block in Nand Flash and the logical block of file system are set up mapping relations.Owing to being piece mapping, the array length in internal memory reduces greatly, and EMS memory occupation reduces.But the page in piece must be corresponding one by one, this relation that there is no array conversion is also named mapping one by one.Therefore, when certain sector is upgraded, the whole physical block of its correspondence will be upgraded simultaneously, and readwrite performance relatively also reduces greatly.
Summary of the invention
The object of the present invention is to provide a kind of Nand to write Balance Treatment method, the method combines page mapping and two kinds of algorithms of piece mapping simultaneously, can be when reducing EMS memory occupation energetically, guarantee again the efficient of readwrite performance.
Object of the present invention can realize by following technical measures:
A kind of Nand writes Balance Treatment method, comprises write operation process:
(1) by a certain logical block in writing buffer status: corresponding two physical blocks of described logical block, first physical block is first written into as old data block, the page mapping relations of this logical block and first physical block are to shine upon one by one; Second physical block writes after as buffer stopper, and the page mapping relations of this logical block and second physical block are Random Maps;
(2), according to writing buffer algorithm, set up page mapping relations;
(3) in the write operation process to physical block, full if the corresponding buffer stopper of this physical block has been write, trigger housekeeping operation process, and finish the write operation to this physical block, discharge the corresponding relation of this logical block to described buffer stopper simultaneously.
The buffer algorithm of writing in described step (2) adopts the conventional buffer algorithm of writing.
The process of setting up page mapping relations in described step (2) is: the data in the sector that will write sequentially write certain page of buffer stopper, and according to the numbering refresh page mapping array of the numbering of sector and page.
In described step (1), also comprise before initialization procedure: the internal memory that allocation block mapping array is required with page mapping array; All physical blocks of scan N and chip, upgrade piece mapping array.
The housekeeping operation process of described step (3) is: to the logical block in writing buffer status, the data of data block and buffer stopper are merged in new physical block; The page mapping relations of described logical block are converted into mapping one by one by Random Maps.
Described Nand writes Balance Treatment method and also comprises read operation process: when system need to be read certain sector, calculate the logical block number (LBN) that need to read; According to the piece mapping array after initialization, find the corresponding physical block of the logical block that will read; If this logical block is being write buffer status,, according to its page mapping array, find corresponding page, otherwise directly calculate corresponding Physical Page, and read this Physical Page.
The computing method of described logical block number (LBN) are: the number of pages of logical block number (LBN)=sector number/every.
The described formula that calculates corresponding Physical Page is: the skew of number of pages+sector number that the physical block * of Physical Page=correspondence is every in piece.
Nand of the present invention writes Balance Treatment method by piece mapping and the ingenious combination of page mapping algorithm, when read operation, adopts piece mapping algorithm, when local write operation, and the page mapping algorithm of employing, therefore the advantage of the inventive method is:
1, EMS memory occupation amount aspect: with piece mapping class seemingly, mapping array length is the number of blocks of Nand Flash, rather than number of pages, therefore, this method internal memory more shared than page mapping algorithm is little, has the EMS memory occupation amount of a small amount of that piece mapping algorithm has;
2, read aspect of performance: piece shines upon chain type sometimes searches page corresponding to certain sector, and this method is similar with page mapping algorithm, directly by array, searches, therefore than piece mapping algorithm to read performance high, there is the high-performance of page mapping algorithm;
3, when writing large file: because sector writes continuously, arrangement can be optimised: one in writing the logical block of buffer status, although page mapping is random, but large file writes and often makes it to meet mapping condition one by one, at this moment only need to delete old data block, and buffer stopper directly changes new data block into;
4, when writing small documents: for certain sector that will write, when carrying out write operation, write and once arrived buffer stopper; When carrying out housekeeping operation, write again and once arrived new data block.Only that is to say write once, therefore can to estimate be 1 times in peak performance loss more; Simple piece mapping algorithm or page mapping algorithm may be write N time more, and peak performance loss is N-1 times;
5, this method is triggered in real time and is arranged by write operation, writes while arranges, and does not write continuously and the difference that writes intermittence.But first two algorithm needs idle housekeeping operation to carry out covert improving performance, write while the actual efficiency that arranges is lower.Idle arrangement needs multithreading support, increased size of code and memory cost simultaneously.
Accompanying drawing explanation
Fig. 1 is the process flow diagram that Nand of the present invention writes the write operation process of Balance Treatment method;
Fig. 2 is that general Mapping and Converting is related to schematic diagram;
Fig. 3 is the mapping relations of the piece that writing;
Fig. 4 is the transformational relation schematic diagram of the arrangement process of the inventive method.
Embodiment
Virtual machine and simulator technology have improved the efficiency of software development greatly, simultaneously can a large amount of hardware of emulation non-existent hardware in reality even.This method is by being used simulator technology, the Nand Flash chip of emulation different size, the integrality of verification algorithm; Then this method is transplanted in WinCE operating system, in real hardware environment operation, test and validation the practical value of algorithm.To be introduced above-mentioned two kinds of embodiments below.The object of introducing simulator embodiment is calculation ratio juris is more clearly described, and introduces real hardware embodiment in order to prove practicality and the beneficial effect of this method.
Embodiment one: simulator embodiment
Simulated environment is: the total block data of Nand Flash is 8, every 4 pages, and every page of 2K byte; Write buffer stopper and have 2 physical blocks; Piece is to number 0 beginning, and in piece, homepage numbering is also 0.
Initialization operation process is as follows:
1) distribute 1 piece mapping array and 2 page mapping array internal memories used.
2) all physical blocks of scan N and chip, upgrade piece mapping array, reproduction blocks mapping relations, and possible mapping relations are as Fig. 2.
3) for buffer stopper, scan every one page, refresh page mapping array, reappears page mapping relations, and possible mapping relations are as Fig. 3.
During read operation, adopt Mapping and Converting as shown in Figure 2.Suppose and will read 17 sectors, calculate logical block corresponding to this sector: the number of pages that logical block number=sector number/Nand chip is every, under this environment is: page every, 17 sector/4, owing to 17 being 1 divided by 4 remainders, after rounding, be the 4th logical block, piece bias internal is 1.In the piece mapping array of setting up when initialization, the physical block that can find the 4th logical block mapping is 6.Then, calculating page corresponding to the 17th sector is: every+piece of physical block 6*4 page bias internal 1, the 25th page.
During read operation, run into logical block corresponding to the sector that will read in writing buffer status.As shown in Figure 3, in piece mapping array, grey block represents to write, and points to a page map table, while reading the 17th sector, although piece mapping array still points to 6, but this logical block is in writing buffer status, then find the page mapping array of the 4th logical block, because the piece bias internal of the 17th sector is 1, therefore search array indexing and be 1 element value, so learn the mapping page array of the 17th sector be 29,29 divided by 4 round 7, it belongs to the 7th physical block.
Housekeeping operation process is as shown in Figure 4: for logical block 4, due to its, process and write buffer status, therefore it has a page mapping array.By page, shine upon array, arrangement process has been incorporated into old data block and buffer stopper in certain blank block, and this blank block becomes new data block.Old data block and buffering are recovered as blank block simultaneously.Carefully analyzing page mapping array can find, page mapping array has been pointed to two physical blocks: physical block 6 and physical block 7; Physical block 6 is old data blocks, and it shines upon one by one; Physical block 7 is buffer stoppers, and it is Random Maps.As for new data block, be which blank block, unimportant.This method is in order to reach erasable balance, and searching of blank block used to sequential search method, and in fact the method is the most simply and the most effective.
Embodiment two: real hardware embodiment
In WinCE operating system, realized this method.As the example of product quality level, this method is made as 16 or higher by buffer stopper quantity, has added power down process and dynamic bad block management, and has done a large amount of optimization.The various operating process of this example are as follows:
1) initialization operation:
A) allocation block mapping array and N page mapping array internal memory used.
B) all physical blocks of scan N and chip, upgrade piece mapping array, reproduction blocks mapping relations.
C) to buffer stopper, scan every one page, refresh page mapping array, reappears page mapping relations.
2) read sector operation:
A) calculate logical block.
B) according to piece mapping array, find corresponding physical block.
If c) this logical block is being write buffer status,, according to its page mapping array, find corresponding page, otherwise directly calculate corresponding page (seeing specific embodiment 1, accompanying drawing 2).
D) then read this page.
3) write sector operation: idiographic flow is shown in accompanying drawing 1, concise and to the point function is as follows:
A) write operation makes certain logical block processing write buffer status, i.e. corresponding two physical blocks of this logical block, and a physical block is first written into, i.e. old data block, page mapping relations are mapping one by one; And write after another physical block, i.e. buffer stopper, page mapping relations are Random Maps.The corresponding page mapping of this logical block array;
B) by writing buffer algorithm, set up page mapping relations, as accompanying drawing 1, the sector that will write order writes buffer stopper page, now according to this sector number with write a page number change page mapping array;
C) if desired, under condition, trigger housekeeping operation process as shown in Figure 1, therefore the buffer status of writing of certain logical block finishes.
4) housekeeping operation: to the logical block in writing buffer status, two physical block is integrated into new physical block, and old data block and buffer stopper are integrated into new data block.Referring to accompanying drawing 4, at this moment, the page mapping relations of this logical block are converted into mapping one by one by Random Maps.
The process merging is exactly the arrangement process of data: for same logical page (LPAGE), may there be one or more Physical Page, as there being a Physical Page in old physical block, and in new physical block, there are one or more Physical Page, in these Physical Page, only have the Physical Page finally writing to be only effectively.Arrangement process copies to the Physical Page finally writing in a new blank block, and owing to having deleted invalid page, therefore two physical blocks can merge to a new physical block, in merging process, guarantees to be mapped as mapping one by one.
FAL algorithm (the FlashAbstract Level of WinCE itself, Chinese meaning: Flash level of abstraction) based on page, shine upon, the Nand Flash of 1G (containing 4K piece, 512K page) is carried out to contrast test with this algorithm, wherein FAL does not support the large capacity Nand of MLC and so on originally, and the FAL is here improved.The FAL algorithm of WinCE and the Data Comparison analytical table of the inventive method are as follows:
Embodiments of the present invention are not limited to this; under the above-mentioned basic fundamental thought of the present invention prerequisite; modification, replacement or the change to other various ways that content of the present invention is made according to the ordinary skill knowledge of this area and customary means, within all dropping on rights protection scope of the present invention.
Claims (6)
1. Nand writes a Balance Treatment method, comprises write operation process, it is characterized in that:
(1) by a certain logical block in writing buffer status: corresponding two physical blocks of described logical block, first physical block is first written into as old data block, the page mapping relations of this logical block and first physical block are to shine upon one by one; Second physical block writes after as buffer stopper, and the page mapping relations of this logical block and second physical block are Random Maps;
(2), according to writing buffer algorithm, set up page mapping relations;
(3) in the write operation process to physical block, full if the corresponding buffer stopper of this physical block has been write, trigger housekeeping operation process, and finish the write operation to this physical block, discharge the corresponding relation of described logical block and described buffer stopper simultaneously;
The process of setting up page mapping relations in described step (2) is: the data in the sector that will write sequentially write certain page of buffer stopper, and according to the numbering refresh page mapping array of the numbering of sector and page;
The housekeeping operation process of described step (3) is: to the logical block in writing buffer status, the data of data block and buffer stopper are merged in new physical block; The page mapping relations of described logical block are converted into mapping one by one by Random Maps.
2. Nand according to claim 1 writes Balance Treatment method, it is characterized in that: the buffer algorithm of writing in described step (2) adopts the conventional buffer algorithm of writing.
3. Nand according to claim 1 writes Balance Treatment method, it is characterized in that: in described step (1), also comprise before initialization procedure: the internal memory that allocation block mapping array is required with page mapping array; All physical blocks of scan N and chip, upgrade piece mapping array.
4. Nand according to claim 3 writes Balance Treatment method, it is characterized in that: described Nand writes Balance Treatment method and also comprises read operation process: when system need to be read certain sector, calculate the logical block number (LBN) that need to read; According to the piece mapping array after initialization, find the corresponding physical block of the logical block that will read; If this logical block is being write buffer status,, according to its page mapping array, find corresponding page, otherwise directly calculate corresponding Physical Page, and read this Physical Page.
5. Nand according to claim 4 writes Balance Treatment method, it is characterized in that: the computing method of described logical block number (LBN) are: the number of pages of logical block number (LBN)=sector number/every.
6. Nand according to claim 4 writes Balance Treatment method, it is characterized in that: described in calculate corresponding Physical Page formula be: the skew of number of pages+sector number that the physical block * of Physical Page=correspondence is every in piece.
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| CN103970674B (en) * | 2013-01-30 | 2017-04-05 | 安凯(广州)微电子技术有限公司 | A kind of physical block wiring method and system |
| CN103970483B (en) * | 2013-01-30 | 2017-05-31 | 安凯(广州)微电子技术有限公司 | A kind of physical block wiring method and system |
| CN103995783B (en) * | 2013-02-20 | 2017-08-25 | 安凯(广州)微电子技术有限公司 | A kind of method and system for setting up logical block and physical block mapping relations |
| CN107092563B (en) * | 2017-04-20 | 2021-02-26 | 新华三信息技术有限公司 | Garbage recovery method and device |
| CN107632941A (en) * | 2017-08-16 | 2018-01-26 | 南京扬贺扬微电子科技有限公司 | A kind of method for improving flash memory write performance |
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| CN1828555A (en) * | 2005-02-07 | 2006-09-06 | 三星电子株式会社 | Flash memory control devices that support multiple memory mapping schemes and methods of operating same |
| CN101075211A (en) * | 2007-06-08 | 2007-11-21 | 马彩艳 | Flash memory management based on sector access |
| CN101241472A (en) * | 2008-03-07 | 2008-08-13 | 威盛电子股份有限公司 | Mapping management process and system |
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| CN1828555A (en) * | 2005-02-07 | 2006-09-06 | 三星电子株式会社 | Flash memory control devices that support multiple memory mapping schemes and methods of operating same |
| CN101075211A (en) * | 2007-06-08 | 2007-11-21 | 马彩艳 | Flash memory management based on sector access |
| CN101241472A (en) * | 2008-03-07 | 2008-08-13 | 威盛电子股份有限公司 | Mapping management process and system |
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