CN102298562A

CN102298562A - Method, device and system for interconnecting line and arbitration bus

Info

Publication number: CN102298562A
Application number: CN2011101039927A
Authority: CN
Inventors: 王记锋
Original assignee: Huawei Technologies Co Ltd
Current assignee: Huawei Technologies Co Ltd
Priority date: 2008-08-15
Filing date: 2008-08-15
Publication date: 2011-12-28

Abstract

The embodiment of the invention discloses a method, device and system for interconnecting a line and an arbitration bus. The device comprises a circuit-mode controller and a logic multiple input AND gate, wherein, the circuit-mode controller is used for controlling the circuit to carry out switch between the normal mode and the self-test mode; and when the circuit works in the self-test mode, logic and operation are carried out by the logic multiple input AND gate on the output signals, the operation result is output, and the line and arbitration bus interconnection can be realized for the circuit. By utilizing the method, device and system provided by the embodiment of the invention, collocation and interconnection of the line and an arbitration device in a chip are realized, and the separation of the device on the bus and the bus can be controlled through the logic multiple input AND gate.

Description

The methods, devices and systems that a kind of line and arbitration bus are interconnected

Technical field

The embodiment of the invention relates to the communications field, relates in particular to the interconnected methods, devices and systems of a kind of line and arbitration bus.

Background technology

Line and arbitration bus are a kind of many simply and easily host bus systems.Be widely used in I2C (The Inter-Integrated Circuit, a kind of serial bus protocol standard), CAN multi-host systems such as (ControllerArea Network, controller local area networks).This technology is utilized the line and the characteristic of single line, has solved the arbitration problem when bus drives more.

Prior art is used and is opened fistulae pin or ternary pin realization line and characteristic.Bus with I2C is connected to the example explanation below.Among Fig. 1 11 and 12 is respectively two I2C devices that are connected on online and the arbitration bus, also can connect more.Arbitration bus comprises SDA (Serial Data Line, serial data line) and SCL (serial time clock line).The I2C device is connected with bus by the two-way fistulae pin 13 of opening.SCL1_OUT and SDA1_OUT are the signal of I2C 1 to bus output, and SCL1_IN and SDA1_IN are the signals that I2C 1 imports from bus.I2C 2 is also similar.

Pin one 3 is one and opens the Lou two-way pin of output, opening Lou, output pin can only drive low level output, can't drive high level output, outside need adds and draws resistance 14, that is: when SCL1_OUT is low level, pin one 3 is opened CMOS (Complementary Metal-Oxide Semiconductor, complementary matal-oxide semiconductor) pipe conducting leakage, and bus SCL is driven to low level; When SCL1_OUT is high level, open leakage the CMOS pipe by, output high resistant, this moment bus under the effect of pull-up resistor 14, keep high level, the input of two-way pin is used to the bus state of sampling.

Because there are a plurality of devices to be connected to bus simultaneously, output signal, for example SCL1_OUT or SCL2_OUT, the device of output high level can not influence bus level.As long as any device has been exported low level on the bus, final bus will keep low level, i.e. line and function: SCL=SCL1_OUT﹠amp; SCL2_OUT, SDA=SDA_OUT1﹠amp; SDA_OUT2.

The real-time testbus SCL of input signal SCL1_IN, SDA1_IN of I2C 1, the state of SDA.According to the pattern difference that I2C is in, two purposes are arranged: when I2C 1 is in accepting state, can obtain the data that other device sends; When I2C 1 is in transmit status, is used for arbitration and judges.If inconsistent from the signal that the signal and the SDA1_OUT of SDA1_IN input sends, show that then other device is using bus, 1 of I2C interrupts this time sending, and loses arbitration.For example: if I2C1 and I2C 2 send simultaneously, SDA1_OUT exports high level, while SDA2_OUT output low level, and according to line and characteristic, this moment, bus state kept low level.SDA1_IN and SDA2_IN also are low level.I2C 1 back finds relatively that according to SDA1_OUT and SDA1_IN the high level that oneself sends does not appear on the bus, sends and gets nowhere, and then interrupts automatically this time sending, and loses arbitration.I2C 2 will continue to send this moment, and can not be affected.

Along with the increase of ASIC (Application Specific Integrated Circuit, Application Specific Integrated Circuit) integrated level, lines such as multipath I 2 C or CAN and arbitration type bus in same chip, can have been realized.In order to improve the self-testing capability of chip, need realize that sheet is reached the standard grade and arbitration bus interconnects at chip internal.

In implementing process of the present invention, the inventor finds to exist at least in the prior art following shortcoming:

Because pull-up resistor, open with Louing, the problem of implementation of bidirectional bus, line recited above and interconnect scheme can't be integrated in chip, and can't Configuration Online after the bus connection, so can't realize the controlled isolation of device and bus on the bus.

Summary of the invention

The embodiment of the invention provides a kind of line and the interconnected methods, devices and systems of arbitration bus, to be implemented in the controlled isolation that chip internal carries out device and bus on the interconnection of line and arbitration bus and the bus.

The embodiment of the invention also provides the device of a kind of line and arbitration bus interconnection, comprising:

Pin, line and arbitration bus, many inputs of logic and door;

The signal that described line that described pin will receive and arbitration bus send sends to many inputs of described logic and door, the many inputs of described logic are carried out logic and operation with door to described signal, and the result of logic and operation is sent to described line and arbitration bus by described pin.

The embodiment of the invention also provides a kind of line and the interconnected method of arbitration bus, comprising:

Receive the signal that line and arbitration bus send;

Send described signal to many inputs of logic and door;

Receive the logic and operation result of many inputs of described logic and door;

Send described logic and operation result to described line and arbitration bus.

The methods, devices and systems that the embodiment of the invention provides by many inputs of logic and door, are realized configurable interconnected in chip of line and arbitration device, and the isolation of device and bus on can control bus.

Description of drawings

In order to be illustrated more clearly in the embodiment of the invention or technical scheme of the prior art, to do to introduce simply to the accompanying drawing of required use in embodiment or the description of the Prior Art below, apparently, accompanying drawing in describing below only is some embodiments of the present invention, for those of ordinary skills, under the prerequisite of not paying creative work, can also obtain other accompanying drawing according to these accompanying drawings.

Fig. 1 is the interconnection circuit synoptic diagram of prior art center line and arbitration bus;

The structural representation of the many inputs of logic and door in the device that Fig. 2 provides for the embodiment of the invention;

The circuit diagram of the device that Fig. 3 provides for the embodiment of the invention;

The schematic flow sheet of the method that Fig. 4 provides for the embodiment of the invention;

The circuit diagram of the device that Fig. 5 provides for the embodiment of the invention;

The structural representation of pin in the device that Fig. 6 provides for the embodiment of the invention;

The schematic flow sheet of the method that Fig. 7 provides for the embodiment of the invention;

The structural representation of the system that Fig. 8 provides for the embodiment of the invention.

Embodiment

Below in conjunction with the accompanying drawing in the embodiment of the invention, the technical scheme in the embodiment of the invention is clearly and completely described, obviously, described embodiment only is the present invention's part embodiment, rather than whole embodiment.Based on the embodiment among the present invention, those of ordinary skills belong to the scope of protection of the invention not making the every other embodiment that is obtained under the creative work prerequisite.

Below in conjunction with drawings and Examples the present invention is introduced.

The embodiment of the invention provides the device of a kind of line and arbitration bus interconnection, comprising:

The circuit-mode controller, many inputs of logic and door;

Wherein, the circuit-mode controller is used for control circuit and switches between normal mode and self-testing mode;

The many inputs of logic are used for circuit working when self-testing mode with door, and output signal is carried out logic and operation, and the output operation result, make circuit realize line and arbitration.

The structure of many inputs of above-mentioned logic and door comprises as shown in Figure 2:

Receiving element 210 is used to receive the output end signal of primary controller or pin;

Arithmetic element 220 is used for the signal that receiving element 210 receives is carried out logic and operation;

Output unit 230 is used to export the logic and operation result of arithmetic element 220.

By the device that adopts the embodiment of the invention to provide, use circuit-mode controller and logic are imported the logical circuit with door more, and line and arbitration bus that compositing chip is interior are conveniently tested circuit in the chip.

Below in conjunction with concrete application scenarios the present invention is further introduced.Wherein, primary controller is an example with I2C1, I2C2, and signal is with SCL1_OUT, SCL1_IN, SDA1_OUT, SDA1_IN, and the input and output signal that is I2C1 is an example; SCL2_OUT, SCL2_IN, SDA2_OUT, SDA2_IN, the input and output signal that is I2C2 is an example; Pin is an example with the two-way fistulae pin of opening; The circuit-mode controller comprises input signal LP_EN and MUX.

The embodiment of the invention provides the device of a kind of line and arbitration bus interconnection, as shown in Figure 3, comprising:

I2C1, I2C2, the two-way fistulae pin 33 of opening,

MUX

34,35, bus SDA, SCL, LP_EN 36, the many inputs of logic and door 31 and trigger 32.

Wherein, LP_EN 36 and MUX 34,35 forming circuit mode controllers, when LP_EN 36 is high level, the signal of corresponding port " 1 " is by MUX 34,35, circuit working is at self-testing mode, this moment, I2C1 and I2C2 and external bus were isolated, and realized that by the present invention the chip internal bus connects; When LP_EN 36 was low level, the signal of corresponding port " 0 " was by MUX 34,35, and circuit working is at normal mode, and I2C1 is connected with external bus SDA, SCL by the two-way fistulae pin 33 of opening with I2C2.

It is high level that the many inputs of logic are used at LP_EN36 with door 31, and circuit working receives the multi-channel output signal when self-testing mode, output end signal is carried out logic and operation, realizes sending the line and the function of signal wire; And the result of logic and operation outputed to signal receiving end, the monitoring that is used to arbitrate is judged, realizes arbitration.

Trigger 32 is used to interrupt the feedback loop of combinational logic, is beneficial to carry out time series analysis when ASIC designs.

The two-way fistulae pin 33 of opening, being used at LP_EN36 is low level, circuit working when normal mode, output I2C1, the signal of I2C2 is to line and arbitration bus SDA, SCL, and the signal that returns of reception line and arbitration bus SDA, SCL; The two-way fistulae pin 33 of opening is out to leak the two-way pin of exporting, and can only drive low level output, can't drive high level output, for example: when SCL1_OUT is low level, the pin conducting; When SCL1_OUT is high level, pin by, the input of two-way pin is used to the bus state of sampling.

SDA and SCL are line and arbitration bus.

When LP_EN 36 is low level, circuit working is at normal mode, SCL1_OUT, SCL2_OUT, SDA1_OUT, SDA2_OUT pass through corresponding pin to bus SDA and SCL output signal, SCL1_IN, SCL2_IN, SDA1_IN, SDA2_IN then receive the signal that bus sends from the pin of correspondence, this moment I2C 1 and I2C 2 by separately pin and the bus SCL of outside be connected realization line and arbitration function with SDA.

When LP_EN 36 was high level, circuit working was at self-testing mode, and SCL1_OUT, SCL2_OUT, SDA1_OUT, SDA2_OUT disconnect at

MUX

34,35 places, do not export by pin; SCL1_IN, SCL2_IN, SDA1_IN, SDA2_IN also isolate with external terminal 33; This moment, I2C 1, I2C 2 and outside bus were isolated.Above-mentioned output end signal SCL1_OUT, SCL2_OUT, SDA1_OUT, SDA2_OUT carry out logic and operation by the many inputs of logic with door 31, realize sending the line and the function of signal, for example: when SCL1_OUT be low level, when SCL2_OUT is high level, line with after the result be the output low level signal; When the both is low level signal, the output low level signal; When having only the both to be high level signal, just export high level signal.Output behind logic and operation a and b as a result promptly is end-state on the bus.The a as a result of Xiang Yuhou and b are connected to data receiver SCL1_IN and SCL2_IN, SDA1_IN and SDA2_IN respectively, and receiving end is used for monitoring bus state or receiving data according to the signal that receives.In receiving course, be used for receiving data; Monitor bus state in process of transmitting if the state of bus state and oneself transmission is inconsistent, is then lost arbitration, discharges bus.

For example: suppose that I2C 1 sends sequence 00101100 since moment t at SDA1_OUT; I2C 2 sends sequence 00111001 since moment t at SDA2_OUT.Sequence is output synchronously successively from left to right.According to the characteristic of logical and, it is 00101000 that signal wire a goes up the sequence that begins to occur constantly from t.When sending, I2C 1 receives bus (signal state a) by SDA1_IN; I2C 2 receives the state of bus by SDA2_IN.At preceding 3 that send sequence, the data of signal a, SDA1_OUT output, SDA2_OUT output are consistent, all are " 001 ".When the 4th of transmission sequence, bus state is " 0 ".I2C 1 is the data consistent of " 0 " and oneself transmission by the state that SDA1_IN detects on the bus, and I2C 1 will continue to send; I2C 2 is inconsistent by the data that SDA2_IN detects bus state and oneself transmission, and this shows has miscellaneous equipment also using bus, and I2C 2 loses arbitration with initiatively stopping the transmission of back data, sends high level, discharges bus.Appear at finally on the bus that (signal sequence a) is 00101100, and the sequence that sends with I2C 1 is consistent.Line and arbitration bus have so just been realized.

The embodiment of the invention provides a kind of line and the interconnected method of arbitration bus, as shown in Figure 4, comprising:

Step s410 when the circuit-mode controller controling circuit is operated in self-testing mode, receives the output end signal of primary controller;

Step s420 carries out logic and operation to the output end signal of primary controller;

Step s430, output logic and calculated result make primary controller arbitrate according to the result who receives.

By the method that adopts the embodiment of the invention to provide, use circuit-mode controller and logic are imported the logical circuit with door more, and line and arbitration bus that compositing chip is interior are conveniently tested circuit in the chip.

The embodiment of the invention also provides a kind of line and the interconnected device of arbitration bus, comprising:

Pin, at least two buses, many inputs of logic and door;

Pin is used to receive the signal that bus sends, by the logic and operation of the many inputs of logic with door, the received signal of control bus.

As shown in Figure 5, pin is an example with the two-way fistulae pin of opening, and bus is an example with the double bus under VDD1, the VDD2, comprising: the two-

way fistulae pin

52,53 of opening, line and

arbitration bus

54,55, many inputs of logic and door 51.

The two-

way fistulae pin

52,53 of opening is used for line and arbitration bus are changed into transmission, receive two signals, handles with DLC (digital logic circuit) with convenient; Transmission, received signal after perhaps will handling change line and arbitration bus once more into.54,55 is respectively bus, between the double bus through two-way

open fistulae pin

52,53 after, interconnected by the many inputs of logic with door 51.

The signal that sends from bus 54 through two-way input buffering of opening fistulae pin 52 after and the transmission signal of bidirectional bus 55 carry out logic and operation by the many inputs of logic with door 51, signal behind the logic and operation is used to control the output of

52 and 53, therefore the signal on the

bus

54,55 be

bus

54,55 lines and the result, promptly realized line and function.

On to draw level VDD1, VDD2 can be different voltage, the device of suitable different voltages correspondence respectively is connected on 54 and 55, computing by logical and can not have influence on the voltage on original VDD1, the VDD2, and the result behind the logical and controls the output of

52 and 53, plays the effect of isolating different voltages.

Also can control two-way signal output of opening the fistulae pin, isolate different bus zones by many inputs of steering logic and door to bus 54 and 55.For example, control and two-wayly open fistulae pin output and end, just can realize isolating the signal of

bus

54,55, the different bus zone is independent of each other.

The structure of above-mentioned pin comprises as shown in Figure 6:

Signal receiving unit 610 is used to receive two wires and the signal of arbitration bus transmission or the operation result of many inputs of logic and door at least;

Signal transmitting unit 620 is used to transmit a signal to the many inputs of logic and door or two wires and arbitration bus at least.

By the device that adopts the embodiment of the invention to provide, use pin, at least two buses, many inputs of logic and door can promote the bus driver ability, realize configurable interconnected in chip of line and arbitration device, and the isolation of device and bus on can control bus.

The embodiment of the invention also provides a kind of line and the interconnected method of arbitration bus, as shown in Figure 7, comprising:

Step s710 receives the signal that line and arbitration bus send;

Step s720 sends above-mentioned signal to many inputs of logic and door;

Step s730, the logic and operation result of many inputs of receive logic and door;

Step s740 sends described logic and operation result to described line and arbitration bus.

Method by adopting the embodiment of the invention to provide can promote the bus driver ability, realizes configurable interconnected in chip of line and arbitration device, and the isolation of device and bus on can control bus.

The embodiment of the invention also provides the system of a kind of line and arbitration bus interconnection, as shown in Figure 8, comprising:

The many inputs of logic and door 81, primary controller 82, line and arbitration bus 83 and pin 84;

The many inputs of logic and door 81 receive the signal that primary controller 82 sends and carry out logic and operation under the circuit self-testing mode, and the result who sends logic and operation is to primary controller 82; Or

The many inputs of logic receive line with door 81 and arbitration bus 83 carries out logic and operation by the signal that pin 84 sends, and send the result of logic and operation to line and arbitration bus 83 by pin 84.

Said system also comprises:

Circuit-mode controller 85 is used for the mode of operation of control circuit, comprises normal mode and self-testing mode.

System by adopting the embodiment of the invention to provide uses simple logical circuit, realizes configurable interconnected in chip of line and arbitration device, and the isolation of device and bus on can control bus.

Through the above description of the embodiments, those skilled in the art can be well understood to the present invention and can realize by hardware, also can realize by the mode that software adds necessary general hardware platform.Based on such understanding, technical scheme of the present invention can embody with the form of software product, it (can be CD-ROM that this software product can be stored in a non-volatile memory medium, USB flash disk, portable hard drive etc.) in, comprise some instructions with so that computer equipment (can be personal computer, server, the perhaps network equipment etc.) carry out the described method of each embodiment of the present invention.

In a word, the above is preferred embodiment of the present invention only, is not to be used to limit protection scope of the present invention.Within the spirit and principles in the present invention all, any modification of being done, be equal to replacement, improvement etc., all should be included within protection scope of the present invention.

Claims

1. the device of line and arbitration bus interconnection is characterized in that, comprising:

Pin, line and arbitration bus, many inputs of logic and door;

2. device as claimed in claim 1 is characterized in that, the many inputs of described logic comprise with door:

Receiving element is used to receive the signal that described pin sends;

Arithmetic element is used for the signal that described receiving element receives is carried out logic and operation;

Output unit is used to export the logic and operation result of described arithmetic element.

3. device as claimed in claim 1 is characterized in that, described pin comprises:

Signal receiving unit is used to receive the signal of described line and arbitration bus transmission or described logic is imported more and the logic and operation result of door;

Signal transmitting unit is used to transmit a signal to the many inputs of described logic and door or described line and arbitration bus.

4. line and the interconnected method of arbitration bus is characterized in that, comprising:

Receive the signal that line and arbitration bus send;

Send described signal to many inputs of logic and door;

5. method as claimed in claim 4 is characterized in that, the many inputs of the described logic of described reception also comprise with the logic and operation result of door before:

The many inputs of described logic are carried out logic and operation with door to described signal.