CN102290399B - Stacking type chip packaging structure and method - Google Patents

Stacking type chip packaging structure and method Download PDF

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Publication number
CN102290399B
CN102290399B CN 201010201997 CN201010201997A CN102290399B CN 102290399 B CN102290399 B CN 102290399B CN 201010201997 CN201010201997 CN 201010201997 CN 201010201997 A CN201010201997 A CN 201010201997A CN 102290399 B CN102290399 B CN 102290399B
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China
Prior art keywords
chip
substrate
pin
depressed part
resettlement section
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CN 201010201997
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Chinese (zh)
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CN102290399A (en
Inventor
肖俊义
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- Core Of Electronic Science And Technology (zhongshan) Co Ltd
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AMBIT ELECTRONICS (ZHONGSHAN) Co Ltd
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Priority to CN 201010201997 priority Critical patent/CN102290399B/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16245—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic

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Abstract

The invention relates to a stacking type chip packaging structure, which comprises a substrate, a first chip, a second chip and a packaging rubber body. The substrate comprises a plurality of pins, an accommodating part and a depression part, and the depression part is arranged in the middle area of the substrate and is surrounded by the pins. The accommodating part is arranged under the depression part and is communicated with the depression part. The first chip is fixed on the pins and is hidden in the depression part. The second chip is fixed on the first chip and is accommodated in the accommodating part, and the top surface of the second chip is parallel and level with the bottom surface of the pins. The packaging rubber body is used for packaging the substrate, the first chip and the second chip and is filled in the depression part and the accommodating part. The invention also provides a stacking type chip packaging method. By adopting the stacking type chip packaging structure and the stacking type chip packaging method, the first chip and the second chip are hidden in the substrate, so that the product size is reduced.

Description

Stack type chip packaging structure and method
Technical field
The present invention relates to semiconductor packaging, particularly a kind of stack type chip packaging structure and method.
Background technology
Existing stack type chip packaging structure is that the first chip-stacked end face in substrate is chip-stacked in the end face of first chip with second again.Yet this encapsulating structure volume is bigger, can not satisfy the development trend of miniaturization of electronic products, and cost is higher.
Summary of the invention
In view of this, need provide a kind of stack type chip packaging structure that can reduce volume.
A kind of stacked chips method for packing that can reduce volume also need be provided.
A kind of stack type chip packaging structure comprises substrate, first chip, second chip and adhesive body.Described substrate comprises a plurality of pins, resettlement section and depressed part, described depressed part be positioned at described substrate zone line and by described pin around.Described resettlement section is positioned at the below of described depressed part and is communicated with described depressed part.Described first chip is fixed in described pin and is hidden in the described depressed part.Described second chip is fixed in described first chip and is contained in the described resettlement section, and the end face of described second chip is concordant with the bottom surface of described each pin.Described adhesive body is packaged in described substrate, described first chip and described second chip in it, and fills described depressed part and described resettlement section, and the outer rim of described adhesive body is concordant with the outer rim of described substrate.
A kind of stacked chips method for packing comprises: substrate is provided, and described substrate comprises a plurality of pins, resettlement section and depressed part; First chip is fixed in described pin and is hidden in the described depressed part; The described substrate that overturns is fixed in described first chip with described second chip and is contained in the resettlement section, and the end face of second chip is concordant with the bottom surface of each pin; Glued membrane is pasted in bottom surface at described substrate; And will described first chip, second chip and described substrate package in adhesive body and remove glued membrane, with the formation packaging body; Wherein, described adhesive body is filled described depressed part and described resettlement section, and the outer rim of described adhesive body is concordant with the outer rim of described substrate.
Stack type chip packaging structure of the present invention by first chip and second chip are hidden in the substrate, has dwindled small product size.
Description of drawings
Fig. 1 is the assembling cross-sectional schematic that stack type chip packaging structure of the present invention does not have adhesive body.
Fig. 2 is the vertical view of stack type chip packaging structure shown in Figure 1.
Fig. 3 (a) to Fig. 3 (f) be the schematic flow sheet of stacked chips method for packing of the present invention.
The main element symbol description
Stack type chip packaging structure 100
Adhesive body 10
Substrate 20
Body 21
The first side wall 210
Second sidewall 230
Pin 23
Supporting part 232
Stop part 234
Depressed part 25
Resettlement section 27
First chip 30
Tin ball 32,42
Second chip 40
Glued membrane 50
Embodiment
Fig. 1 is the assembling cross-sectional schematic of stack type chip packaging structure 100 no adhesive bodies 10 of the present invention.Please also refer to Fig. 3 (e), stack type chip packaging structure 100 of the present invention comprises adhesive body 10, substrate 20, first chip 30 and second chip 40.
Please refer to Fig. 1 and Fig. 2, substrate 20 is frame structure, and it comprises body 21, a plurality of pin 23, resettlement section 27 and depressed part 25.Body 21 comprises a pair of relative the first side wall 210 and a pair of second relative sidewall 230, and described the first side wall 210 vertically links to each other respectively with described second sidewall 230.
Described pin 23 is separate and link to each other with body 21 respectively.In the present embodiment, described pin 23 is 6.Wherein, the inwall of each the first side wall 210 connects pair of pins 23 respectively, and the inwall of each second sidewall 230 connects a pin 23 respectively.
In other embodiments, the inwall of each the first side wall 210 and second sidewall 230 is connected one or more pins 23 respectively.
The interior ora terminalis place of the end face of each pin 23 is etched partially, thereby forms step-like.Each pin 23 comprises supporting part 232 and stop part 234, and the end face of stop part 234 is higher than the end face of supporting part 232.The height of supporting part 232 is substantially equal to the thickness of second chip 40.The height of stop part 234 is greater than the thickness of first chip 30.
Because the end face of stop part 234 is higher than the end face of supporting part 232, thereby form depressed part 25 at the zone line of substrate 20, namely depressed part 25 be positioned at the zone line of substrate 20 and be blocked portion 234 around, and the degree of depth of depressed part 25 is greater than the thickness of first chip 30.
Resettlement section 27 is surrounded by described supporting part 232, is used for accommodating second chip 40.Resettlement section 27 is positioned at the below of depressed part 25 and is communicated with depressed part 25, and the degree of depth of depressed part 25 is substantially equal to the thickness of second chip 40.
Glued membrane 50 (please refer to Fig. 3 (d)) is also pasted at the back side of substrate 20, is used for fixing described pin 23, and the excessive glue problem when preventing follow-up sealing.
First chip 30 comprises a plurality of tin balls 32, is electrically connected at the supporting part 232 of described pin 23 by described tin ball 32, and namely first chip 30 is fixed in pin 23.After the assembling, the end face of first chip 30 is lower than the end face of stop part 234, and namely first chip 30 is hidden in the depressed part 25 of substrate 20.
Second chip 40 comprises a plurality of tin balls 42, is fixed in first chip 30 by described tin ball 42.After the assembling, second chip 40 is contained in the resettlement section 27, and the end face of second chip 40 is concordant with the bottom surface of each pin 23.
Please refer to Fig. 3 (e), adhesive body 10 is with first chip 30, in second chip 40 and substrate 20 are packaged in, the outer rim of adhesive body 10 is concordant with the outer rim of substrate 20, and the gap between the tin ball 32 of adhesive body 10 fillings first chip 30, gap between the tin ball 42 of second chip 40, each pin 23 respectively and the gap between first chip 30 and second chip 40 and the end face of body 21, it is the end face that adhesive body 10 is filled body 21, depressed part 25 and resettlement section 27, and each pin 23 of substrate 20 exposes to adhesive body 10 bottom face profile and becomes the independent shape that do not link to each other separately, after treating that adhesive body 10 solidifies, tear the glued membrane 50 that is pasted on substrate 20 bottom surfaces off, namely form stack type chip packaging structure 100.In the present embodiment, adhesive body 10 is black glue.
Because first chip 30 is hidden in the depressed part 25 of substrate 20, and second chip 40 is hidden in the resettlement section 27 of substrate 20, namely first chip 30 and second chip 40 are hidden in respectively in the substrate 20, thereby reduced the height of stack type chip packaging structure 100, namely dwindled small product size and saved cost.
Fill gap between the tin ball 42 of gap between the tin ball 32 of first chip 30, second chip 40, each pin 23 because of adhesive body 10 respectively and the gap between first chip 30 and second chip 40 and the end face of body 21, thereby promote the power that is connected between substrate 20 and the adhesive body 10, improve aqueous vapor and infiltrate the degree of difficulty of stack type chip packaging structure 100 inside, and then guarantee that stack type chip packaging structure 100 has good reliability.
Fig. 3 (a) to Fig. 3 (f) be the schematic flow sheet of stacked chips method for packing of the present invention.
Step 1: substrate 20 (Fig. 3 (a)) is provided.In the present embodiment, substrate 20 comprises body 21, a plurality of pin 23, resettlement section 27 and depressed part 25.Described pin 23 is separate and link to each other with body 21 respectively.The interior ora terminalis place of the end face of each pin 23 is etched partially, thereby forms step-like.Each pin 23 comprises supporting part 232 and stop part 234, and the end face of stop part 234 is higher than the end face of supporting part 232.The height of supporting part 232 is substantially equal to the thickness of second chip 40.The height of stop part 234 is greater than the thickness of first chip 30.Resettlement section 27 is surrounded by described supporting part 232, is used for accommodating second chip 40.Depressed part 25 be positioned at the centre of substrate 20 and be blocked portion 234 around.Depressed part 25 is communicated with resettlement section 27, and the width of depressed part 25 is less than the width of resettlement section 27.
Step 2: first chip 30 is electrically connected at the pin 23 of substrate 20 and is contained in (Fig. 3 (b)) in the depressed part 25.
Step 3: substrate overturn 20, be fixed in the bottom surface of first chip 30 with second chip 40 and be contained in (Fig. 3 (c)) in the resettlement section 27.
Step 4: glued membrane 50 (Fig. 3 (d)) is pasted in the bottom surface at substrate 20.
Step 5: with adhesive body 10 first chip 30, second chip 40 and substrate 20 are encapsulated and remove glued membrane 50, to form packaging body (Fig. 3 (e)).In the present embodiment, adhesive body 10 is black glue.
Step 6: with the assembling (Fig. 3 (f)) that is stacked of a plurality of stack type chip packaging structures 100.In other embodiments, can there be step 6 yet.

Claims (10)

1. a stack type chip packaging structure comprises substrate, first chip, second chip and adhesive body, it is characterized in that:
Described substrate comprises a plurality of pins, resettlement section and depressed part, described depressed part be positioned at described substrate zone line and by described pin around, described resettlement section is positioned at the below of described depressed part and is communicated with described depressed part;
Described first chip is fixed in described pin and is hidden in the described depressed part;
Described second chip is fixed in described first chip and is contained in the described resettlement section, and the end face of described second chip is concordant with the bottom surface of described each pin; And
Described adhesive body is packaged in described substrate, described first chip and described second chip in it;
Wherein, described adhesive body is filled described depressed part and described resettlement section, and the outer rim of described adhesive body is concordant with the outer rim of described substrate.
2. stack type chip packaging structure as claimed in claim 1 is characterized in that, described substrate is frame structure, and described frame structure comprises body, and described pin is connected with described body.
3. stack type chip packaging structure as claimed in claim 2 is characterized in that, each pin is step-like.
4. stack type chip packaging structure as claimed in claim 3 is characterized in that, each pin comprises supporting part and stop part, and the end face of described stop part is higher than the end face of described supporting part.
5. stack type chip packaging structure as claimed in claim 4 is characterized in that, described resettlement section is surrounded by described supporting part, and described stop part is around described depressed part.
6. a stacked chips method for packing is characterized in that, comprising:
Substrate is provided, and described substrate comprises a plurality of pins, resettlement section and depressed part;
First chip is fixed in described pin and is hidden in the described depressed part;
The described substrate that overturns is fixed in described first chip with described second chip and is contained in the described resettlement section, and the end face of second chip is concordant with the bottom surface of each pin;
Glued membrane is pasted in bottom surface at described substrate; And
With described first chip, second chip and described substrate package in adhesive body and remove glued membrane, to form packaging body;
Wherein, described adhesive body is filled described depressed part and described resettlement section, and the outer rim of described adhesive body is concordant with the outer rim of described substrate.
7. stacked chips method for packing as claimed in claim 6 is characterized in that, described substrate is frame structure, and described frame structure comprises body, and described pin is connected with described body.
8. stacked chips method for packing as claimed in claim 7 is characterized in that, each pin is step-like.
9. stacked chips method for packing as claimed in claim 8 is characterized in that, each pin comprises supporting part and stop part, and the end face of described stop part is higher than the end face of described supporting part.
10. stacked chips method for packing as claimed in claim 9 is characterized in that, described resettlement section is surrounded by described supporting part, and described stop part is around described depressed part.
CN 201010201997 2010-06-17 2010-06-17 Stacking type chip packaging structure and method Active CN102290399B (en)

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Publication number Priority date Publication date Assignee Title
CN103208471B (en) * 2013-04-23 2015-12-23 山东华芯半导体有限公司 Multi-chip encapsulation body

Citations (4)

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Publication number Priority date Publication date Assignee Title
JP2000183275A (en) * 1998-12-11 2000-06-30 Mitsui High Tec Inc Semiconductor device
US6483181B2 (en) * 2001-04-19 2002-11-19 Walton Advanced Electronics Ltd. Multi-chip package
CN1505149A (en) * 2002-12-02 2004-06-16 华泰电子股份有限公司 Three-dimensional packaging apparatus of multichip integrated circuit
CN201838585U (en) * 2010-06-17 2011-05-18 国碁电子(中山)有限公司 Stackable chip packaging structure and base plate thereof

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Publication number Priority date Publication date Assignee Title
JPH06120418A (en) * 1992-10-07 1994-04-28 Nec Corp Manufacture of hybrid integrated circuit
JPH06268153A (en) * 1993-03-12 1994-09-22 Hitachi Maxell Ltd Semiconductor device
KR20040060124A (en) * 2002-12-30 2004-07-06 동부전자 주식회사 Flip-chip ceramic packaging method
TWI237882B (en) * 2004-05-11 2005-08-11 Via Tech Inc Stacked multi-chip package
TWI250592B (en) * 2004-11-16 2006-03-01 Siliconware Precision Industries Co Ltd Multi-chip semiconductor package and fabrication method thereof
JP2009295959A (en) * 2008-05-09 2009-12-17 Panasonic Corp Semiconductor device, and method for manufacturing thereof

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2000183275A (en) * 1998-12-11 2000-06-30 Mitsui High Tec Inc Semiconductor device
US6483181B2 (en) * 2001-04-19 2002-11-19 Walton Advanced Electronics Ltd. Multi-chip package
CN1505149A (en) * 2002-12-02 2004-06-16 华泰电子股份有限公司 Three-dimensional packaging apparatus of multichip integrated circuit
CN201838585U (en) * 2010-06-17 2011-05-18 国碁电子(中山)有限公司 Stackable chip packaging structure and base plate thereof

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Applicant before: Hon Hai Precision Industry Co., Ltd.

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Owner name: XUNXIN ELECTRONIC TECHNOLOGY (ZHONGSHAN) CO., LTD.

Free format text: FORMER NAME: AMBIT MICROSYSTEMS (ZHONGSHAN) CORPORATION

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Address after: 528437 No. 9 Jianye East Road, Torch Development Zone, Guangdong, Zhongshan

Patentee after: - the core of Electronic Science and Technology (Zhongshan) Co., Ltd.

Address before: 528437 export processing zone of Torch Development Zone, Guangdong, Zhongshan

Patentee before: Ambit Electronics (Zhongshan) Co., Ltd.