CN102289420B - Simple single-bus interface conversion circuit and data acquisition system adopting same - Google Patents
Simple single-bus interface conversion circuit and data acquisition system adopting same Download PDFInfo
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- CN102289420B CN102289420B CN 201110177874 CN201110177874A CN102289420B CN 102289420 B CN102289420 B CN 102289420B CN 201110177874 CN201110177874 CN 201110177874 CN 201110177874 A CN201110177874 A CN 201110177874A CN 102289420 B CN102289420 B CN 102289420B
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Abstract
The invention discloses a simple single-bus interface conversion circuit. At least two three-state buffers drive sending of data, so transmission capacity is transmitted; and a single-bus end is grounded by a pull-down resistor, so the anti-interference capacity of sending of the data is improved. Meanwhile, after the three-state buffers amplify input data which is input to a data input end of a logical AND gate, the input data is input to a serial point of two input resistors, which are connected in series, of the logical AND gate by output resistors which are connected in parallel and capacitors, so the input data is amplified in the forward direction, the signal strength of the input data of the data input end of the logical AND gate is improved, and the receiving stability of the data is improved. Moreover, a microprocessor is adopted to control the sending and receiving of the data; during the sending of the data, the logical AND gate is closed, and the input data is not received, so the sending of the data cannot influence a receiving end of the microprocessor; and burrs are avoided from being formed at the receiving end of the microprocessor during the sending of the data in the prior art, so communication reliability is reduced.
Description
Technical field
The invention belongs to the interface circuit technical field, more specifically say, relate to the data acquisition system (DAS) of a kind of simple and easy Monobus interface conversion circuit and application thereof.
Background technology
Most microprocessor internals have two order wires usually with UART Universal Asynchronous Receiver Transmitter on its hardware, one is the reception line, and one for sending line.But in some application scenario, particularly very harsh for communication distance and the not high but space requirement of required communication rate, can't design the application scenario with transmitting-receiving interface circuits such as triple gates, can only be designed to an order wire.Single bus interface is for communication distance and required communication rate not high application scenario, and is not only easy for installation, and reduces wiring cost.
Existing universal asynchronous receiving-transmitting interface is made of a PNP triode and a NPN triode usually to the change-over circuit of single bus interface, although circuit is simple, exists use dumb, the deficiencies such as communication reliability and inefficiency.
As improvement, be CN 101674074A on 03 07th, 2010 announcement, publication number, denomination of invention has been announced a kind of Monobus interface conversion circuit in the Chinese invention patent application Publication Specification of " a kind of Monobus interface conversion circuit of self-adaptive level ", adopt four Sheffer stroke gates to divide two groups of series connection to consist of the sending and receiving change-over circuits, carry out level conversion at the output terminal of each Sheffer stroke gate with pull-up resistor.simultaneously, microprocessor is sent order wire be linked into an input end (2 pin) that receives change-over circuit output Sheffer stroke gate (U2A), the input of other three Sheffer stroke gates all connects together, suitable Sheffer stroke gate, like this, when the microprocessor transmitted signal is high level, the next signal of another input end (1 pin) feedback that receives change-over circuit output Sheffer stroke gate (U2A) is low level, be output as high level like this and after non-, and when the microprocessor transmitted signal is low level, an input end (2 pin) that receives change-over circuit output Sheffer stroke gate (U2A) is low level, be output as high level like this and after non-, when being the microprocessor output signal, the output of interface conversion circuit, the receiving end RXD clock that is microprocessor is high level, avoid microprocessor that the data that receive the machine and send are carried out unnecessary judgement and processing and reduced the reliability of communication and the work efficiency of microprocessor.
but in above-mentioned Monobus interface conversion circuit, adopt Sheffer stroke gate to export to drive on unibus and send data, driving force is not strong, makes the transmission range of unibus less, and transmittability is low, the employing Sheffer stroke gate directly receives the data from unibus, easily be interfered, the data receiver poor stability, in addition, although transmitted signal is in theory, can not produce low level look-at-me at the receiving end RXD of microprocessor, but because the time-delay that three grades of Sheffer stroke gates are arranged exists, in the microprocessor output signal from low to high the time, two ends of output Sheffer stroke gate (U2A) will be all high level, Sheffer stroke gate (U2A) can occur like this and be output as low level burr, the receiving end RXD of microprocessor can produce low level look-at-me, reduced on the contrary the reliability of communication.
Summary of the invention
The object of the invention is to overcome the deficiencies in the prior art, provide that a kind of transmittability is strong, stable high, the simple and easy Monobus interface conversion circuit that communication reliability is strong of data receiver.
For achieving the above object, a kind of simple and easy Monobus interface conversion circuit of the present invention comprises:
At least two three-state buffers, its input end all connects the data sending terminal of microprocessor, and output terminal outputs on the unibus end by an output resistance respectively, and the unibus end is by a drop-down resistance eutral grounding;
One phase inverter, the transmit-receive position control end of its input termination microprocessor, output terminal is received respectively described at least two three-state buffers Enable Pin separately;
One logical AND gate, its output terminal is connected to the data receiver of microprocessor, and an input end is as the transmit-receive position control end of controlling the termination microprocessor, and another input end is received the unibus end as data input pin by two input resistances of series connection;
One impact damper, its input end is received the input end of logical AND gate, on the series connection point of two input resistances of the series connection that output terminal is received logical AND gate by output resistance and the electric capacity of parallel connection;
When microprocessor sends data, its transmit-receive position control end output low level, anti-phase rear output high level, enable described at least two three-state buffers in phase inverter, send data after described at least two three-state buffers drive, output to the unibus end through separately output resistance; Simultaneously, the data input pin of logical AND gate is low level, closes logical AND gate, and its output is always low level, does not receive the input data;
During the microprocessor receive data, its transmit-receive position control end output high level, anti-phase rear output low level in phase inverter, described at least two three-state buffers do not enable, and do not export; Simultaneously, the control end of logical AND gate is high level, open logical AND gate, input data from the unibus end output to the data receiver of microprocessor by two input resistances, logical AND gates of series connection, in addition, after the input data that are input to the logical AND gate data input pin are amplified by impact damper by output resistance in parallel and electric capacity output logic with the series connection point of two input resistances of connecting on.
Goal of the invention of the present invention is achieved in that
The simple and easy Monobus interface conversion circuit of the present invention drives sending data by at least two three-state buffers, has strengthened transmittability, and the unibus end by a drop-down resistance eutral grounding, has improved the antijamming capability that sends data simultaneously.Simultaneously, after adopting impact damper that the input data that are input to the logical AND gate data input pin are amplified, on the series connection point of the output resistance by parallel connection and electric capacity output logic and two input resistances of connecting of door, like this input data being carried out forward amplifies, strengthened the signal intensity of logical AND gate data input pin input data, data receiver stability is improved.In addition, adopt microprocessor to control transmitting and receive data, when sending data, closed logical AND gate, do not receive the input data, avoided sending data to the impact of microprocessor receiving end, simultaneously, also avoided in prior art, when sending data, burr appears in the microprocessor receiving end, reduces the situation of communication reliability.
Description of drawings
Fig. 1 is a kind of embodiment schematic diagram of using the data acquisition system (DAS) of the simple and easy Monobus interface conversion circuit of the present invention.
Embodiment
Below in conjunction with accompanying drawing, the specific embodiment of the present invention is described, so that those skilled in the art understands the present invention better.What need to point out especially is that in the following description, when perhaps the detailed description of known function and design can desalinate main contents of the present invention, these were described in here and will be left in the basket.
Embodiment
Fig. 1 is a kind of embodiment schematic diagram of using the data acquisition system (DAS) of the simple and easy Monobus interface conversion circuit of the present invention.
As shown in Figure 1, in the present embodiment, simple and easy Monobus interface conversion circuit comprises:
Two three-state buffers, be three-state buffer 1, three-state buffer 2, their input ends all meet the data sending terminal SDATA_OUT of PIC microprocessor, output terminal SDATA_OUT1, SDATA_OUT2 output on unibus end SDATA by output resistance R2, R3 respectively, and unibus end SDATA is by drop-down resistance R 1 ground connection;
Phase inverter, the transmit-receive position control end DIR of its input termination microprocessor, output terminal is received respectively three-state buffer 1, three-state buffer 2 Enable Pin ENB separately;
Logical AND gate, its output terminal is connected to the data receiver SDATA_IN of microprocessor, an input end is as the transmit-receive position control end of controlling termination PIC microprocessor, and another input end is received unibus end SDATA as data input pin SDATA_IN1 by two input resistance R6, R4 that connect;
One impact damper, its input end is received the data input pin SDATA_IN1 of logical AND gate, on the series connection point of two input resistance R6, R4 of the series connection that positive feedback output terminal SDATA_FB receives logical AND gate by output resistance R5 and the capacitor C 1 of parallel connection, wherein, 1 pair of input data level speed reversal degree of capacitor C is accelerated, and the edge is played shaping operation.
In the present embodiment, three-state buffer 1,2, phase inverter, logical AND gate and impact damper adopt the design of CPLD internal logic unit.
In the present embodiment, the simple and easy Monobus interface conversion circuit of the present invention is applied in data acquisition system (DAS), wherein PIC microprocessor is carried out sending and receiving end SDATA_IN, SDATA_OUT, and to the conversion of unibus end SDATA, unibus end SDATA receives on the host computer of data acquisition system (DAS).
Under original state, the PIC microprocessor in data acquisition system (DAS) is preset as high level with transmit-receive position control end DIR, interrupts enabling to open, and is the receive data state.After receiving the order data of host computer by simple and easy Monobus interface conversion circuit of the present invention, data acquisition system (DAS) begins fill order, namely carries out the collection of data.Because data acquisition is very accurate to regularly requiring, when the executing data acquisition, thereby if will destroying its control sequential, PIC microprocessor execution interruption processing causes the gatherer process mistake, therefore will close the PIC microprocessor when carrying out acquisition interrupts enabling, make the PIC microprocessor not accept interruption, also namely do not receive the order of host computer.After command execution is complete, opening the PIC microprocessor interrupts enabling, the PIC microprocessor is made as low level with transmit-receive position control end DIR, begin this moment to send data to host computer, and the data volume that sends is counted, by the transmission data being counted to judge the end of process of transmitting, after data are sent completely, the PIC microprocessor is made as high level with transmit-receive position control end DIR again, enters into original state, i.e. the receive data state.Corresponding with the course of work of simple and easy Monobus interface conversion circuit, under original state, host computer is in the transmission coomand mode, after being sent completely, Wait Order is in the receive data state, no longer send order to data acquisition system (DAS) this moment, only has just to be in again the transmission coomand mode after the data that receive data acquisition system (DAS).Data acquisition system (DAS) can be passed through unibus like this, realize the transmission of host computer order data and the reception of image data, and communication reliability is strong.
When the PIC microprocessor received data from host computer, namely under original state, its transmit-receive position control end DIR exported high level, anti-phase rear output low level in phase inverter, and three-state buffer 1, three-state buffer 2 do not enable, and do not export; Simultaneously, the control end of logical AND gate is high level, open logical AND gate, input data from unibus end SDATA output to the data receiver SDATA_IN of PIC microprocessor by two input resistance R4, R6, logical AND gates of series connection, in addition, after the input data that are input to logical AND gate data input pin SDATA_IN1 are amplified by impact damper by output resistance R5 in parallel and capacitor C 1 output logic with the series connection point of two input resistance R6, R4 connecting on.Like this input data are carried out forward and amplify, strengthened the signal intensity of logical AND gate data input pin SDATA_IN1 input data, data receiver stability is improved.
When the PIC microprocessor sends data to host computer, its transmit-receive position control end DIR output low level, anti-phase rear output high level in phase inverter, enable three-state buffer 1, three-state buffer 2, send data after three-state buffer 1, three-state buffer 2 drive, output to unibus end SDATA through output resistance R2, R3; Simultaneously, the data input pin SDATA_IN1 of logical AND gate is low level, closes logical AND gate, and its output is always low level, does not receive the input data.The purpose of utilizing two three-state buffers 1, three-state buffer 2 to export simultaneously same transmission data-signal is strengthen the load capacity that sends data-signal and improve this Anti-jamming of signal ability.The pull down resistor R1 that the output resistance R2 that output terminal SDATA_OUT1 and SDATA_OUT2 connect separately and output resistance R3 are connected with unibus end SDATA forms the dividing potential drop to the transmission data-signal of output terminal SDATA_OUT1 and SDATA_OUT2 output, thereby unibus end SDATA obtain a range value be about data sending terminal SDATA_OUTS send the data signal amplitude value half, this is conducive to reduce to the amplitude of data that host computer sends and then reduces interference to circuit itself and host computer.
In addition, adopt microprocessor to control transmitting and receive data, when sending data, closed logical AND gate, do not receive the input data, avoided sending data to the impact of microprocessor receiving end, simultaneously, also avoided in prior art, when sending data, burr appears in the microprocessor receiving end, reduces the situation of communication reliability.
Although the above is described the illustrative embodiment of the present invention; so that those skilled in the art understand the present invention; but should be clear; the invention is not restricted to the scope of embodiment; to those skilled in the art; as long as various variations appended claim limit and the spirit and scope of the present invention determined in, these variations are apparent, all utilize innovation and creation that the present invention conceives all at the row of protection.
Claims (2)
1. a simple and easy Monobus interface conversion circuit, is characterized in that, comprising:
At least two three-state buffers, its input end all connects the data sending terminal of microprocessor, and output terminal outputs on the unibus end by an output resistance respectively, and the unibus end is by a drop-down resistance eutral grounding;
One phase inverter, the transmit-receive position control end of its input termination microprocessor, output terminal is received respectively described at least two three-state buffers Enable Pin separately;
One logical AND gate, its output terminal is connected to the data receiver of microprocessor, and an input end is as the transmit-receive position control end of controlling the termination microprocessor, and another input end is received the unibus end as data input pin by two input resistances of series connection;
One impact damper, its input end is received the input end of logical AND gate, on the series connection point of two input resistances of the series connection that output terminal is received logical AND gate by output resistance and the electric capacity of parallel connection;
When microprocessor sends data, its transmit-receive position control end output low level, anti-phase rear output high level, enable described at least two three-state buffers in phase inverter, send data after described at least two three-state buffers drive, output to the unibus end through separately output resistance; Simultaneously, the data input pin of logical AND gate is low level, closes logical AND gate, and its output is always low level, does not receive the input data;
During the microprocessor receive data, its transmit-receive position control end output high level, anti-phase rear output low level in phase inverter, described at least two three-state buffers do not enable, and do not export; Simultaneously, the control end of logical AND gate is high level, open logical AND gate, input data from the unibus end output to the data receiver of microprocessor by two input resistances, logical AND gates of series connection, on the series connection point of two input resistances of the series connection that output resistance and the electric capacity by parallel connection after the input data that in addition, are input to the logical AND gate data input pin are amplified by impact damper exports logical AND gate to.
2. data acquisition system (DAS) of using simple and easy Monobus interface conversion circuit, comprise the PIC microprocessor, host computer, it is characterized in that, also comprise simple and easy Monobus interface conversion circuit claimed in claim 1, the PIC microprocessor is carried out the sending and receiving end to the conversion of unibus end, the receiving on host computer of unibus end;
Under original state, the PIC microprocessor in data acquisition system (DAS) is preset as high level with the transmit-receive position control end, interrupts enabling to open, and simple and easy Monobus interface conversion circuit is in the receive data state;
Receive the order data of host computer when simple and easy Monobus interface conversion circuit after, data acquisition system (DAS) begins fill order, carries out the collection of data, the PIC microprocessor interrupts enabling to cut out when carrying out acquisition; After command execution is complete, opening the PIC microprocessor interrupts enabling, the PIC microprocessor is made as low level with the transmit-receive position control end, begin this moment to send data to host computer, and the data volume that sends is counted, by the transmission data being counted to judge the end of process of transmitting, after data are sent completely, the PIC microprocessor is made as high level with the transmit-receive position control end again, enters into the receive data state;
Corresponding with the course of work of simple and easy Monobus interface conversion circuit, under original state, host computer is in the transmission coomand mode, after being sent completely, Wait Order is in the receive data state, no longer send order to data acquisition system (DAS) this moment, only has just to be in again the transmission coomand mode after the data that receive data acquisition system (DAS).
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| CN 201110177874 CN102289420B (en) | 2011-06-28 | 2011-06-28 | Simple single-bus interface conversion circuit and data acquisition system adopting same |
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| CN 201110177874 CN102289420B (en) | 2011-06-28 | 2011-06-28 | Simple single-bus interface conversion circuit and data acquisition system adopting same |
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| CN102289420B true CN102289420B (en) | 2013-06-12 |
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| CN105866610B (en) * | 2016-04-15 | 2019-11-22 | 中国海洋石油集团有限公司 | Connect the detection device and detection method of bus |
| CN107678995B (en) * | 2017-09-26 | 2024-04-02 | 歌尔科技有限公司 | Data communication method and electronic equipment |
| CN110768815B (en) * | 2018-07-27 | 2023-10-10 | 东君新能源有限公司 | Method for switching signal lines and solar system |
| CN109586750B (en) * | 2018-12-20 | 2020-12-01 | 苏州路之遥科技股份有限公司 | Single bus communication signal enhancement circuit |
| CN109861896A (en) * | 2019-03-29 | 2019-06-07 | 上海剑桥科技股份有限公司 | High speed unibus equipment |
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| CN101674074A (en) * | 2009-09-29 | 2010-03-17 | 福建师范大学 | Monobus interface conversion circuit of self-adaptive level |
| CN101741515A (en) * | 2009-12-31 | 2010-06-16 | 煤炭科学研究总院重庆研究院 | Single-bus two-way communication circuit |
| CN101820372A (en) * | 2010-03-17 | 2010-09-01 | 浙江大学 | TDM (Time Division Multiplexing) single-bus communication system of power supply, data signals and audio analog signals |
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Patent Citations (8)
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| EP0808530B1 (en) * | 1995-12-11 | 2002-11-13 | Koninklijke Philips Electronics N.V. | Bi-directional signal transmission system |
| EP0810735A2 (en) * | 1996-05-30 | 1997-12-03 | Nec Corporation | Tristate buffer having a bipolar transistor |
| CN1288543A (en) * | 1997-12-18 | 2001-03-21 | 汤姆森许可公司 | High speed data bus driver |
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