CN102259833B - Preparation method of nano wire device based on nano wire cross connection - Google Patents
Preparation method of nano wire device based on nano wire cross connection Download PDFInfo
- Publication number
- CN102259833B CN102259833B CN201110144804.5A CN201110144804A CN102259833B CN 102259833 B CN102259833 B CN 102259833B CN 201110144804 A CN201110144804 A CN 201110144804A CN 102259833 B CN102259833 B CN 102259833B
- Authority
- CN
- China
- Prior art keywords
- covering
- core
- table top
- nano wire
- nano
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Landscapes
- Electrodes Of Semiconductors (AREA)
Abstract
The invention provides a preparation method of a nano wire device based on nano wire cross connection, which is characterized in that a table-board structure is formed by etching on the top film of a semiconductor substrate; the substrate surface is used as a substrate for growing a nano wire having a 'core-envelope' device structure; the electrical connection of the envelope of the nano wire and the table-board wall is realized through nano wires which subsequently grow, wherein the nano wires which subsequently grow use the table-board side wall or the side wall of ' core-envelope' nano wire as a growing substrate for lateral growth so as to realize the electrical connection of the envelope of the nano wire device and the table-board side wall. According to the method, fine and expensive electron beam photolithographic process is not adopted; the nano wires are not moved and operated; and the preparation method provided by the invention has the characteristics of simple process and suitability to scale preparation.
Description
Technical field
The present invention relates to a kind of preparation method of nano-wire devices, can be used for nano wire microelectronics and opto-electronic device.
Background technology
Nanoscale science and technology is considered to one of three big science technology of 21 century.Wherein, semiconductor nanowires is due to its unique One-dimensional Quantum structure, is considered to following nano-electron and receives the basic structure [Mater.Today, 9 (2006) 18-27] of photonic device.In recent years, the research work of semiconductor nanowires has received very big concern, its application comprises integrated circuit [Nature, 470 (2011) 240-244], transistor [Nano Letters, 8 (2008) 925-930], laser [Science, 292 (2001) 1897-1899], single photon device [Nature Nanotechnology, 5 (2010) 195-199], LED[Nano Letters, 6 (2006) 1719-1722, ] and solar cell [Nano Lett., 10 (2010) 1082-1087] etc.
Although semiconductor nanowires has very important application prospect, but solution series of problems is also needed in the practical and industrialization of nano-wire devices badly, key issue is wherein how to manipulate, to assemble and to process for the nano wire of extremely very thin (diameter is thin to several nanometers).
The preparation of nano-wire devices at present needs first nano wire to be shifted and kept flat on another substrate (normally to stack in a jumble) conventionally, then find one by one suitable nano wire by electron beam photoetching process and carry out lithography process [Nano Letters, 8 (2008) 925-930]; This technique for single nano-wire processing cannot realize extensive batch preparation, and the speed of electron beam lithography is very slow, expensive.Therefore, simplifying nano-wire devices technique, reduce preparation difficulty, is the problem that nano-wire devices industrialization faces.
For this reason, people have invented a kind of without electron beam lithography, also without original position processing technology [Nanotechnology, 15 (2004) L5-L8 of mobile nano wire; Appl.Phys.Lett., 89 (2006) 133121; Adv.Mater., 17 (2005) 2098-2102], in Semiconductor substrate, etch perpendicular grooves structure (each groove has two vertical side), semiconductor nanowires starts growth and finally touches another side, opposite from a side of groove.Nano wire is just equivalent to a bridge two sides of groove is coupled together like this, nano wire can be between two sidewalls On current.What is more important: the two end electrodes of nano-wire devices just can be prepared on the table top of groove both sides, and without being prepared on very thin nano wire, also without mobile and manipulation nano wire.Because the area of groove both sides table top is very large, prepare electrode and adopt common optical lithography processes, without adopting meticulous electron beam lithography technique; (two sides of parallel connecting groove) in order of the orientation of nano wire simultaneously, are applicable to scale and prepare in batches nano-wire devices.
But for the nano-wire devices (its two ends connect respectively N-shaped and p-type electrode) of axial arrangement, therefore requiring groove two layers of material is respectively also N-shaped and p-type doping (being different types of doping) accordingly.But groove is that etching forms on same semiconductor, and therefore its doping type is normally identical; If need to form different doping types in groove both sides, need extra complicated technology.
What is more important: (core that is nano wire is that p-type doping, covering are N-shaped doping for the nano-wire devices of radial structure (i.e. " core one covering (core-shell) " coaxial configuration), or core is that N-shaped doping, covering are p-type doping), two electrodes of device must be connected with core and the covering of nano wire respectively, and therefore groove structure cannot be used for connecting two electrodes of " core one covering " structure nanometer wire.
In sum, the groove structure of nano wire bridge joint, the electrode that cannot be used for " core one covering " structure nanometer wire device connects, and needs extra technique to realize the dissimilar doping of groove both sides.Therefore design research and development are applicable to simple, low cost process prepared by " core one covering " structure nanometer wire device, are that wound of the present invention is ground motivation.
Summary of the invention
The present invention is intended to the electrode of solution " core one covering " structure nanometer wire (hereinafter to be referred as " CS nano wire ") device and prepares problem; a kind of " based on the interconnected nano-wire devices preparation method of nanowire crossbars " proposed; the method, without the electron beam lithography technique of the meticulous costliness of employing, also without mobile and manipulation nano wire, has the advantages that prepared by simple, the applicable scale of technique.
Inventor has deep research [Nano Letters to semiconductor nanowires, 10 (2010) 64-68], and once observed in test the mutual cross-coupled phenomenon of nano wire (as shown in Figure 1, nano wire junction is in conjunction with good), thus generation of the present invention inspired.The present invention can realize in the following manner:
In the Semiconductor substrate with intermediate insulating layer, (between N-shaped region, bottom and p-type region, top, be insulating barrier, as shown in Fig. 2 (a)), form mesa structure by etching, make the doping type of table top bottom different with the doping type of side (for example table top bottom is that N-shaped, table top sidewall are p-type, shown in Fig. 2 (a));
By the mode of metal-coated films after annealing or metallizing particle colloidal sols, at bottom and the side attachment metallic particles (as shown in Fig. 2 (b)) of table top, as catalyst guiding nanowire growth (if the mode of the growth of nano wire employing self-catalysis, can be without metallic particles, this step can be omitted); Then cover one deck mask in mesa surfaces, cover metallic particles and table top (as shown in Fig. 2 (b));
Then adopt photoetching and etching technics that the mask of table top bottom is removed, expose the metallic particles (as shown in Fig. 2 (c)) (if the growth of nano wire adopts the mode of self-catalysis, exposing table top bottom) of bottom; Then epitaxial growth CS nano wire, wherein the doping type of core segment is identical with the doping type of table top bottom, the doping type of covering identical with the doping type of table top sidewall (as shown in Fig. 2 (c));
Then remove the mask layer of table top sidewall, expose the metallic particles of sidewall (if the growth of nano wire adopts the mode of self-catalysis, expose table top sidewall), and on sidewall, start grow nanowire (its doping type is identical with sidewall); Along with the carrying out of lateral growth, sidewall nano wire (hereinafter to be referred as " SW nano wire ") is connected (as shown in Fig. 2 (d)) with the CS nanowire crossbars of bottom, formed good current channel so the bridge joint of two kinds of nano wires is interconnected;
Last bottom and mesa top metallized electrode (as shown in Fig. 2 (d)) at substrate, because the area of substrate bottom and table top is very large, prepare in the above electrode and can adopt common optical lithography processes, and without mobile and manipulation nano wire.
In sum, the CS nano-wire devices in the present invention, one of them electrode is connected with table top bottom by nanowire core, and another electrode is connected covering by SW nano wire with sidewall.Because the density of nano wire is conventionally very high by (10
10root/cm
2), so without the accurate nano wire of alignment interconnects, always having certain root SW nano wire can be connected with the CS nano wire of bottom.
In the present invention, the doping type of substrate can be also bottom for p-type doping, top are N-shaped doping, and the core of corresponding CS nano wire is that p-type doping, covering are N-shaped doping, and corresponding SW nano wire is that N-shaped adulterates.
In the present invention, the intermediate layer of Semiconductor substrate is insulating barrier, and as silicon-on-insulator substrate, (be SOI substrate, insulating barrier is SiO
2); Intermediate insulating layer also can adopt the doped structure (as shown in Fig. 4 (a)) of PNP or NPN, has so reverse PN junction between substrate top and bottom, equally can On current.
Substrate of the present invention and nano-material are selected from IV family, II-VI family and III-V family material, the wherein preferred Si of backing material, GaAs and InP, the preferred Si of nano-material, GeSi, ZnO, GaAs, AlInGaAsP, InP, GaN, AlInGaN and InGaSb.
CS nano-wire devices in accompanying drawing of the present invention, is PN junction diode structure, also can is the more complicated structure such as PIN, PINIP, concrete structure is depending on different type of device.Feature of the present invention is that CS nano-wire devices belongs to the coaxial configuration of " core one covering ", and wherein covering is connected by the SW nano wire of subsequent growth with the electrical connection of table top sidewall.
SW nano wire in the present invention also can start using the sidewall of CS nano wire as substrate growth (as shown in Fig. 4 (c)); With the carrying out of lateral growth, SW nano wire final with table top sidewall contact, thereby covering and the table top sidewall of connection CS nano wire.
One has the electrode preparation method of " core one covering " structure nanometer wire device, concrete steps are: in the Semiconductor substrate with mesa structure, there is the nano wire of " core one covering " structure as substrate grown using table top bottom, the covering of this nano wire is realized with being electrically connected by the side direction nano wire of subsequent growth of table top sidewall, described Semiconductor substrate contains intermediate insulating layer, and the doping type of substrate top is different from the doping type of substrate bottom.
Wherein, described side direction nano wire, be sidewall using table top as substrate, thereby and " core one covering " structure nanometer wire interconnection of lateral growth and the growth of table top bottom.
Wherein, described side direction nano wire, be covering using " core one covering " structure nanometer wire as substrate, thereby and lateral growth be connected with table top sidewall.
Wherein, described side direction nano wire, is that covering and the table top sidewall of " core one covering " structure nanometer wire are linked up, thereby realizes being electrically connected between the covering of nano-wire devices and table top sidewall.
Wherein, described table top, can obtain by etching semiconductor substrate, the doping type of its sidewall is different with the doping type of bottom, wherein, by the mode of metal-coated films after annealing or metallizing particle colloidal sols, at bottom and the side attachment metallic particles of table top, as catalyst guiding nanowire growth.
Wherein, described intermediate insulating layer is SiO
2insulating barrier or there is the semiconductor lamella of NPN doped structure.
Wherein, described " core one covering " structure nanometer wire device, its electrode can be prepared in table top bottom and mesa top; Wherein the electrode of table top bottom is connected with the core of " core one covering " nano wire, the electrode of mesa top is connected with the covering of " core one covering " nano wire by side direction nano wire, wherein, the doping type of core segment is identical with the doping type of table top bottom, and the doping type of covering is identical with the doping type of table top sidewall.
Brief description of the drawings
Accompanying drawing, it is incorporated into and becomes the part of this specification, the embodiments of the invention of having demonstrated, and explain principle of the present invention with aforesaid summary together with detailed description below.
Fig. 1 is the scanning electron microscope image that the nanowire crossbars that arrives of experimental observation connects.
Fig. 2 is the nano-wire devices preparation flow scheme one interconnected based on nanowire crossbars.
Fig. 2 (a). in the Semiconductor substrate with intermediate insulating layer, etch mesa structure;
Fig. 2 (b). adhesion metal particle mask film covering layer on table top;
Fig. 2 (c). etching is exposed table top bottom the CS nano wire of growing;
Fig. 2 (d). etching is exposed table top sidewall and the SW nano wire of growing on sidewall is connected with CS nano wire;
Fig. 3 is the nano-wire devices preparation flow scheme two interconnected based on nanowire crossbars.
Fig. 3 (a). mask film covering the CS nano wire of growing in table top bottom on table top sidewall;
Fig. 3 (b). etching is exposed table top sidewall and the SW nano wire of growing on sidewall is connected with CS nano wire;
Fig. 4 is based on the interconnected nano-wire devices preparation flow scheme three of nanowire crossbars.
Fig. 4 (a). in the Semiconductor substrate with PNP doped layer, etch mesa structure;
Fig. 4 (b). form metallic particles the CS nano wire of growing in table top bottom;
Fall and along lateral growth and sidewall contact in the top of Fig. 4 (c) .CS nano wire;
Embodiment
For making the content of technical scheme of the present invention more clear, describe the specific embodiment of the present invention in detail below in conjunction with technical scheme and accompanying drawing.
The present invention only relates to the electrode preparation method of nano-wire devices, do not relate to the growing technology details (as gas-liquid-solid (VLS) growth, selective area growth (SAG), based on buffer growth, dual-temperature process growth etc.) of nano wire, in specific embodiments of the invention, do not enumerate the various growing technologies of nano wire.Wherein the growth pattern of nano wire comprises: the common technologies such as evaporation, sputter, hydro thermal method (hydrothermal), metal-organic chemical vapor deposition equipment (MOCVD), molecular beam epitaxy (MBE) and chemical vapour deposition (CVD) (CVD).
Example 1
First, remove silicon SOI substrate top subregional top p-type layer and middle SiO by etching
2insulating barrier, forms table top (table top bottom is N-shaped silicon, and table top sidewall is p-type silicon), as shown in Fig. 2 (a);
Secondly, spin coating aurosol on silicon substrate (solution of colloidal Au nanoparticles), ADSORPTION OF GOLD nano particle on the bottom of table top and sidewall, and form alloying pellet by annealing; Then one deck SiO grows on table top
2layer, covers bottom table top and the alloying pellet of sidewall, as shown in Fig. 2 (b);
Then remove the SiO of table top bottom by photoetching and etching technics
2layer, and at bottom growth GeSi/Si CS nano wire, wherein GeSi core is that N-shaped doping, Si covering are the doping of P type, as shown in Fig. 2 (c);
Finally, by the SiO of sidewall
2layer etching removed, and exposes the gold grain of sidewall, and then the Si SW nano wire of growing p-type doping, makes Si SW nano wire be connected with the covering of GeSi/Si CS nano wire, as shown in Fig. 2 (d).
Example 2
First, remove silicon SOI substrate top subregional top p-type layer and middle SiO by etching
2insulating barrier, forms a table top (table top bottom is N-shaped silicon, and table top sidewall is p-type silicon), as shown in Fig. 2 (a);
Secondly, nickel plating film on table top, forms nano nickel particles after annealing; Then one deck SiON layer of growing on table top, covers the nickel particle of table top bottom and sidewall, as shown in Fig. 2 (b);
Then remove the SiON layer of table top bottom by photoetching and etching technics, at table top bottom growing GaN/InGaN/AlGaN CS nano wire, wherein GaN core is that N-shaped doping, InGaN covering undope, AlGaN covering is the doping of P type, as shown in Fig. 2 (c);
Finally, the SiON layer etching of sidewall removed, expose the nickel particle of sidewall, then the GaN SW nano wire of growing p-type doping, makes GaN SW nano wire be connected with the AlGaN covering of GaN/InGaN/AlGaN CS nano wire, as shown in Fig. 2 (d).
Example 3
First, remove silicon SOI substrate top subregional top p-type layer and middle SiO by etching
2insulating barrier, forms a table top (table top bottom is N-shaped silicon, and table top sidewall is p-type silicon), as shown in Fig. 2 (a);
Secondly, one deck SiO grows on table top
2layer, covers table top bottom and sidewall, then removes the SiO of table top bottom by photoetching and etching technics
2layer; Then at table top bottom self-catalysis growing GaN/InGaN/AlGaN CS nano wire, wherein GaN core is that N-shaped doping, InGaN covering undope, AlGaN covering is the doping of P type, as shown in Fig. 3 (a);
Finally, by the SiO of table top sidewall
2layer etching removed, and then the GaN SW nano wire of self-catalysis growing p-type doping on sidewall, makes GaN SW nano wire be connected with the AlGaN covering of GaN/InGaN/AlGaAs CS nano wire, as shown in Fig. 3 (b).
Example 4
First, on GaAs substrate (intermediate layer is NPN doped structure), by top p-type layer and the middle NPN layer in etching remove portion region, (table top bottom is N-shaped GaAs to form a table top, table top sidewall is p-type GaAs), as shown in Fig. 4 (a);
Secondly, at table top bottom gold coated films, after annealing, form golden nano particle, then at table top bottom growth GaAs/InGaAs/AlGaAs CS nano wire, wherein GaAs core is that N-shaped doping, InGaAs covering undope, AlGaAs covering is the doping of P type, as shown in Fig. 4 (b);
Then the InAs nano wire of continued growth P type doping, because the lattice constant of InAs and GaAs material is widely different, InAs nano wire can have been fallen and along lateral growth, final InAs nano wire is connected with sidewall, as shown in Fig. 4 (c); Finally, prepare metal electrode at substrate back and mesa top, as two electrodes of CS nano-wire devices.
The above is know-why and instantiation that the present invention applies, the equivalent transformation doing according to conception of the present invention, as long as when its scheme of using does not exceed spiritual that specification and accompanying drawing contain yet, and all should be within the scope of the invention, explanation hereby.
Claims (8)
1. one kind has the electrode preparation method of " core-covering " structure nanometer wire device, it is characterized in that: in the Semiconductor substrate with mesa structure, there is the nano wire of " core-covering " structure as substrate grown using table top bottom, the covering of this nano wire is realized with being electrically connected by the side direction nano wire of subsequent growth of table top sidewall, described Semiconductor substrate contains intermediate insulating layer, and the doping type of substrate top is different from the doping type of substrate bottom.
2. one according to claim 1 has the electrode preparation method of " core-covering " structure nanometer wire device, it is characterized in that: described side direction nano wire, be sidewall using table top as substrate, thereby and " core-covering " structure nanometer wire interconnection of lateral growth and the growth of table top bottom.
3. one according to claim 1 has the electrode preparation method of " core-covering " structure nanometer wire device, it is characterized in that: described side direction nano wire, be covering using " core-covering " structure nanometer wire as substrate, thereby and lateral growth be connected with table top sidewall.
4. one according to claim 1 has the electrode preparation method of " core-covering " structure nanometer wire device, it is characterized in that: described side direction nano wire, be that the covering of " core-covering " structure nanometer wire and table top sidewall are linked up, thereby realize being electrically connected between the covering of nano-wire devices and table top sidewall.
5. one according to claim 1 has the electrode preparation method of " core-covering " structure nanometer wire device, it is characterized in that: described table top, obtain by etching semiconductor substrate, the doping type of its table top sidewall is different with the doping type of table top bottom, wherein, by the mode of metal-coated films after annealing or metallizing particle colloidal sols, at bottom and the side attachment metallic particles of table top, as catalyst guiding nanowire growth.
6. one according to claim 1 has the electrode preparation method of " core-covering " structure nanometer wire device, it is characterized in that: described intermediate insulating layer is SiO
2insulating barrier or there is the semiconductor lamella of NPN doped structure.
7. one according to claim 1 has the electrode preparation method of " core-covering " structure nanometer wire device, it is characterized in that: described " core-covering " structure nanometer wire device, and its electrode preparation is in substrate bottom and substrate top; Wherein the electrode of substrate bottom is connected with the core of " core-covering " nano wire, the electrode of substrate top is connected with the covering of " core-covering " nano wire by side direction nano wire, wherein the doping type of core segment is identical with the doping type of table top bottom, and the doping type of covering is identical with the doping type of table top sidewall.
8. one according to claim 1 has the electrode preparation method of " core-covering " structure nanometer wire device, it is characterized in that: described substrate and nano-material are selected from IV family, II-VI family and III-V family material, wherein backing material is any in Si, GaAs and InP, and nano-material is any in Si, GeSi, ZnO, GaAs, AlInGaAsP, InP, GaN, AlInGaN and InGaSb.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201110144804.5A CN102259833B (en) | 2011-05-24 | 2011-05-24 | Preparation method of nano wire device based on nano wire cross connection |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201110144804.5A CN102259833B (en) | 2011-05-24 | 2011-05-24 | Preparation method of nano wire device based on nano wire cross connection |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN102259833A CN102259833A (en) | 2011-11-30 |
| CN102259833B true CN102259833B (en) | 2014-11-05 |
Family
ID=45006708
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201110144804.5A Active CN102259833B (en) | 2011-05-24 | 2011-05-24 | Preparation method of nano wire device based on nano wire cross connection |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN102259833B (en) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107195533B (en) * | 2017-05-12 | 2019-07-19 | 华南师范大学 | A kind of multiterminal electronic device preparation method based on GaN horizontal nanowire cross knot |
| CN107805780A (en) * | 2017-09-05 | 2018-03-16 | 上海师范大学 | A kind of preparation method of the nano-device based on nano-electrode |
| CN113948604B (en) * | 2021-10-18 | 2024-05-17 | 中国科学院长春光学精密机械与物理研究所 | Three-dimensional structure high-gain AlGaN solar blind ultraviolet detector and preparation method thereof |
Family Cites Families (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP2360298A3 (en) * | 2000-08-22 | 2011-10-05 | President and Fellows of Harvard College | Method for depositing a semiconductor nanowire |
| JP3823784B2 (en) * | 2001-09-06 | 2006-09-20 | 富士ゼロックス株式会社 | Nanowire and manufacturing method thereof, and nanonetwork using the same, manufacturing method of nanonetwork, carbon structure, and electronic device |
| EP1700336A1 (en) * | 2003-12-23 | 2006-09-13 | Koninklijke Philips Electronics N.V. | Semiconductor device comprising a heterojunction |
| CN101443887B (en) * | 2006-03-10 | 2011-04-20 | Stc.Unm公司 | Pulsed growth of GAN nanowires and applications in group III nitride semiconductor substrate materials and devices |
| WO2010048127A2 (en) * | 2008-10-20 | 2010-04-29 | The Regents Of The University Of Michigan | A silicon based nanoscale crossbar memory |
-
2011
- 2011-05-24 CN CN201110144804.5A patent/CN102259833B/en active Active
Also Published As
| Publication number | Publication date |
|---|---|
| CN102259833A (en) | 2011-11-30 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US8030108B1 (en) | Epitaxial growth of in-plane nanowires and nanowire devices | |
| US9287443B2 (en) | Nanostructured device | |
| CN104145340B (en) | Nanowire device with graphene top electrodes and bottom electrode and the method for manufacturing the device | |
| CN1898803A (en) | Semiconductor device comprising a heterojunction | |
| US9741895B2 (en) | Removal of 3D semiconductor structures by dry etching | |
| US8273983B2 (en) | Photonic device and method of making same using nanowires | |
| CN112020762B (en) | Enhanced thin film device | |
| US8183566B2 (en) | Hetero-crystalline semiconductor device and method of making same | |
| US20070120254A1 (en) | Semiconductor device comprising a pn-heterojunction | |
| US20120199187A1 (en) | Nanowire tunnel diode and method for making the same | |
| CA2741397A1 (en) | Nanostructures and methods for manufacturing the same | |
| CN114207778A (en) | Nanowire device | |
| Yao et al. | Facile five-step heteroepitaxial growth of GaAs nanowires on silicon substrates and the twin formation mechanism | |
| CN102050426B (en) | Method for preparing heterogeneous nanowire | |
| CN102259833B (en) | Preparation method of nano wire device based on nano wire cross connection | |
| US20140361244A1 (en) | Nanowire LED Structure with Decreased Leakage and Method of Making Same | |
| US9196792B2 (en) | Nanowire LED structure with decreased leakage and method of making same | |
| JP6232611B2 (en) | LIGHT EMITTING ELEMENT AND MANUFACTURING METHOD THEREOF | |
| KR20230064222A (en) | Method for manufacturing compound semiconductor nano-rod, compound semiconductor nano-rod and compound smiconductor nano-rod array manufactured by using the same | |
| Samuelson | Semiconductor nanowires as a bottom-up approach to realize nanoelectronic and nanophotonic devices |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| TR01 | Transfer of patent right | ||
| TR01 | Transfer of patent right |
Effective date of registration: 20200601 Address after: 2201, building C3, Nanshan Zhiyuan, No. 1001, Xueyuan Avenue, Changyuan community, Taoyuan Street, Nanshan District, Shenzhen City, Guangdong Province Patentee after: Shenzhen gansheng Technology Co.,Ltd. Address before: 116024 Innovation Park building, 2 Polytechnic Road, Ganjingzi District, Liaoning, Dalian, A328 Co-patentee before: Canal wave Patentee before: Huang Hui |
|
| TR01 | Transfer of patent right | ||
| TR01 | Transfer of patent right |
Effective date of registration: 20220902 Address after: Room 601, building 4, Shenzhen new generation industrial park, 136 Zhongkang Road, Meidu community, Meilin street, Futian District, Shenzhen, Guangdong 518000 Patentee after: SHENZHEN MICRO & NANO INTEGRATED CIRCUITS AND SYSTEMS Research Institute Address before: Room 2201, Building C3, Nanshan Zhiyuan, No. 1001, Xueyuan Avenue, Changyuan Community, Taoyuan Street, Nanshan District, Shenzhen, Guangdong 518000 Patentee before: Shenzhen gansheng Technology Co.,Ltd. |