CN102236622A - Dynamic memory controller and method for increasing bandwidth utilization rate of dynamic memory - Google Patents
Dynamic memory controller and method for increasing bandwidth utilization rate of dynamic memory Download PDFInfo
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- CN102236622A CN102236622A CN2010101653859A CN201010165385A CN102236622A CN 102236622 A CN102236622 A CN 102236622A CN 2010101653859 A CN2010101653859 A CN 2010101653859A CN 201010165385 A CN201010165385 A CN 201010165385A CN 102236622 A CN102236622 A CN 102236622A
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Abstract
The invention provides a dynamic memory controller and method for increasing the bandwidth utilization rate of a dynamic memory. The method comprises the following steps: the dynamic memory controller receives and stores an access request of each access port while transmitting an operating instruction transmitted to the dynamic memory and transmits a next stored operating instruction to the dynamic memory after the transmission of the operating instruction which is being transmitted is finished. By adopting the technical scheme provided by the invention, the technical problem of low bandwidth utilization rate of the dynamic memory in the prior art can be effectively solved.
Description
Technical field
The present invention relates to dynamic storage DRAM (Dynamic Random Access Memory) controller, be specifically related to a kind of dynamic storage controller and method that improves the dynamic storage bandwidth availability ratio.
Background technology
The dram controller synoptic diagram as shown in Figure 1, controller comprises two parts interface: to the interface of access port; To the dram chip interface.
Controller is subjected to its condition restriction when DRAM is carried out read-write operation, need after sending read/write address through reading data or write from DRAM behind the fixing delay requirement.With DDR3-800 is example, and for the DDR3-800 device, under the 400M clock, sending needs behind the read/write address could read data or write from DDR3 SDRAM after 5 clock period time-delays at least.And since DDR3 SDRAM at every turn in same Bank (unit), during the line feed read-write operation, need close the row of having opened among the current Bank (Precharge) earlier, activate the row (Active) that needs visit then, then could be to the line data read-write operation of advancing of needs visit.In each Bank, Precharge has a fixing delay requirement (TRP) between the Active operation.TRP is at least 12.5ns.After sending read/write address like this, will be longer the delay time that data are read or write from DDR3 SDRAM.
For access port by dram controller when the DRAM request msg, if access port is read data or is write from DRAM after, access port initiates DRAM to be carried out read-write operation by dram controller more next time, access port is after distributing read/write address for the first time like this, in all from DRAM, reading or write during this period of time to data, not to the DRAM read-write operation, cause the DRAM bandwidth availability ratio lower.
In order to improve the bandwidth availability ratio of DRAM, existing solution mainly comprises two kinds:
1, Bank by turns.This method needs to switch Bank after each Burst (burst) operation, under the prerequisite that guarantees the data bus high usage, the interval of adjacent twice visit of each Bank is strengthened as far as possible.There is open defect in this method: one, and access port is at random to the address of the read-write operation of DRAM, so can't guarantee that each Burst operation all is different Bank; Two, need do address administration and make each Burst operation switch Bank afterwards, hardware circuit is complicated high, and is portable poor.
2, Precharge operation in advance.This method is if next operation will need Precharge Active then, and does not conflict with this operation, so, just this Precharge operation is advanceed to this operation and carrying out before.After this operation was finished, in the time of carrying out the Active operation of operation next time, the TRP time had satisfied.Still there is deficiency in the result who does so: the precondition that this method is used will need Precharge Active then as next operation, and and this operation does not conflict, but in practice because the randomness of reference address makes that the probability that reaches this precondition is lower.
Summary of the invention
The technical problem to be solved in the present invention provides a kind of dynamic storage controller and method that improves the dynamic storage bandwidth availability ratio, can effectively solve the low technical matters of dynamic storage bandwidth availability ratio in the prior art.
The invention provides a kind of method that improves the dynamic storage bandwidth availability ratio, comprising:
Dynamic storage controller sends next operational order of storage in the request of access that receives and store each access port to described dynamic storage after the operational order transmission that is sending finishes in dynamic storage transmit operation instruction.
Further, described dynamic storage controller does not need when dynamic storage sends next operational order to wait for that the data that data that the operational order that sent need write write described dynamic storage fully or the operational order that sent need be asked read fully from dynamic storage.
Further, described dynamic storage controller receives the request msg that described dynamic storage returns;
Described dynamic storage controller also is sent to corresponding access port with the described request data that receive when dynamic storage transmit operation instruction and receiving the request of access of access port.
Further, described dynamic storage controller receives and the request of access of memory access port is meant,
Dynamic storage controller is stored each request of access according to the sequencing of receiving request of access and is formed the operational order formation, also the sequencing storage according to write operation will write the data of dynamic storage when request of access is write operation, and also generates indication information and store described indication information according to the sequencing of read operation when request of access is read operation;
Each operational order of described storage comprises start address, visit length and the action type of the dynamic storage of visit;
Each indication information of described storage comprises visit length and access number.
Further, described dynamic storage controller setting operation instruction counter, its initial value is 0, adds 1 when the operational order formation has new operational order to add the hour counter value, counter subtracts 1 after the transmission of the operational order in this formation finishes;
The value that described dynamic storage controller detects the operational order counter becomes at 1 o'clock to dynamic storage transmit operation instruction by 0, and the operational order that detects current transmission sends and finishes and the operational order Counter Value is not to instruct to the dynamic storage transmit operation in 0 o'clock.
Further, described dynamic storage controller also is provided with address counter, be used to write down the address information number that sends to dynamic storage, its initial value is 0, address information of the every transmission of dynamic storage controller then address counter adds 1, clear 0 when the length of the value of address counter and current operational order indication is consistent, the value of address counter is clear to subtract 1 with the operational order queue counter 0 the time when dynamic storage controller detects.
Further, described dynamic storage controller also is provided with the indication information counter, its initial value is 0, when having new indication information to add fashionable indication information Counter Value, the indication information formation adds 1, the indication information counter subtracts 1 after the operation of the indication information in this formation is finished, the value that detects the indication information counter when dynamic storage controller reads the first indication information in the indication information formation when becoming 1 by 0, and finish and the indication information Counter Value reads first indication information in the indication information formation when being not 0 when the data that send according to current indication information send, after receiving the request msg that dynamic storage returns, send request msg to the access port of correspondence according to the described indication information that reads.
Further, described dynamic storage controller also is provided with data counter, be used to write down the data number that dynamic storage sends to dynamic storage controller, its initial value is 0, dynamic storage to data of the every transmission of dynamic storage controller then data counter add 1, clear 0 when the visit length of the value of data counter and current indication information indication is consistent, the value of data counter is clear to subtract 1 with the indication information queue counter 0 the time when dynamic storage controller detects.
Further, described dynamic storage controller comprises the address information that action type and request are visited to dynamic storage transmit operation instruction, also comprises the data that will write when described action type is write operation.
Further, if described dynamic storage controller is received the request of access of a plurality of access ports simultaneously, then according to the priority memory access request of access port, the request of access of the access port that priority is high is positioned at before the request of access of the low access port of priority.
The invention provides a kind of dynamic storage controller that improves the dynamic storage bandwidth availability ratio, comprise arbitration modules, memory module and sending module;
Described arbitration modules is used for receiving the request of access of each access port and request of access being stored to described memory module in sending module transmit operation instruction;
Described sending module is used for to dynamic storage transmit operation instruction, and next operational order that sends storage after the operational order transmission that is sending finishes to described dynamic storage.
Further, described sending module does not need when dynamic storage sends next operational order to wait for that the data that data that the operational order that sent need write write described dynamic storage fully or the operational order that sent need be asked read fully from dynamic storage.
Further, described sending module also is used to receive the request msg that dynamic storage returns, and in dynamic storage transmit operation instruction, the described request data that receive is sent to corresponding access port.
Further, described memory module comprises storage unit 1, storage unit 2 and storage unit 3;
Described arbitration modules receives and the request of access of memory access port is meant: arbitration modules is instructed according to generating run after receiving request of access, and each operational order is stored to described storage unit 1 formation operational order formation according to the sequencing of asking; Arbitration modules will write the data storage of dynamic storage to described storage unit 2 according to the sequencing of write operation when request of access is write operation; Arbitration modules generates indication information when request of access is read operation, and each indication information is stored to described storage unit 3 according to the sequencing of read operation forms the indication information formations;
Each operational order of described storage comprises start address, visit length and the action type of the dynamic storage of visit;
Each indication information of described storage comprises visit length and access number.
Further, described dynamic storage controller also comprises and reads enable module;
Described sending module comprises transmitting element 1;
The described enable module of reading comprises and reads to enable unit 1, and be used for the setting operation instruction counter, its initial value is 0, adds 1 when the operational order formation has new operational order to add the hour counter value, when the operational order in this formation send finish after counter subtract 1; The value that also is used to detect the operational order counter becomes at 1 o'clock to transmitting element 1 and sends by 0 reads enable signal, and finishes and the operational order Counter Value is not read enable signal to transmitting element 1 transmission when being not 0 when the operational order of transmitting element 1 current transmission sends.
Further, describedly read to enable unit 1 and also be used to be provided with address counter, be used to write down the address information number that transmitting element 1 sends to dynamic storage, its initial value is 0, the then described address counter of transmitting element address information of 1 every transmission adds 1, clear 0 when the length of the value of address counter and current operational order indication is consistent, detect when reading to enable unit 1 that the value of address counter is clear to subtract 1 with the operational order queue counter 0 the time.
Further, described dynamic storage controller also comprises and reads enable module;
Described sending module comprises transmitting element 2;
The described enable module of reading comprises and reads to enable unit 2, be used to be provided with the indication information counter, its initial value is 0, when having new indication information to add fashionable indication information Counter Value, the indication information formation adds 1, the indication information counter subtracts 1 after the operation of the indication information in this formation is finished, the value that also is used to detect the indication information counter becomes at 1 o'clock to transmitting element 2 and sends by 0 reads enable signal, and the data that send according to current indication information when transmitting element 2 send and finish and the indication information Counter Value is not read enable signal to transmitting element 2 transmissions when being not 0;
Described transmitting element 2 is received and is read to obtain first indication information behind the enable signal from the indication information formation, and the request msg that dynamic storage returns is sent to the access port of correspondence according to the indication of the indication information that obtains.
Further, describedly read to enable unit 2 and also be used to be provided with data counter, the data number that the record dynamic storage sends to dynamic storage controller, its initial value is 0, dynamic storage to data of the every transmission of dynamic storage controller then data counter add 1, clear 0 when the visit length of the value of data counter and current indication information indication is consistent, detect when reading to enable unit 2 that the value of data counter is clear to subtract 1 with the indication information queue counter 0 the time.
Further, if described arbitration modules is received the request of access of a plurality of access ports simultaneously, then according to the priority memory access request of access port, the request of access of the access port that priority is high is positioned at before the request of access of the low access port of priority.
Further, described transmitting element 1 receive read enable signal after transmit operation instruction, the operational order that transmitting element 1 sends to dynamic storage comprises the address information of action type and request visit, also comprises the data that will write when described action type is write operation.
In sum, the invention provides a kind of dynamic storage controller and method that improves the dynamic storage bandwidth availability ratio, the operational order that dram controller will receive when receiving request of access mails to DRAM, can farthest reduce like this and receive request of access to the delay between the transmit operation instruction, moreover, do not read fully from DRAM when dram controller does not need to wait for the data that data that the operational order that sent need write write DRAM fully or the operational order that sent need be asked when the DRAM transmit operation is instructed, therefore can farthest reduce DRAM from receiving the delay that operational order is written into or reads to data.By above-mentioned means, can make data from DRAM, read or be written into DRAM continuously, thereby can improve the bandwidth availability ratio of dynamic storage.
Description of drawings
Fig. 1 is the application scenarios synoptic diagram of dynamic storage controller;
Fig. 2 is the structural representation of dynamic storage controller of the present invention;
Fig. 3 is the processing flow chart that dynamic storage controller receives request of access in the embodiment of the invention;
Fig. 4 a to Fig. 4 b is the process flow diagram of dynamic storage controller transmit operation instruction in the embodiment of the invention most;
Fig. 5 a to Fig. 5 b is the process flow diagram when dynamic storage controller sends data in the embodiment of the invention.
Embodiment
The purpose of this invention is to provide a kind of dynamic storage controller method for designing, effectively improve access port to the dynamic storage read-write efficiency, extensibility, transplantability are strong.
The invention provides a kind of method that improves the dynamic storage bandwidth availability ratio, dram controller sends next operational order of storage in the request of access that receives and store each access port to DRAM after the operational order transmission that is sending finishes in DRAM transmit operation instruction.
Further, dram controller does not need to wait for that the data that data that the operational order that sent need write write DRAM fully or the operational order that sent need be asked read fully from DRAM when the DRAM transmit operation is instructed.
Further, dram controller is when DRAM device transmit operation instruction and receiving the request of access of access port, and also the request msg that the DRAM that receives is returned is sent to corresponding access port.
Present embodiment provides a kind of dynamic storage controller that improves the dynamic storage bandwidth availability ratio, as shown in Figure 2, comprises arbitration modules, memory module, reads enable module and sending module;
Arbitration modules is used for receiving the request of access of each access port and request of access being stored to described memory module in sending module transmit operation instruction;
Sending module is used for to dynamic storage transmit operation instruction, and next operational order that sends storage after the operational order transmission that is sending finishes to dynamic storage.
Memory module comprises storage unit 1, storage unit 2 and storage unit 3;
Arbitration modules receives and the request of access of memory access port is meant: arbitration modules is instructed according to generating run after receiving request of access, and each operational order is stored to storage unit 1 formation operational order formation according to the sequencing of asking; Arbitration modules will write the data storage of dynamic storage to storage unit 2 formation data queues according to the sequencing of write operation when request of access is write operation; Arbitration modules generates indication information when request of access is read operation, and each indication information is stored to storage unit 3 according to the sequencing of read operation forms the indication information formations; Arbitration modules also is used for finishing the back when request of access storage and returns to the access port of correspondence and ask the response finished.
Each operational order of storage comprises start address, visit length and the action type of the dynamic storage of visit;
Each indication information of storage comprises visit length and access number, can further include read operation numbering (promptly indicating is the read request of which time of corresponding port).
Above-mentioned visit length can be the address size of visit, also can be the data length of visit, and action type is read operation or write operation.
If arbitration modules is received the request of access of a plurality of access ports simultaneously, then according to the priority memory access request of access port, the request of access of the access port that priority is high is positioned at before the request of access of the low access port of priority.
Reading enable module comprises and reads to enable unit 1 and read to enable unit 2;
Read to enable unit 1, be used for sending and read enable signal to transmitting element 1, and the operational order formation of updated stored unit 1, particularly, the setting operation instruction counter, its initial value is 0, when having new operational order to add the hour counter value, the operational order formation adds 1, counter subtracts 1 after the transmission of the operational order in this formation finishes, when reading to enable value that unit 1 detects the operational order counter and become 1, send and read enable signal, and finish and the operational order Counter Value is not read enable signal to transmitting element 1 transmission when being not 0 when the operational order of transmitting element 1 current transmission sends to transmitting element 1 by 0.
Operational order sends to finish and is meant that transmitting element 1 all is sent to DRAM with this operational order corresponding address information herein.
Read to enable unit 1 address counter also is set, be used to write down the address information number that transmitting element 1 sends to DRAM, its initial value is 0, address information of transmitting element 1 every transmission then address counter adds 1, when the length of the value of address counter and current operational order indication is consistent clear 0, detect when reading to enable unit 1 that the value of address counter is clear to subtract 1 with the operational order queue counter 0 the time, and upgrade the operational order formation, be about to push away before the operational order in the operational order formation.
Read to enable unit 2, be used for sending and read enable signal to transmitting element 2, and the indication information formation of updated stored unit 2, particularly, the indication information counter is set, its initial value is 0, when having new indication information to add fashionable indication information Counter Value, the indication information formation adds 1, the indication information counter subtracts 1 after the operation of the indication information in this formation is finished, when reading to enable value that unit 2 detects the indication information counter and become 1, send and read enable signal, and the data that send according to current indication information when transmitting element 2 send and finish and the indication information Counter Value is not read enable signal to transmitting element 2 transmissions when being not 0 to transmitting element 2 by 0.
Read to enable unit 2 data counter also is set, the data number that the record dynamic storage sends to dynamic storage controller, its initial value is 0, dynamic storage to data of the every transmission of dynamic storage controller then data counter add 1, clear 0 when the visit length of the value of data counter and current indication information indication is consistent, detect when reading to enable unit 2 that the value of data counter is clear to subtract 1 with the indication information queue counter 0 the time.
Sending module comprises transmitting element 1 and transmitting element 2;
The operational order that transmitting element 1 sends to dynamic storage comprises the address information of action type and request visit, also comprises the data that will write when action type is write operation.
Transmitting element 1 be receive read to enable unit 1 sends read enable signal after to dynamic storage transmit operation instruction.
Transmitting element 2, be used to receive the request msg that dynamic storage returns, also be used for receiving and read to enable that unit 2 sends reads to obtain first indication information from storage unit 2 behind the enable signal, and the request msg that receives is sent to corresponding access port according to the indication of indication information; First herein indication information is meant the current indication information that ranks the first in the indication information formation.
Transmitting element 2 can be in real time request msg to be sent to access port, it also can be the request msg that first buffer memory receives, then request msg is sent to access port, if first buffer memory, can be to generate a sign according to access port, the request msg of this access port correspondence all comes after this sign, also can be to use different storage unit to store the request msg of different access port.
Present embodiment provides a kind of method that improves the dynamic storage bandwidth availability ratio, comprise: dynamic storage controller sends next operational order of storage in the request of access that receives and store each access port to dynamic storage after the operational order transmission that is sending finishes in dynamic storage transmit operation instruction.
Further, dram controller does not need to wait for that the data that data that the operational order that sent need write write DRAM fully or the operational order that sent need be asked read fully from DRAM when the DRAM transmit operation is instructed.
Further, dram controller is when DRAM device transmit operation instruction and receiving the request of access of access port, and also the request msg that the DRAM that receives is returned is sent to corresponding access port.
Particularly,
Operation when (A) dram controller receives the request of access of each access port is as shown in Figure 3:
Dynamic storage controller is stored each request of access according to the sequencing of receiving request of access and is formed the operational order formation, when request of access is write operation, also to write the data formation data queue of dynamic storage, and when request of access is read operation, also generate indication information and store the formation of indication information formation indication information according to the sequencing of read operation according to the sequencing storage of write operation; Access port to correspondence after this request of access storage is finished returns the response that request is finished.
Each operational order of storage comprises start address, visit length and the action type of the dynamic storage of visit;
Each indication information of storage comprises visit length and access number; This access number can be access port numbering and/or access order numbering.
(B) dram controller is sent to being operating as of DRAM with the operational order of storage when receiving request of access:
First operational order in the dram controller read operation instruction queue, first operational order refer to the current operational order that ranks the first in the operational order formation;
(B1) when operational order is read operation, the DRAM address information that this read operation is related to is sent to DRAM;
(B2) when operational order is write operation, DRAM address information that this write operation is related to and the data that will write are sent to DRAM.
Shown in Fig. 4 a, dram controller setting operation instruction counter, its initial value are 0, add 1 when the operational order formation has new operational order to add the hour counter value, when the operational order in this formation send finish after to the dynamic storage counter subtract 1; Operational order sends to finish and is meant that dram controller all is sent to DRAM with this operational order corresponding address information herein.
The value that dram controller detects the operational order counter becomes at 1 o'clock to DRAM transmit operation instruction by 0, and the operational order that detects current transmission sends and finishes and the operational order Counter Value is not to instruct to the DRAM transmit operation in 0 o'clock.
Shown in Fig. 4 b, dram controller also is provided with address counter, be used to write down the address information number that sends to DRAM, its initial value is 0, address information of the every transmission of dram controller then address counter adds 1, clear 0 when the length of the value of address counter and current operational order indication is consistent, the value of address counter is clear to subtract 1 with the operational order queue counter 0 the time when dram controller detects.
After finishing, this first operational order transmission upgrades the operational order formation, promptly delete the operational order that this has sent, and will push away before the remaining operational order, when the first operational order that is finished is write operation, also upgrade data queue, i.e. deletion has been sent to the data of DRAM, and will push away before the remaining data.
(C) dram controller request msg that DRAM is returned is sent to being operating as of corresponding access port:
Dram controller receives the request msg that DRAM returns;
Shown in Fig. 5 a, dram controller also is provided with the indication information counter, its initial value is 0, when having new indication information to add fashionable indication information Counter Value, the indication information formation adds 1, the indication information counter subtracts 1 after the operation of the indication information in this formation is finished, the value that detects the indication information counter when dram controller reads the first indication information in the indication information formation when becoming 1 by 0, and finish and the indication information Counter Value reads first indication information in the indication information formation when being not 0, and be sent to corresponding access port according to the request msg that DRAM is returned in the indication of this first indication information when the data that send according to current indication information send; First indication information refers to the current indication information that ranks the first in the indication information formation;
Shown in Fig. 5 b, dram controller also is provided with data counter, and is clear 0 when the visit length of the value of data counter and the indication of current indication information is consistent, and the value of data counter is clear to subtract 1 with the indication information queue counter 0 the time when dram controller detects.
When dram controller sends request msg to the access port of correspondence, can be in real time request msg to be sent to access port, it also can be the request msg that first buffer memory receives, then request msg is sent to access port, if first buffer memory, can be to generate a sign according to access port, the request msg of this access port correspondence all comes after this sign, also can be to use different storage unit to store the request msg of different access port.
As seen from the above technical solution provided by the invention, the present invention access port send at every turn dynamic storage the address, write data, reading of data separately, effectively evaded the switching of each operation of access port, need all to wait for that the data of last operation go out or write the end of dynamic storage from dynamic memory read, significantly improved the bandwidth availability ratio of dynamic storage, the hardware logic electric circuit complexity is low simultaneously, to the number of access port without limits, portable and extendability height.
Claims (20)
1. method that improves the dynamic storage bandwidth availability ratio comprises:
Dynamic storage controller sends next operational order of storage in the request of access that receives and store each access port to described dynamic storage after the operational order transmission that is sending finishes in dynamic storage transmit operation instruction.
2. the method for claim 1 is characterized in that, described method also comprises:
Described dynamic storage controller does not need when dynamic storage sends next operational order to wait for that the data that data that the operational order that sent need write write described dynamic storage fully or the operational order that sent need be asked read fully from dynamic storage.
3. method as claimed in claim 1 or 2 is characterized in that, described method also comprises:
Described dynamic storage controller receives the request msg that described dynamic storage returns;
Described dynamic storage controller also is sent to corresponding access port with the described request data that receive when dynamic storage transmit operation instruction and receiving the request of access of access port.
4. method as claimed in claim 3 is characterized in that:
Described dynamic storage controller receives and the request of access of memory access port is meant,
Dynamic storage controller is stored each request of access according to the sequencing of receiving request of access and is formed the operational order formation, also the sequencing storage according to write operation will write the data of dynamic storage when request of access is write operation, and also generates indication information and store described indication information according to the sequencing of read operation when request of access is read operation;
Each operational order of described storage comprises start address, visit length and the action type of the dynamic storage of visit;
Each indication information of described storage comprises visit length and access number.
5. method as claimed in claim 1 or 2 is characterized in that:
Described dynamic storage controller setting operation instruction counter, its initial value is 0, adds 1 when the operational order formation has new operational order to add the hour counter value, counter subtracts 1 after the transmission of the operational order in this formation finishes;
The value that described dynamic storage controller detects the operational order counter becomes at 1 o'clock to dynamic storage transmit operation instruction by 0, and the operational order that detects current transmission sends and finishes and the operational order Counter Value is not to instruct to the dynamic storage transmit operation in 0 o'clock.
6. method as claimed in claim 5 is characterized in that:
Described dynamic storage controller also is provided with address counter, be used to write down the address information number that sends to dynamic storage, its initial value is 0, address information of the every transmission of dynamic storage controller then address counter adds 1, clear 0 when the length of the value of address counter and current operational order indication is consistent, the value of address counter is clear to subtract 1 with the operational order queue counter 0 the time when dynamic storage controller detects.
7. method as claimed in claim 1 or 2 is characterized in that:
Described dynamic storage controller also is provided with the indication information counter, its initial value is 0, when having new indication information to add fashionable indication information Counter Value, the indication information formation adds 1, the indication information counter subtracts 1 after the operation of the indication information in this formation is finished, the value that detects the indication information counter when dynamic storage controller reads the first indication information in the indication information formation when becoming 1 by 0, and finish and the indication information Counter Value reads first indication information in the indication information formation when being not 0 when the data that send according to current indication information send, after receiving the request msg that dynamic storage returns, send request msg to the access port of correspondence according to the described indication information that reads.
8. method as claimed in claim 7 is characterized in that:
Described dynamic storage controller also is provided with data counter, be used to write down the data number that dynamic storage sends to dynamic storage controller, its initial value is 0, dynamic storage to data of the every transmission of dynamic storage controller then data counter add 1, clear 0 when the visit length of the value of data counter and current indication information indication is consistent, the value of data counter is clear to subtract 1 with the indication information queue counter 0 the time when dynamic storage controller detects.
9. method as claimed in claim 1 or 2 is characterized in that:
Described dynamic storage controller comprises the address information that action type and request are visited to dynamic storage transmit operation instruction, also comprises the data that will write when described action type is write operation.
10. method as claimed in claim 4 is characterized in that:
If described dynamic storage controller is received the request of access of a plurality of access ports simultaneously, then according to the priority memory access request of access port, the request of access of the access port that priority is high is positioned at before the request of access of the low access port of priority.
11. a dynamic storage controller that improves the dynamic storage bandwidth availability ratio comprises arbitration modules, memory module and sending module; It is characterized in that:
Described arbitration modules is used for receiving the request of access of each access port and request of access being stored to described memory module in sending module transmit operation instruction;
Described sending module is used for to dynamic storage transmit operation instruction, and next operational order that sends storage after the operational order transmission that is sending finishes to described dynamic storage.
12. dynamic storage controller as claimed in claim 11 is characterized in that:
Described sending module does not need when dynamic storage sends next operational order to wait for that the data that data that the operational order that sent need write write described dynamic storage fully or the operational order that sent need be asked read fully from dynamic storage.
13., it is characterized in that as claim 11 or 12 described dynamic storage controllers:
Described sending module also is used to receive the request msg that dynamic storage returns, and in dynamic storage transmit operation instruction, the described request data that receive is sent to corresponding access port.
14. dynamic storage controller as claimed in claim 13 is characterized in that:
Described memory module comprises storage unit 1, storage unit 2 and storage unit 3;
Described arbitration modules receives and the request of access of memory access port is meant: arbitration modules is instructed according to generating run after receiving request of access, and each operational order is stored to described storage unit 1 formation operational order formation according to the sequencing of asking; Arbitration modules will write the data storage of dynamic storage to described storage unit 2 according to the sequencing of write operation when request of access is write operation; Arbitration modules generates indication information when request of access is read operation, and each indication information is stored to described storage unit 3 according to the sequencing of read operation forms the indication information formations;
Each operational order of described storage comprises start address, visit length and the action type of the dynamic storage of visit;
Each indication information of described storage comprises visit length and access number.
15. dynamic storage controller as claimed in claim 13 is characterized in that:
Described dynamic storage controller also comprises reads enable module;
Described sending module comprises transmitting element 1;
The described enable module of reading comprises and reads to enable unit 1, and be used for the setting operation instruction counter, its initial value is 0, adds 1 when the operational order formation has new operational order to add the hour counter value, when the operational order in this formation send finish after counter subtract 1; The value that also is used to detect the operational order counter becomes at 1 o'clock to transmitting element 1 and sends by 0 reads enable signal, and finishes and the operational order Counter Value is not read enable signal to transmitting element 1 transmission when being not 0 when the operational order of transmitting element 1 current transmission sends.
16. dynamic storage controller as claimed in claim 15 is characterized in that:
Describedly read to enable unit 1 and also be used to be provided with address counter, be used to write down the address information number that transmitting element 1 sends to dynamic storage, its initial value is 0, the then described address counter of transmitting element address information of 1 every transmission adds 1, clear 0 when the length of the value of address counter and current operational order indication is consistent, detect when reading to enable unit 1 that the value of address counter is clear to subtract 1 with the operational order queue counter 0 the time.
17. dynamic storage controller as claimed in claim 13 is characterized in that:
Described dynamic storage controller also comprises reads enable module;
Described sending module comprises transmitting element 2;
The described enable module of reading comprises and reads to enable unit 2, be used to be provided with the indication information counter, its initial value is 0, when having new indication information to add fashionable indication information Counter Value, the indication information formation adds 1, the indication information counter subtracts 1 after the operation of the indication information in this formation is finished, the value that also is used to detect the indication information counter becomes at 1 o'clock to transmitting element 2 and sends by 0 reads enable signal, and the data that send according to current indication information when transmitting element 2 send and finish and the indication information Counter Value is not read enable signal to transmitting element 2 transmissions when being not 0;
Described transmitting element 2 is received and is read to obtain first indication information behind the enable signal from the indication information formation, and the request msg that dynamic storage returns is sent to the access port of correspondence according to the indication of the indication information that obtains.
18. dynamic storage controller as claimed in claim 17 is characterized in that:
Describedly read to enable unit 2 and also be used to be provided with data counter, the data number that the record dynamic storage sends to dynamic storage controller, its initial value is 0, dynamic storage to data of the every transmission of dynamic storage controller then data counter add 1, clear 0 when the visit length of the value of data counter and current indication information indication is consistent, detect when reading to enable unit 2 that the value of data counter is clear to subtract 1 with the indication information queue counter 0 the time.
19. dynamic storage controller as claimed in claim 14 is characterized in that:
If described arbitration modules is received the request of access of a plurality of access ports simultaneously, then according to the priority memory access request of access port, the request of access of the access port that priority is high is positioned at before the request of access of the low access port of priority.
20. dynamic storage controller as claimed in claim 15 is characterized in that:
Described transmitting element 1 receive read enable signal after transmit operation instruction, the operational order that transmitting element 1 sends to dynamic storage comprises the address information of action type and request visit, also comprises the data that will write when described action type is write operation.
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Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102708079A (en) * | 2012-05-15 | 2012-10-03 | 钜泉光电科技(上海)股份有限公司 | Data transmission controlling method and system applied to microcontroller |
| CN104183267A (en) * | 2013-05-20 | 2014-12-03 | 雅马哈株式会社 | Data Processing Apparatus and Memory Apparatus |
| CN104765701A (en) * | 2015-03-24 | 2015-07-08 | 华为技术有限公司 | Data access method and device |
| CN106484531A (en) * | 2016-09-18 | 2017-03-08 | 上海顺久电子科技有限公司 | One memory visit and arbitration method, circuit and device |
| CN108345594A (en) * | 2017-01-22 | 2018-07-31 | 中国移动通信集团安徽有限公司 | Control method, control device and the control system of database access request |
| CN109032503A (en) * | 2018-06-14 | 2018-12-18 | 浙江大华技术股份有限公司 | A kind of flow control method and device of solid state hard disk Data Migration bandwidth |
Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1387644A (en) * | 1999-08-31 | 2002-12-25 | 英特尔公司 | SDRAM controller for parallel processor architecture |
| US6667926B1 (en) * | 2002-09-09 | 2003-12-23 | Silicon Integrated Systems Corporation | Memory read/write arbitration method |
| CN1588552A (en) * | 2004-09-16 | 2005-03-02 | 联合信源数字音视频技术（北京）有限公司 | Control device and method for double speed dynamic random access storage with asynchronous buffer |
| CN1735869A (en) * | 2001-09-27 | 2006-02-15 | 英特尔公司 | Method and apparatus for memory access scheduling to reduce memory access latency |
| CN1815626A (en) * | 2005-01-31 | 2006-08-09 | 上海奇码数字信息有限公司 | Storage access controller and storage access method |
| CN101021819A (en) * | 2007-03-14 | 2007-08-22 | 北京中星微电子有限公司 | Access control method for synchronous dynamic memory and synchronous dynamic memory controller |
| CN101685427A (en) * | 2009-09-02 | 2010-03-31 | 北京龙芯中科技术服务中心有限公司 | Device and method for scheduling dynamic memory on the basis of used time margin |
-
2010
- 2010-04-30 CN CN2010101653859A patent/CN102236622A/en active Pending
Patent Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1387644A (en) * | 1999-08-31 | 2002-12-25 | 英特尔公司 | SDRAM controller for parallel processor architecture |
| CN1735869A (en) * | 2001-09-27 | 2006-02-15 | 英特尔公司 | Method and apparatus for memory access scheduling to reduce memory access latency |
| US6667926B1 (en) * | 2002-09-09 | 2003-12-23 | Silicon Integrated Systems Corporation | Memory read/write arbitration method |
| CN1588552A (en) * | 2004-09-16 | 2005-03-02 | 联合信源数字音视频技术（北京）有限公司 | Control device and method for double speed dynamic random access storage with asynchronous buffer |
| CN1815626A (en) * | 2005-01-31 | 2006-08-09 | 上海奇码数字信息有限公司 | Storage access controller and storage access method |
| CN101021819A (en) * | 2007-03-14 | 2007-08-22 | 北京中星微电子有限公司 | Access control method for synchronous dynamic memory and synchronous dynamic memory controller |
| CN101685427A (en) * | 2009-09-02 | 2010-03-31 | 北京龙芯中科技术服务中心有限公司 | Device and method for scheduling dynamic memory on the basis of used time margin |
Cited By (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102708079A (en) * | 2012-05-15 | 2012-10-03 | 钜泉光电科技(上海)股份有限公司 | Data transmission controlling method and system applied to microcontroller |
| CN102708079B (en) * | 2012-05-15 | 2015-09-30 | 钜泉光电科技(上海)股份有限公司 | Be applied to the method and system of the control data transmission of microcontroller |
| CN104183267A (en) * | 2013-05-20 | 2014-12-03 | 雅马哈株式会社 | Data Processing Apparatus and Memory Apparatus |
| CN104765701A (en) * | 2015-03-24 | 2015-07-08 | 华为技术有限公司 | Data access method and device |
| CN104765701B (en) * | 2015-03-24 | 2018-05-29 | 华为技术有限公司 | Data access method and equipment |
| CN106484531A (en) * | 2016-09-18 | 2017-03-08 | 上海顺久电子科技有限公司 | One memory visit and arbitration method, circuit and device |
| CN106484531B (en) * | 2016-09-18 | 2019-12-24 | 上海顺久电子科技有限公司 | Memory access arbitration method, circuit and device |
| CN108345594A (en) * | 2017-01-22 | 2018-07-31 | 中国移动通信集团安徽有限公司 | Control method, control device and the control system of database access request |
| CN109032503A (en) * | 2018-06-14 | 2018-12-18 | 浙江大华技术股份有限公司 | A kind of flow control method and device of solid state hard disk Data Migration bandwidth |
| CN109032503B (en) * | 2018-06-14 | 2021-04-16 | 浙江大华存储科技有限公司 | Flow control method and device for data migration bandwidth of solid state disk |
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Application publication date: 20111109 |