CN102226891B - Device, system and method for performing memory reference filtering - Google Patents
Device, system and method for performing memory reference filtering Download PDFInfo
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Abstract
The invention provides a device, system and method for performing memory reference filtering, wherein the device for performing the memory reference filtering includes: a first channel which is configured to be programmed with a first scene and store a carry mark; a second channel which is configured to be programmed with a second scene and monitor the carry mark stored in the first channel; a hardware which is configured to receive the mark instruction at some point in the program, respond to the received mark instruction and use a first scene to test the operation after the mark instruction in the program command, respond to the operation period in which the first scene happens in testing the program command after the mark instruction so as to set the carry mark, and use a second scene to monitor the carry mark and respond to that in which the carry mark is monitored by the second scene so as to send a signal notification concession event.
Description
The application is the divisional application of the application for a patent for invention that application number is 200710146938.4, the applying date is on August 21st, 2007, denomination of invention is " technology of execute store reference filtering ".
Technical field
The disclosure relates to the field of calculating and computer system, more particularly, relates to address, instruction, data or other field of quoting of the storer in detection computations machine system.
Background technology
Some computer system operations can adopt the program of reference point (for example " instrument ") annotation, carry out tracking computer program the various of storer are quoted.For example, some computer programs can comprise the instrument code of the address realm of tracking computer program institute access, and some action can be carried out in response to access particular address range.Conventionally, in software program or routine, realize for the memory access of the storage address of comparison program to certain test specification or value and/or carry out the logic of certain function in response to access specific memory scope.
Type, quantity and the frequency of the memory access that can monitor may have been limited due to the expense that for example required with these verifications of operation execution software is associated by software execute store access compare operation.In general, the size increasing for monitoring software program functions such as memory access filtration or monitoring may reduce computer system performance, and expands code size, needs thus larger code storage and the system cost of increase.
Summary of the invention
The device that the invention provides a kind of execute store reference filtering, comprising: first passage, and being configured to programming has the first scene and preserves carry flag; Second channel, is configured to the described carry flag that programming has the second scene to preserve in described first passage with monitoring; Hardware, is configured to be received in the mark instructions of certain point in program, utilizes the operation of described the first scrnario testing mark instructions described in program command after in response to receiving described mark instructions, occurs in and test the operating period after mark instructions described in program command and described carry flag is set, utilizes described in described the second scene monitoring carry flag and in response to utilizing carry flag described in described the second scene monitoring to be set up and signaling yield event in response to described the first scene.
The present invention also provides a kind of system of execute store reference filtering, comprises processor and storer, and wherein, described processor comprises: first passage, and being configured to programming has the first scene and preserves carry flag; Second channel, is configured to the described carry flag that programming has the second scene to preserve in described first passage with monitoring; And hardware, be configured to be received in the mark instructions of certain point in program, utilize the operation of described the first scrnario testing mark instructions described in program command after in response to receiving described mark instructions, occur in and test the operating period after mark instructions described in program command and described carry flag is set, utilizes described in described the second scene monitoring carry flag and in response to utilizing carry flag described in described the second scene monitoring to be set up and signaling yield event in response to described the first scene; And wherein said storer is preserved described mark instructions and the described operation after described mark instructions.
The present invention provides again a kind of method of execute store reference filtering, comprising: to first passage, programming makes it have the first scene; To second channel, programming makes it dispose the second scene to monitor the carry flag in described first passage; Be received in the mark instructions of certain point in program; Utilize the operation of described the first scrnario testing after mark instructions described in program command in response to receiving described mark instructions; In response to described the first scene occurs in the operating period after mark described in test procedure order, described carry flag is set; Utilize carry flag described in described the second scene monitoring; And in response to utilizing carry flag described in described the second scene monitoring to be set up and signaling yield event.
One aspect of the present invention, a kind of device is provided, comprise: the first logic, determine whether one or more memory areas of access and it is responded and causes yield event of memory access operations, described yield event is called interrupt handling routine and is carried out one or more functions in response to the described memory access operations of one or more memory areas described in access.
Another aspect of the present invention, provides a kind of system, comprising: storer, storage mark instruction; Processor, for the access to one or more address realms, the instruction of monitoring after mark instructions described in program command.
Another aspect of the present invention, provides a kind of method, comprising: one or more scenes are programmed in the logical channel of processor; For the first mark watchdog routine to trigger described one or more scene; Response detects the first mark and carries out described one or more scene; If meet described one or more scene, carry out yield event, wherein said one or more scenes comprise and determine whether the first address realm have been carried out to access.
Another aspect of the present invention, provides a kind of machine readable media that stores instruction set thereon, and described instruction set, in the time being carried out by machine, makes described machine carry out the method comprising the following steps: the access of monitored instruction thread to memory area; Access according to response monitoring to described memory area and the information abridged table that generates is revised the performance of described instruction thread.
Brief description of the drawings
In the accompanying drawings as an example instead of restriction the present invention is described.
Fig. 1 illustrates an embodiment of the system of variety of event in monitoring processor.
Fig. 2 is process flow diagram, and the various aspects of at least one embodiment of the present invention are described.
Fig. 3 explanation can be used environment working time being managed of an embodiment therein.
Fig. 4 explanation can be used the shared bus system of at least one embodiment therein.
Fig. 5 explanation can be used the point-to-point bus of at least one embodiment of the present invention therein.
Fig. 6 illustrates the multiple passages that can programme to one or more scenes therein according to an embodiment.
Fig. 7 is process flow diagram, illustrates according to an embodiment for making one or more scenes can monitor the operation of the access to memory area.
Fig. 8 is process flow diagram, and the operation using is in one embodiment described.
Embodiment
Embodiments of the invention relate to computer system.More particularly, at least one embodiment of the present invention relates to and detecting and the technology of filtering access in computer system or the information relevant with memory access.
In one embodiment, can monitor the access to storer by computer program or other logic, and it is responded and carries out various operations by adopting such as the combination of the hardware logic of realizing in the circuit in processor and one or more software instructions.In one embodiment, hardware programmable logic can be used to detect the access of various memory areas or various data values as " passage ", and in response to the access of these detections, carry out function according to the various scenes (scenario) of programming in passage.In one embodiment, the generation of special scenes or scene combination can trigger concession (yield) event of similar fault, carries out function to call processing routine in response to the generation of scene.
Due to for detection of quoting with response storage or the logic of the generation of access realizes in hardware logic, therefore in one embodiment, be responsible for the less expense code of software loading of memory reference/access, allow thus more effectively and with larger performance index to carry out executive software when with software detection and processing memory access/quote.In addition, at least one embodiment allows the more dirigibility of detectable various memory access and quantity, type and the combined aspects quoted.
In one embodiment, while being performed by being included in, make instruction or other code of other instruction in scene detection code in the program that will monitor, the various memory access of the scene of hardware definition in can monitoring software program.For example, in one embodiment, can be in program command, to insert the instruction such as " mark " instruction before the instruction in access memory region or instruction group.After being run into by the processor of working procedure or carrying out this mark, passage or multiple passage corresponding in this processor or other processor can be carried out various compare operations to data, address or out of Memory that comprise or associated with it in the instruction of carrying out after this mark in program command.In addition, if the execution of the instruction in program command after mark meets the condition in passage of being programmed into, this condition can trigger the yield event of similar fault, makes call processing pragram respond and carry out certain function it.
In one embodiment, to the access of linearity or range of physical addresses can by program command by making one or more passages detect this access and it being responded and leading instruction or the instruction group of mark of carrying out certain function carried out access.In other embodiments, can, by one or more passages of carrying out one or more scenes in response to the one or more marks before the instruction of being responsible for storage data or data area in program command being detected, carry out data or the data area of detection of stored to linearity or physical memory address.In addition, in one embodiment, can, by one or more passages of carrying out one or more scenes in response to the one or more marks before being responsible for carrying out the instruction that branch prediction operates being detected in program command, detect the control of transferring to branch target or branch target scope.In other embodiments, can, by programming passage with in response to detecting that the mark in program carries out some scene, detect other memory reference or access.In addition, can be by the scene that be carried out by passage of combination, in one or more passages, detection of stored device is quoted or one or more combinations of access (for example data corresponding with memory access or address).
In one embodiment, area filter technology can be used to allow program threads or other instruction sequence to utilize the global storage region such as " heap ", instead of therein when in the time that the export-oriented program of stack is announced the pointer that points to data easily rewrite data such as " stack " compared with scratchpad area (SPA).More particularly, in one embodiment, a part (" primary part (kindergarten) ") for heap specifically can be distributed to one or more program threads, and no matter whether announce to other program or thread the pointer that points to primary part, because keep the prior art of the pointer (" refuse collection ") that points to heap to be only just applicable to primary part for those threads of the access primary part of having the right.In one embodiment, memory access filtering technique can make thread can adopt heap primary part instead of stack is stored and access information, make thread or multiple thread can avoid the occasional nature of stack, and do not cause the refuse collection expense being associated with whole heap.
Fig. 1 explanation can be monitored the system of the condition of carrying out resource according to an embodiment.In the embodiment in figure 1, carry out the part that resource 105, watch-dog 110 and enable logic 120 form the processor 100 that can carry out instruction.In certain embodiments, carry out resource and can comprise the hardware resource that can be integrated in single component or integrated circuit.But, carry out resource and can comprise the software or the firmware resource that also can be used for execution of program instructions, or any combination of hardware and software and/or firmware.For example, firmware can be used as a part for level of abstraction, or can as software, add function to processing hardware.Software also can be used to the part or all of of dummy instruction collection, or helps in addition to process.
Processor can be to carry out any in the various dissimilar processor of instruction.For example, processor can be that reduction instruction collection calculates (RISC) processor, sophisticated vocabulary calculates (CISC) processor, very long instruction word (VLIW) processor, or any mixing or alternative processor type.In addition, can adopt published technology such as application specific processors such as network or communication processor, coprocessor, flush bonding processor, compression engine, graphic process unit.Along with integrated trend continuation development and processor become more complicated, the monitoring to inner performance index and the needs of reaction may further increase, thereby disclosure technology is more catered to the need.But, due in the technical progress rapidly of this technical field, be difficult to predict all application of disclosed technology, but they are popularized for the complex hardware of executive routine sequence.
As shown in Figure 1, processor 100 is coupled to storage medium 150, as storer.Storage medium 150 can be to have hierarchy memory sub-system at different levels, wherein can include but not limited to the at different levels of cache memory, Nonvolatile memory devices system storages such as dynamic RAM and such as, such as flash memory (memory stick etc.), disk or CD.As shown in the figure, storage medium stores program 160 and handling procedure and/or other thread instruction, as the instruction of service thread 170.In addition, storer can be stored the environment 155 working time being managed, and can carry out the variety of event in resource and develop and optimizer thread or multiple thread in response to monitoring therein.
In order to allow watch-dog 110 to monitor expected event, watch-dog 110 can be coupled to the various piece of carrying out resource, to detect specified conditions or notified some microarchitectural events.Signal wire can be routed to watch-dog 110, or watch-dog can be put together with related resource or integrated with it in strategy.Watch-dog 110 can comprise various FPGA (Field Programmable Gate Array) or software or firmware components.For at least one embodiment, watch-dog 110 is programmed for monitoring and can be used to trigger the composition of matter defining of yield event or one or more architectures or the microarchitectural events that " scene " is associated in architecture.
In one embodiment, be programmed for the logic that realizes scene and be included in hardware corridor, can be separately or in conjunction with for forming the scene more elaborating.In one embodiment, the instruction of scene available software or instruction group are programmed.In addition, in one embodiment, read instruction carry out multiple simple crosscorrelation scenes of storing in multiple passages by execution passage, passage can be logically relevant to another passage.Or watch-dog 110 can pass through hardwired, to detect and specified conditions or the condition group of certain scene relating.
Correspondingly, the system shown in Fig. 1 can be supported one or more architectural events or " yield event ".Yield event moves on to described execution the yield event service routine of passage from current operating instruction circulation.The service routine of passage belongs to the same process/context of current operating instruction stream.When be associated with passage scenario triggered time, signaling yield event.
Watch-dog 110 is followed the tracks of variety of event or condition, and if event or condition that it is programmed to detect occur, signaling is carried out resource 105, so that the conventional control flow that interrupt routine will carry out originally.As shown in Figure 1, interruption can cause calling button.onrelease or thread switching occurs.For at least one alternative, if the event that watch-dog 110 is monitored or condition occur, the not necessarily interruption of the conventional control flow of trigger.But whether one group of architecture state memory element should there is yield event as passage 1300 one or more can be used to instruction in the time that watch-dog 110 detects all conditions of certain scene.That is to say, passage can, through programming, make, in the time a scene being detected, yield event to occur.Satisfied having detected of scene do not have this instruction in passage, even if may can not cause yield event yet.
In one embodiment, processor 100 shown in Fig. 1 comprises one group of passage 1300.Each passage can be specified triggering scene.The triggering of responding scene, yield event handling procedure can record the generation of trigger event, and responds by calling service routine passage service processing program 185 as shown in Figure 1.Yield event handling procedure can be hardware, firmware or software mechanism.
In one embodiment, one or more scenes are programmed in one or more passages, for example, to the in the situation that of the operation access memory area in the program by operating on processor (in high-speed cache or in system storage), generate the concession of similar fault.For example, in one embodiment, scene may be defined to according to the linearity of access or physical address and tests the access to storer first area.As a supplement or substitute, in one embodiment, scene may be defined to the test data of storing in the second address realm.In yet another embodiment, can test and will be stored in storer or the data area of access from storer, and it is responded and triggers yield event.Other detected event that can be low progress indicator can relate to various other microarchitectures or the CONSTRUCTED SPECIFICATION of carrying out resource.
Fig. 1 illustrates that storage medium 150 also can comprise operating system (OS) 180 and passage service processing preset mechanism 185.For at least one embodiment, operating system 180 can relate to user-level thread monitoring as herein described and optimisation technique by minimally.For example, OS 180 can relate to Save and restore context during yield event is processed.Therefore operating system 180 can provide context management service.Channel status can be the contextual part that OS 180 manages.
But at least one embodiment, OS 180 does not relate to transmission yield event.For this embodiment, the yield event that the satisfied triggering of programming scene (being programmed in passage to trigger the composition of matter of yield event) is transmitted via yield event handling procedure in hardware or firmware.For at least one embodiment, for example, triggering the satisfied instruction of scene can tag via hardware.This label can be through processing, to transmit yield event.This processing example is as carried out such as microcode ROM instruction by hardware or the firmware of carrying out resource 105.This hardware or the firmware device of realizing the controls metastasis of yield event is called " yield event processor " sometimes.
Control can be transferred to passage service processing program 185 via yield event handling procedure.Like this, the processing of the scene defining in architecture can directly be carried out by user class code, and has the Min. intervention of OS 180.For so a kind of embodiment, scene condition detects and yield event transmission (comprising controls metastasis) is transparent to OS 180.
But at least one other embodiment, meeting of scene can trigger the software interruption generating in inside, instead of triggers as mentioned above the yield event that hardware transmits.For this embodiment, operating system 180 can be called passage service processing program 185 in the time there is yield event software interruption.
No matter yield event is (hardware and software) how to transmit, yield event all can be processed by user class code.That is to say, under any mode, control and all can be transferred to passage service processing program 185, in fact handling procedure 185 can give user-defined service thread or handling procedure by controls metastasis in response to trigger condition being detected.This controls metastasis has interrupted the execution of the present instruction stream of carrying out in the time there is yield event.In one embodiment, user-defined service thread or handling procedure can comprise and optimize the routine that makes the thread that scene is triggered.In addition, in one embodiment, user-defined service thread or handling procedure can be used to optimize the user class program that causes the scenario triggered of the working time being managed in environment, make to optimize and can carry out in real time.
In the situation that meeting scene, at least one embodiment, can carry out one or more in some functions, comprise and one or more marks are set to indicate various states and/or to generate yield event.For example, in order to monitor therein the first scene of the access to data area or address area and to call another scene in response to triggering, can adopt certain mark, as " carry flag ".In one embodiment, one or more passages are programmed for: 1) carry flag is set but does not cause yield event, or 2) carry flag is set and causes yield event.
In addition, in one embodiment, other mark can be used to other action that expression is taked as carrying out the result of another kind of type scene.For example, in response to trigger access therein instruction pointer scope the first scene and call another scene, can adopt certain mark, as " zero flag ".In one embodiment, one or more passages are programmed for: 1) zero flag is set but does not cause yield event, or 2) zero flag is set and causes yield event.Similarly, in response to trigger access therein branch target address the first scene and call another scene, can arrange certain mark, as " overflow indicator ".For example, in one embodiment, one or more passages are programmed for: 1) overflow indicator is set but does not cause yield event, or 2) overflow indicator is set and causes yield event.
In one embodiment, mark can be embodied as memory block, position in channel logic or that be associated with channel logic in addition.In addition, by the passage being associated with each scene being programmed for after there is corresponding event, suitable mark is set, any amount of scene all can logically be configured to realize combination logic function together.Scene is programmed for the mark of other scene of monitoring, to call scene with suitable order.
Fig. 6 illustrates two passages using the different scenes that link together by mark to programme according to an embodiment.In Fig. 6, passage 601 is carried out the first scene, and responds the generation of that scene and carry flag 605 is set, and it is monitored by the second scene of programming in passage 610.Result is the compound scene of its function that is output as the first and second scenes.In one embodiment, after carrying out the second scene, by concession mark 620 signaling yield event.Handling procedure can be set up and carry out in response to concession mark, and it carries out certain function according to the combination of two kinds of scenes that occur.
In one embodiment, program can comprise mark instructions, with indicate in program special scenes by the access of test specific memory as that of read or write.In one embodiment, mark is to carry out passage that indicating just in program command programming to have scene will start that the instruction of function of monitor subsequent operation or instruction.In other embodiments, mark can comprise except instruction program start by the position of scene monitoring also carry out other function.In certain embodiments, mark can be included in the identical one or more instructions by scene monitoring.
In one embodiment, mark instructions can have following form: " MOD r/m ", wherein " MOD " represents the retouching operation from source address, " r/m " (register/memory address) for example represented by 3 byte oriented operands.In this example, mark does not comprise destination address field (DAF).But in other embodiments, mark can comprise destination address field (DAF), or there is other form.The form (such as operational code etc.) of mark can depend on the particular, instruction set architecture under it at least partly.For example, operand can be from storer or register, as specified with MOD r/m form.
The following describes a series of instructions of carrying out according to one embodiment of present invention memory access that can be monitored:
Sentinel<mode>
Mov<dest>，<src>
In above code sequence, after mark instructions, be memory access instruction.In one embodiment, mark is to being programmed into the instruction of scene in processor internal channel, for the access to first memory address or address realm and the data that are associated with instruction subsequently, monitoring memory access instruction.In other embodiments, for other reason can be monitored instruction subsequently, for example, detect whether store data area into storer by instruction subsequently.
If memory access instruction meets the condition that is programmed into passage or multiple passages, the concession of similar fault may occur, and its responds yield event and calls processing routine and carry out some operation.The operation of being carried out by handling procedure may be different.For example, in one embodiment, handling procedure notifies user certain address realm to be carried out to access.In other embodiments, handling procedure can respond yield event and carry out other abridged table and set up (profiling) or personal code work amendment, discusses after a while a part wherein in the disclosure.Many scenes are programmed in passage, to the trigger condition of yield event is set.In addition, in certain embodiments, one or more scenes are programmed in the one or more passages that logically link together, to detect more complicated scene.
In one embodiment, carry out initialization procedure, wherein the one or more passages in processing hardware are programmed for and detect certain scene, if the first mark wherein detected, memory access operations are subsequently compared as destination address and the address realm of storage instruction.In one embodiment, if the destination address of storage instruction is in certain address realm, hardware flags or other designator can be set, for example, so that the generation of notifying another scene to monitor another condition, the particular data scope corresponding with storage instruction.In this example, the first scene can not cause yield event, and mark or other designator are just set, and code sequence will continue.
In one embodiment, the second scene can be initialized as and detect the generation (as mentioned above) of the first scene, then the scope of the detection data value corresponding with the instruction detecting in the first scene (for example data corresponding with storage instruction within the scope of certain of data value).In one embodiment, if meet the second scene, yield event can occur, and in response to two scenes that meet, calling processor is carried out some operation therein.In above-mentioned example, the first scene is initialized as the destination address that detects the storage instruction in address realm, and its response is arranged to mark, the second scene is initialized as monitoring, to determine and store storage data corresponding to instruction whether within the scope of certain of value or equal particular value, in this case, by the concession of the similar fault of generation calling processor.In other embodiments, other scene can be initialized as and detect the memory access operations corresponding with a series of or concrete memory location and pack other generation of operation into as storer.Like this, at least one embodiment can be used to execute store area filter.
Fig. 2 is process flow diagram, and the operation corresponding with at least one embodiment of the present invention is described.In operation 201, the generation of monitoring the first mark.If the first mark do not detected, procedure operation is proceeded.If the first mark detected, in operation 205, determine that whether memory access operations is corresponding to paid close attention to memory location or memory location scope subsequently.If so,, in operation 210, mark is set to indicate meeting of the first scene.In one embodiment, memory access operations can be the storage instruction with paid close attention to destination address or certain destination address scope subsequently.In other embodiments, memory access operations can be the load corresponding with certain load address or load address scope subsequently.If the first mark detected, if and from the first scene setting this mark, and the data corresponding with memory access operations equal certain value, or drop within the scope of certain of data value, if and other scene that does not depend on previous scenario result in operation 215, there is the concession of similar fault in operation 220, and at operation 225 calling processors.If not from the first scene setting mark, if or the data value corresponding with memory access do not belong to certain value or scope, yield event does not occur, and procedure operation is proceeded.
Embodiment as herein described, applicable to various memory access, comprises access and the access to the memory area corresponding with code branches target etc. carried out by the access packing into or storage operation is carried out storer, by the instruction pointer that points to the various regions of storer.In addition, at least one embodiment can be used to filter address and/or the data value range by instruction, instruction pointer or the access of branch target institute.
If there is the concession of similar fault in above-mentioned example, can carry out any amount of operation by calling processor.For example, in one embodiment, can carry out in response to above-mentioned scene is satisfied various abridged tables and set up operation, make can real time modifying to cause the program of yield event.In one embodiment, can prevent program or the instruction accessing of various memory blocks by this memory block of inexpectancy access by calling program in response to the meeting of one or more scenes of the generation of one or more memory access operations.
For example, in one embodiment, above-described memory area filtering technique can be used to detect software program thread and when attempts being accessed in the object that there is no distribution in its heap primary part, stack or other memory block, and prevents access in the future.In addition,, if pointer may be not announced outside stack, embodiment allows on stack distribution object speculatively.This can save high-speed cache and jolt, and saves the stack access time simultaneously.Or, in one embodiment, allow object to be stored in thread and specifically to pile primary part, make can keep pointing to the pointer of primary part, and primary part is carried out to refuse collection, and do not consider to carry out refuse collection in other region of the heap of thread.In addition, for example, if the primary part corresponding with particular thread or multiple thread carried out to access, at least one embodiment can trigger scene and carrys out processing event, thereby causes the concession of similar fault.
In one embodiment, mark instructions can detect the access to storer, and then triggering a definable will cause the scene of one or more trigger events that similar fault is given way.In at least one embodiment, in fact scene can be included in the multiple scenes that connect to form in logic compound scene according to certain Trigger Function.But in other embodiments, definition in the mark instructions combination that the one or more trigger events that define in one or more scenes can link together in mark instructions or logically, makes to reduce the scene number that mark (or compound token) triggers.
In certain embodiments, except only, to memory area access, mark instructions also can be used to define other parameter.For example, in one embodiment, a mark can be controlled in the time window of wherein being monitored the access to memory area by another mark.For example, the first mark can arrange to another mark and indicate it will start the mark of the access of monitoring to memory area.The first mark can be removed this mark after a while, to stop the access of monitoring to memory area to another mark instruction.
In certain embodiments, as supplementing or substituting mark I/O (I/O) scope that also definable will be monitored memory area.In one embodiment, monitor I/O according to address realm, and in other embodiments, mark can for example, be monitored the access to I/O scope according to each certain combination (" bitmap ") corresponding to the position of different I/O.
Advantageously, one or more embodiment of the present invention can allow user program, the access of the software application for example moving in operating system to processor resource, at least abstractively traditionally according to level of privilege only to OS core can with mode carry out.For example, in one embodiment, user program can adopt mark to monitor the memory access to certain region, and it is responded and carries out and affect highly privileged and process the action of resource such as the privileged resource on " ring 0 " in a kind of processing architecture.The different brackets of other processing architecture definable resource privilege, and can utilize embodiment to forbid or allow these resources of user program access.
In some application that data therein can be shared between concurrent thread, must increase code and additional data structure, to strengthen the exclusive-access to data object, make once to only have a data object that thread access is given.These locking mechanisms produce performance cost.The techniques described herein allow data object to be only grouped into the memory area by a thread access, and their monitoring are from the access of other thread, to guarantee mutual exclusion.
In one embodiment, can come filter store region according to the techniques described herein, to stop accesses protected or " non-locking " data.For example, can be some data of storing in particular thread designated memory, and other data can be used by multiple different threads.Correspondingly, at least one embodiment of the present invention can detect the access of the data to only distributing for particular thread, and stops the access to these " locking " data by undelegated thread.On the contrary, can to allow multiple thread accesses may not be data that particular thread is monopolized or " non-locking " to embodiments of the invention.In this example, be appointed as in the storage space of " thread local " storage space during when object is stored in, can allow thread to use the latch-up-free form of code, and under some environment, only can allow the locking form of thread code to carry out the data in another storage space of access.
Embodiments of the invention also can be used for other application.For example, in security fields, at least one embodiment can be used to monitoring memory access, and calling processor allows user in software, to regulate in real time various security parameters.Specifically; at least one embodiment can be used to prevent from putting code letter or machinery inspection by the rogue's agents modify in same process; prevent that private data structures from being that unauthorized proxy in same process is visible; prevent that data structure from being revised by the unauthorized proxy in same process; or make the authorization code can the shielded structure of access, and without any performance cost.
In one embodiment, can be monitored and detect to the access of those code object such as the accreditation of various programming languages, particularly in the time that access attempt packs into or stores data for the heap of the corresponding outside of access or stack.For example, first passage can be with determining that whether the object address (x) that pack into neither do not distributing to the scene that thread that object packs into specifically piles in scope (r2) yet and programme distributing in the overall situation heap scope (r1) that object packs into.In order to trigger the address of scene to check that object packs into, can in program command, before packing into, object use the first mark instructions.
In the situation of object storage operation, the second mark can be used to trigger the scene being programmed in second channel, whether do not correspond to r2, but the data of object storage (z) still stores r2 into the address (y) of determining object storage.If so, can suppose that object storage just attempting publish data outside its corresponding local heap.
Fig. 7 illustrates according to the process flow diagram of an embodiment.As shown in Figure 7, in operation 700, the condition that monitor is programmed.In operation 705, executable program instructions.In operation 710, can be to event-monitoring tolerance or microarchitecture condition.As shown in Figure 7, if do not trigger generation, method can restart in operation 705.Otherwise, for example, operation 715 (, if triggered), can interrupt processing the processing that causes institute's testing conditions to regulate.And in operation 715, control flow can be transferred to different program parts.
Fig. 8 is process flow diagram, and the operation using is in one embodiment described, wherein monitored object packs into and object storage, to determine whether they have attempted its corresponding software of access and piled outside memory area.In operation 801, if the first mark detected, whether neither distributing in the overall situation heap scope (r1) that object packs into, also not in thread is specifically piled scope (r2) in operation 805, the first scrnario testings address (x) that object packs into subsequently.If so,, in operation 810, can there is yield event, again issue and/or Select None packs into calling processor.If not,, in operation 815, determine whether to detect the second mark, if so,, in operation 820, determine whether the address (y) of object storage does not correspond to r2, but the data of object storage (z) still store r2 into.If so,, in operation 825, there is yield event, so that calling processor is issued again and/or Select None storage.
Except can be used for being managed working time environment the above application, embodiments of the invention also can be used for the alternate manner irrelevant with environment working time being managed.For example, in one embodiment, above-described memory area filtering technique can be used to detect and recover the access to thread special object, or is used for realizing the coherence protocol between memory area or polytype storer.Many other application can utilize embodiment as herein described.
Fig. 3 explanation is monitored and is processed in resource event and adopt institute's monitor event to improve or optimize the system of the user-level software program of moving in architecture according to an embodiment.Specifically, Fig. 3 explanation therein can development of user level software program as the environment 301 working time being managed of application program.In other embodiments, environment 301 can be environment working time of not managing.In one embodiment, by CPU 320 software program for execution, CPU 320 can comprise multiple processing resources, for example polycaryon processor and/or multiple processor.Passage 315 can be set up application programming interface (API) 310 via abridged table and be programmed for monitoring useful event and scene in the time detecting some Performance Characteristics of CPU as code hotspot.Can be programmed into event in passage by explanation by logical OR software 307 and the result of scene detects Performance Characteristics as code hotspot.In addition, also can explain that the concession being programmed in passage moves by detection of code/logic 307, and it is responded and calls suitable handling procedure.
By detecting that logic/code 307 is explained and the performance information that detects can be used for generating by abridged table generating code or logic 303 abridged table of the characteristic of monitoring, then it can convert specific action or method to by abridged table method generating code or logic 305, so as to improve or the code of optimizing the user of the working time being managed in environment as application program.In addition, in one embodiment, can carry out the improvement to personal code work in real time and by thread, and there is detection overhead few or that do not applied by the performance monitoring architecture of Fig. 3.In other embodiments, other grade or functional unit can be used to generate and detect the performance information in CPU and it is responded and the required information of the code of optimizing user.
Fig. 4 explanation can be used Front Side Bus (FSB) computer system of one embodiment of the invention therein.Processor 405 is access data from one-level (L1) cache memory 410 and primary memory 415.In other embodiments of the invention, cache memory can be secondary (L2) high-speed cache, or other storer in computer system memory hierarchy.In addition, in certain embodiments, the computer system of Fig. 4 can comprise L1 high-speed cache and L2 high-speed cache.
Shown in the processor of Fig. 4 is the memory block 406 of machine state.In one embodiment, memory block can be one group of register, and in other embodiments, memory block can be other memory construction.What in Fig. 4, also illustrate is the memory block 407 for conserved domain according to an embodiment.In other embodiments, conserved domain can be arranged in other device or memory construction.Processor can have any amount of processing core.But other embodiments of the invention can as independently realize in bus agent at intrasystem other device, or are distributed in whole system by hardware, software or their certain combination.
Primary memory can be realized by various storages source, for example dynamic RAM (DRAM), hard disk drive (HDD) 420 or the storage source that comprises various memory storages and technology away from computer system location via network interface 430.Cache memory for example can be positioned on, in processor or near processor, on the local bus 407 of processor.
In addition, cache memory can comprise faster storage unit as six transistors (6T) unit, or other storage unit of approximately equal or faster access speed.The computer system of Fig. 4 can be point-to-point (PtP) network of the bus agents such as such as microprocessor, and they communicate via the bus signals that is exclusively used in the each agency on PtP network.Fig. 5 explanation configures with point-to-point (PtP) computer system arranging.Specifically, Fig. 5 illustrates the system that wherein processor, storer and input/output device interconnect by multiple point-to-point interfaces.
The system of Fig. 5 also can comprise some processors, and wherein two processors 570,580 are only shown for simplicity.Processor 570,580 respectively can comprise the local storage controller hub (MCH) 572,582 being connected with storer 22,24.Processor 570,580 can adopt PtP interface circuit 578,588 to carry out swap data via point-to-point (PtP) interface 550.Processor 570,580 respectively can adopt point-to-point interface circuit 576,594,586,598 via each PtP interface 552,554 and chipset 590 swap datas.Chipset 590 also can be via high performance graphics interface 539 and high performance graphics circuit 538 swap datas.Embodiments of the invention can be arranged in any processor with any amount of processing core, or are arranged in PtP bus agent each of Fig. 5.
But other embodiments of the invention can be present in intrasystem other circuit of Fig. 5, logical block or device.In addition, other embodiments of the invention can be distributed on the some circuit shown in Fig. 5, logical block or device.
The processor relating to herein or can be designing to the various stages of manufacturing from being created to simulation according to any other assembly of embodiment of the present invention design.The data that represent design can represent design in several ways.First,, as available in simulation, hardware can adopt hardware description language or another kind of functional description language to represent.As a supplement or substitute, adopt the circuit level model of logic and/or transistor gate to produce in some stage of design process.In addition,, in certain stage, most of design reaches therein them and can come by the data of physical layout that represent various devices the rank of modeling.In the situation of use conventional semiconductor fabrication techniques, the data of indication device placement model can specify in for the production of the various features on the different mask layers of the mask of integrated circuit and exist or non-existent data.
In any expression of design, data can be stored in any type of machine readable media.Through modulation or to generate in addition to transmit the light wave of this information or electric wave, storer or magnetic or optical storage media can be machine readable media such as dish.Any in these media can " be carried " or " instruction " this design, or the out of Memory using in an embodiment of the present invention, as mistake is recovered the instruction in routine.So that while carrying out the copying, cushion or retransmit of electric signal, make new copy when transmitting instruction or the electric carrier wave of carry information.Therefore, the action of communication provider or network provider can be the copy of making goods such as the carrier wave of implementing the technology of the present invention.
Therefore, disclose for handling memory access as the technology that packs into or store.Although describing and some embodiment shown in the drawings, but be appreciated that, these embodiment are explanation instead of the restriction to extensive invention just, and the invention is not restricted to illustrated and described concrete structure and configuration, because those skilled in the art can expect other various amendments after the research disclosure.Rapid development and being difficult in other progressive for example such technical field of prediction therein, promote by realizing technical progress, the disclosed embodiments can be easy to amendment in configuration and details, and do not deviate from the scope of principle of the present disclosure or appended claims.
The each side of one or more embodiment of the present invention can be described, discuss or quote can use in the processor of the one or more embodiment of the present invention or the advertisement of computer system.This series advertisements can include but not limited to newsprint, magazine, billboard or other newspaper or tangible media.Specifically, can advertise on the internet via website, " ejection " advertisement or other media based on WEB in the various aspects of the one or more embodiment of the present invention, and no matter the server that comprises the program that generates website or pop-up advertisement is positioned at the U.S. or its territory.
Claims (15)
1. a device that carries out memory reference filtering, comprising:
The first hardware corridor, being configured to programming has the first scene and preserves carry flag;
The second hardware corridor, is configured to the described carry flag that programming has the second scene to preserve in described the first hardware corridor with monitoring;
Carry out resource hardware, be configured to the mark instructions of certain point in the present instruction stream of the program that is received in; And
Watch-dog hardware, the part that is coupled to described execution resource hardware is to utilize the operation of described the first scrnario testing mark instructions described in program command after and to occur in and test the operating period after mark instructions described in program command and in described the first hardware corridor, described carry flag is set in response to described the first scene in response to receiving described mark instructions
Described watch-dog hardware be used for utilizing described in described the second scene monitoring carry flag and in response to utilizing described in described the second scene monitoring carry flag to be set up signaling yield event so that execution is moved on to Event Service routine from described present instruction circulation.
2. device as claimed in claim 1, wherein said the first scene comprises that the memory access to memory area, the described operation after described mark instructions comprise memory access operations, and tests described memory access operations and comprise and determine that the described memory access operations address of quoting is whether in described memory area.
3. device as claimed in claim 1, wherein said the second hardware corridor is also configured to preserve the mark of giving way, and wherein said watch-dog hardware is also configured to arrange in response to described carry flag is set up described concession mark.
4. device as claimed in claim 1, wherein said yield event is calling processor in response to yield event described in signaling.
5. device as claimed in claim 1, described mark instructions comprises does not have the corresponding instruction that packs destination address into.
6. a system of carrying out memory reference filtering, comprises processor and storer,
Wherein, described processor comprises:
The first hardware corridor, being configured to programming has the first scene and preserves carry flag;
The second hardware corridor, is configured to the described carry flag that programming has the second scene to preserve in described the first hardware corridor with monitoring;
Carry out resource hardware, be configured to the mark instructions of certain point in the present instruction stream of the program that is received in; And
Watch-dog hardware, the part that is coupled to described execution resource hardware is to utilize the operation of described the first scrnario testing mark instructions described in program command after and to occur in and test the operating period after mark instructions described in program command and in described the first hardware corridor, described carry flag is set in response to described the first scene in response to receiving described mark instructions
Described watch-dog hardware be used for utilizing described in described the second scene monitoring carry flag and in response to utilizing described in described the second scene monitoring carry flag to be set up signaling yield event so that execution is moved on to Event Service routine from described present instruction circulation; And
Wherein said storer is for preserving described mark instructions and the described operation after described mark instructions.
7. system as claimed in claim 6, wherein said the first scene comprises that the memory access to memory area, the described operation after described mark instructions comprise memory access operations, and tests described memory access operations and comprise and determine that the described memory access operations address of quoting is whether in described memory area.
8. system as claimed in claim 6, wherein said the second hardware corridor is also configured to preserve the mark of giving way, and wherein said watch-dog hardware is also configured to arrange in response to described carry flag is set up described concession mark.
9. system as claimed in claim 6, wherein said yield event is calling processor in response to yield event described in signaling.
10. system as claimed in claim 6, described mark instructions comprises does not have the corresponding instruction that packs destination address into.
11. 1 kinds are carried out the method for memory reference filtering, comprising:
To first passage, programming makes it have the first scene;
To second channel, programming makes it dispose the second scene to monitor the carry flag in described first passage;
Be received in the mark instructions of certain point in the present instruction stream of program;
Utilize the operation of described the first scrnario testing after mark instructions described in program command in response to receiving described mark instructions;
In response to described the first scene occurs in the operating period after mark instructions described in test procedure order, described carry flag is set;
Utilize carry flag described in described the second scene monitoring; And
In response to utilizing described in described the second scene monitoring carry flag to be set up, signaling yield event is to move on to Event Service routine by execution from described present instruction circulation.
12. methods as claimed in claim 11, wherein said the first scene comprises that the memory access to memory area, the described operation after described mark instructions comprise memory access operations, and tests described memory access operations and comprise and determine that the described memory access operations address of quoting is whether in described memory area.
13. methods as claimed in claim 11, wherein said second channel is also configured to preserve the mark of giving way, and described concession mark is wherein set in response to described carry flag is set up.
14. methods as claimed in claim 11, the wherein calling processor in response to signaling yield event.
15. methods as claimed in claim 11, described mark instructions comprises does not have the corresponding instruction that packs destination address into.
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| US9977725B2 (en) * | 2016-08-26 | 2018-05-22 | Cisco Technology, Inc. | Automatic classification and parallel processing of untested code in a protected runtime environment |
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| US10884662B2 (en) * | 2018-08-06 | 2021-01-05 | Silicon Motion, Inc. | Method for performing storage control in a storage server, associated memory device and memory controller thereof, and associated storage server |
| US11635965B2 (en) | 2018-10-31 | 2023-04-25 | Intel Corporation | Apparatuses and methods for speculative execution side channel mitigation |
| US11080182B2 (en) * | 2019-01-07 | 2021-08-03 | International Business Machines Corporation | Object load introspection using guarded storage |
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| US20050155020A1 (en) * | 2004-01-14 | 2005-07-14 | International Business Machines Corporation | Method and apparatus for autonomic detection of cache "chase tail" conditions and storage of instructions/data in "chase tail" data structure |
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Also Published As
| Publication number | Publication date |
|---|---|
| CN102393823A (en) | 2012-03-28 |
| CN101174223B (en) | 2011-08-10 |
| JP4925973B2 (en) | 2012-05-09 |
| GB0716300D0 (en) | 2007-09-26 |
| HK1120126A1 (en) | 2009-03-20 |
| GB0716036D0 (en) | 2007-09-26 |
| GB0817653D0 (en) | 2008-11-05 |
| US20080046668A1 (en) | 2008-02-21 |
| GB2441216A (en) | 2008-02-27 |
| GB0716299D0 (en) | 2007-09-26 |
| CN102393823B (en) | 2018-05-22 |
| US7769964B2 (en) | 2010-08-03 |
| JP2008071339A (en) | 2008-03-27 |
| GB2441216B (en) | 2009-08-26 |
| DE102007039431A1 (en) | 2008-04-10 |
| CN102226891A (en) | 2011-10-26 |
| CN101174223A (en) | 2008-05-07 |
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