CN102223466A - Monitoring device and floating color eliminating method thereof - Google Patents
Monitoring device and floating color eliminating method thereof Download PDFInfo
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- CN102223466A CN102223466A CN2010101639781A CN201010163978A CN102223466A CN 102223466 A CN102223466 A CN 102223466A CN 2010101639781 A CN2010101639781 A CN 2010101639781A CN 201010163978 A CN201010163978 A CN 201010163978A CN 102223466 A CN102223466 A CN 102223466A
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Abstract
The invention discloses a monitoring device and a floating color eliminating method thereof; the monitoring device provides a pixel scan clock pulse to scan a plurality of scanning lines, and comprises a phase comparer, a clock pulse manager and a timing sequence generator. The phase comparer receives an alternate current power supply signal and a vertical synchronizing signal, compares a phase position of the power supply signal with a phase position of the vertical synchronizing signal, and obtains the phase difference state. The clock pulse manager selects a plurality of scanning lines to be adjusted from the scanning lines according to the phase difference state. The clock pulse manager adjusts pulse width of the pixel scan clock pulse when scanning the scanning lines to be adjusted. The timing sequence generator receives the pixel scan clock pulse and generates the vertical synchronizing signal. According to the method, the phenomenon of color floating can be eliminated.
Description
Technical field
The present invention relates to a kind of monitoring arrangement, and the look that the is particularly related to a kind of monitoring arrangement removing method that wafts.
Background technology
In display system now, (NationalTelevision System Committee, the display frequency of the monitoring arrangement of the image broadcast format of NTSC) being formulated are 59.94 of per seconds (field) to adopt National Television System Committee.And in the environment of fluorescent lamp, the glow frequency of fluorescent lamp then present with its ac supply signal that is received synchronous 60 hertz (Hertz, Hz).Therefore, charge coupled cell (CCD) surround lighting that is received and the display frequency of monitoring arrangement have certain phase difference in the monitoring arrangement.This phase difference then can visually produce the waft phenomenon of (color rolling) of so-called look.
In addition, at line-by-line inversion (Phase Alternating Line, PAL) under the form, though the display frequency of monitoring arrangement and the glow frequency of fluorescent lamp all are set at 50Hz, but because monitoring arrangement is in the operation of reality, some errors still unavoidably appear in the glow frequency of display frequency and fluorescent lamp.Therefore, the so-called look phenomenon of wafing still can't effectively be avoided.
Summary of the invention
The invention provides a kind of monitoring arrangement with and the look removing method that wafts, in order to eliminate because of the environment light frequency and the different looks that produce of frame rate of monitoring arrangement (color rolling) phenomenon of wafing.
The invention provides a kind of monitoring arrangement, this monitoring arrangement provides the picture element scan clock pulse with scanning multi-strip scanning line, comprises phase comparator, clock pulse manager and clock generator.Phase comparator receives power supply signal and the vertical synchronizing signal that exchanges, and compares the phase place of power supply signal and vertical synchronizing signal and obtains the phase difference state.The clock pulse manager couples phase comparator, selectes many according to the phase difference state in scan line and is adjusted scan line.The clock pulse manager is adjusted the pulse bandwidth of picture element scan clock pulse when scan line is adjusted in scanning.Clock generator couples phase comparator and clock pulse manager, receives the picture element scan clock pulse and produces vertical synchronizing signal.
In an embodiment of the present invention, above-mentioned monitoring arrangement is when the phase place of the leading vertical synchronizing signal of phase place of power supply signal, and the clock pulse manager lowers the pulse bandwidth of picture element scan clock pulse when scan line is adjusted in scanning.
In an embodiment of the present invention, above-mentioned monitoring arrangement is when the phase place of the phase lag vertical synchronizing signal of power supply signal, and the clock pulse manager increases the pulse bandwidth of picture element scan clock pulse when scan line is adjusted in scanning.
In an embodiment of the present invention, the above-mentioned scan line of being adjusted is evenly distributed between described multi-strip scanning line according to scanning sequency.
In an embodiment of the present invention, the above-mentioned scan line of being adjusted is distinguished into a plurality of scanline groups of being adjusted, and adjusted scanline groups and be evenly distributed between scan line according to scanning sequency, and the number of scanning lines amount of respectively being adjusted in the scanline groups of being adjusted equates.
In an embodiment of the present invention, above-mentioned clock pulse manager also receives main clock pulse.The pulse bandwidth of picture element scan clock pulse decides for the pulse wave number according to main clock pulse.
In an embodiment of the present invention, above-mentioned phase comparator comprises first trigger, second trigger and arithmetic logic unit.First trigger has clock pulse terminal, data terminal, reset terminal and output, and its data terminal couples reference voltage, and its clock pulse termination is received this power supply signal, and its reset terminal receives reset signal, and its output produces phase lead signal.Second trigger has clock pulse terminal, data terminal, reset terminal and output equally, and its data terminal couples reference voltage, and its clock pulse termination is received vertical synchronizing signal, and its reset terminal receives reset signal, and its output produces the phase lag signal.Arithmetic logic unit couples first and second trigger with receiving phase anticipating signal and phase lag signal.Arithmetic logic unit produces reset signal according to phase lead signal and phase lag signal at its output.
The present invention provides a kind of look of monitoring arrangement removing method that wafts in addition, and monitoring arrangement wherein provides the picture element scan clock pulse with scanning multi-strip scanning line.Its step comprises: at first, receive the power supply signal and the vertical synchronizing signal that exchange, wherein vertical synchronizing signal is to produce according to the picture element scan clock pulse.Then, the phase place of power supply signal and vertical synchronizing signal and obtain the phase difference state relatively.Then, in scan line, select many according to the phase difference state and adjusted scan line, and, when scan line is adjusted in scanning, adjust the pulse bandwidth of picture element scan clock pulse.
Based on above-mentioned, the present invention utilizes the phase difference state that detects between ac supply signal and vertical synchronizing signal, calculate the amplitude that to transfer soon or transfer the frequency of slow picture element scan clock pulse, and select right quantity according to this amplitude and adjusted scan line, adjusted the phase place that the pulse bandwidth that increases or lower the picture element scan clock pulse when scan line is scanned is adjusted vertical synchronizing signal at these.So that the frame rate of monitoring arrangement and environment light frequency can be synchronous, and then eliminate the look phenomenon of wafing.
For above-mentioned feature and advantage of the present invention can be become apparent, embodiment cited below particularly, and conjunction with figs. is described in detail below.
Description of drawings
Fig. 1 illustrates the schematic diagram of the monitoring arrangement 100 of one embodiment of the invention.
Fig. 2 illustrates the schematic diagram of the monitoring arrangement 200 of another embodiment of the present invention.
Fig. 2 A, 2B illustrate the action schematic diagram that clock pulse manager 220 is adjusted the pulse bandwidth of picture element scan clock pulse PCLK respectively.
Fig. 3 illustrates an execution mode of the phase comparator of the embodiment of the invention.
A waft embodiment of removing method of the look that Fig. 4 illustrates the monitoring arrangement of the embodiment of the invention.
Description of reference numerals in the above-mentioned accompanying drawing is as follows:
100,200: monitoring arrangement
110,210: phase comparator
120,220: the clock pulse manager
130,230: clock generator
240: charge coupled cell
250: image processor
260: display
310,320: trigger
330: arithmetic logic unit
331: NAND gate
PD: phase difference state
ACP: power supply signal
VSYNC: vertical synchronizing signal
PCLK: picture element scan clock pulse
MCLK: main clock pulse signal
IMG: view data
L1, L2, L132, L133, L263, L264, L394, L395: adjusted scan line
VDD: reference voltage
D, CK, RST, O: end points
R: reset signal
PD1: phase lead signal
PD2: phase lag signal
S410～S440: the waft step of removing method of look
Embodiment
At first please refer to Fig. 1, Fig. 1 illustrates the schematic diagram of the monitoring arrangement 100 of one embodiment of the invention.Provide picture element scan clock pulse PCLK with scanning multi-strip scanning line (not shown) in the monitoring arrangement 100.Monitoring arrangement 100 comprises phase comparator 110, clock pulse manager 120 and clock generator 130.Phase comparator 110 receives power supply signal ACP and the vertical synchronizing signal VSYNC that exchanges.Phase comparator 110 is according to the phase place that compares power supply signal ACP and vertical synchronizing signal VSYNC and so as to obtaining phase difference state PD.At this, phase difference state PD representative be that the phase place of power supply signal ACP is leading or lags behind the phase place of vertical synchronizing signal VSYNC.
In addition, owing to the phase difference that perhaps only exists between power supply signal ACP and vertical synchronizing signal VSYNC slightly.Therefore, the adjustment of the pulse bandwidth of picture element scan clock pulse PCLK action need not carried out at the time that each scan line is carried out scanning.Clock pulse manager 120 can be set several scan lines of being adjusted in scan line, and when these are adjusted scan line and are scanned, carries out the adjustment action of the pulse bandwidth of picture element scan clock pulse PCLK.
Note that the number of being adjusted scan line can dynamically change.For instance, clock pulse manager 120 can be set the adjustment action that scan line (for example being 4) carries out the pulse bandwidth of picture element scan clock pulse PCLK of being adjusted of lesser amt earlier.Do not change if adjust back phase difference state PD, then represent the insufficient amplitude of adjustment, clock pulse manager 120 can correspondingly increase to set is adjusted scan line (for example being 8).
In addition, when the phase place of the leading vertical synchronizing signal VSYNC of phase place of phase difference state PD display power supply signal ACP, clock pulse manager 120 correspondences are adjusted and reduced the pulse bandwidth of picture element scan clock pulse PCLK.Relative, when the phase place of the backwards vertical synchronizing signal VSYNC of phase difference state PD display power supply signal ACP, clock pulse manager 120 corresponding accent increase the pulse bandwidths of picture element scan clock pulse PCLK.
When to be adjusted scan line and scan in order to lower, cause the decline of display quality because of the change of the pulse bandwidth of picture element scan clock pulse PCLK, being adjusted the selected of scan line can be to be evenly distributed between scan line according to scanning sequency.With adjusted scan line equal 4 and all scan line have 56 to be example, adjusted scan line and can be chosen to be the 1st, 15,29 and 43 scan line.If being adjusted scan line equals 8, adjusted scan line and can be chosen to be the 1st, 8,15,22,29,36,43 and 50 scan line.
In addition, adjusted scan line and also can on average be distinguished into a plurality of scanline groups of being adjusted, these adjusted scanline groups then by mean allocation between scan line.Equally with adjusted scan line equal 8 and all scan line have 56 to be example, adjusted scan line can be assigned as 4 and adjusted scanline groups, wherein respectively adjusted scanline groups and comprise two and adjusted scan line.Being adjusted scanline groups for 4 all is distributed in 56 scan lines.Adjusted scan line for these 8 and be respectively the 1st, 2 scan line, the 15th, 16 scan line, the 29th, 30 scan line and the 43rd, 44 scan line.
130 of clock generators are in order to receive picture element scan clock pulse PCLK and to produce vertical synchronizing signal VSYNC according to this.Because the pulse bandwidth of picture element scan clock pulse PCLK is adjusted according to phase difference state PD when being adjusted scan line and scan.Therefore, show single corresponding being changed of time cycle.That is to say that the phase place of vertical synchronizing signal VSYNC also is changed simultaneously.
Below please refer to Fig. 2, Fig. 2 illustrates the schematic diagram of the monitoring arrangement 200 of another embodiment of the present invention.Monitoring arrangement 200 comprises phase comparator 210, clock pulse manager 220, clock generator 230, charge coupled cell 240, image processor 250 and display 260.Inequality with last embodiment, clock pulse manager 220 receives main clock pulse signal mCLK in addition, and adjusts the pulse bandwidth of its picture element scan clock pulse PCLK that produces according to this main clock pulse signal mCLK.Usually, main clock pulse signal mCLK is 2 frequencys multiplication or 3 frequencys multiplication of picture element scan clock pulse PCLK.That is to say, be that 2 frequencys multiplication of picture element scan clock pulse PCLK are example with main clock pulse signal mCLK, picture element scan clock pulse PCLK just, the epiphysis wave width, all just equal the one-period of main clock pulse signal mCLK.
When the pulse bandwidth that carries out picture element scan clock pulse PCLK when being adjusted scan line and be scanned at clock pulse manager 220 was adjusted, the periodicity of main clock pulse signal mCLK that just changes the pulse bandwidth correspondence of picture element scan clock pulse PCLK was adjusted.If originally picture element scan clock pulse PCLK just, the epiphysis wave width, when all just equaling the one-period of main clock pulse signal mCLK, the positive pulse bandwidth (or the negative pulse bandwidth of change) that transfer the pulse bandwidth of wide picture element scan clock pulse PCLK then to change picture element scan clock pulse PCLK equals the length in the cycle of main clock pulse signal mCLK below two and gets final product.In like manner, in the time of downgrading the pulse bandwidth of picture element scan clock pulse PCLK, then downgrade the periodicity of one of them corresponding main clock pulse signal mCLK at least of the positive and negative pulse bandwidth of picture element scan clock pulse PCLK.
Thus, clock pulse manager 220 can just can be implemented easily by simple digital circuit.No matter cost or complexity at circuit can effectively reduce, and then promote product advantage.And utilize digital circuit to realize that clock pulse manager 220 is techniques well known, does not give unnecessary details for this reason at this.
230 of clock generators receive picture element scan clock pulse PCLK and produce charge coupled cell 240 needed clock pulse signals according to this.Charge coupled cell 240 is sent to image processor 250 with the view data IMG that is sensed and handles, and demonstrates the image that charge coupled cell 240 is sensed by display 260.
Below please respectively with reference to Fig. 2 A, 2B, Fig. 2 A, 2B illustrate the action schematic diagram that clock pulse manager 220 is adjusted the pulse bandwidth of picture element scan clock pulse PCLK respectively.
Please earlier with reference to Fig. 2 A, with each display frame (frame) 525 scan lines are arranged, it is example that every scan line has 1820 pixels.When display frame 271, before the pulse bandwidth of picture element scan clock pulse PCLK is not adjusted, system in alternating expression (interlace) scanning, and a rate (field rate) is under the situation of 59.94Hz, the frequency of picture element scan clock pulse PCLK equals 1820 * 525/2 * 59.94=28.636363 MHz (MHz) (in the sweep time of each scan line, all pulsewidths of picture element scan clock pulse PCLK, the cycle of the main clock pulse signal mCLK by 1820 is formed).
Then, when display frame 272, selected the 1st, 132,263 and 394 scan line L1, L132, L263 and L394 are adjusted all pulsewidths of picture element scan clock pulse PCLK and are made up of the cycle of 1821 main clock pulse signal mCLK when respectively being adjusted scan line for adjusting scan line.Thus, frequency at fixed pixel scan clock pulse PCLK is under the situation of 28.636363MHz, field rate=28636363/ that shows (1821 * 4+1820 * (525/2-4)=59.825Hz, than the field rate of display frame 271 slow 59.94-59.9395=0.0004Hz.
In addition, when display frame 273, selected the 1st, 2,132,133,263,264 and 394,395 scan line L1, L2, L132, L133, L263, L264 and L394, L395 are adjusted all pulsewidths of picture element scan clock pulse PCLK equally and are made up of the cycle of 1821 main clock pulse signal mCLK when respectively being adjusted scan line for adjusting scan line.Thus, be under the situation of 28.636363MHz in the frequency of fixed pixel scan clock pulse PCLK, the field rate of demonstration than the field rate of display frame 271 slow 0.0009Hz.
Then please refer to Fig. 2 B, in the example identical with Fig. 2 A, when display frame 282, selected the 1st, 132,263 and 394 scan line L1, L132, L263 and L394 are adjusted all pulsewidths of picture element scan clock pulse PCLK and are made up of the cycle of 1819 main clock pulse signal mCLK when respectively being adjusted scan line for adjusting scan line.Thus, frequency at fixed pixel scan clock pulse PCLK is under the situation of 28.636363MHz, field rate=28636363/ that shows (1819 * 4+1820 * (525/2-4))=59.9405Hz, than the fast 59.9405-59.94=0.0005Hz of field rate of display frame 271.
In addition, when display frame 273, selected the 1st, 2,132,133,263,264 and 394,395 scan line L1, L2, L132, L133, L263, L264 and L394, L395 are adjusted all pulsewidths of picture element scan clock pulse PCLK equally and are made up of the cycle of 1821 main clock pulse signal mCLK when respectively being adjusted scan line for adjusting scan line.Thus, be under the situation of 28.636363MHz in the frequency of fixed pixel scan clock pulse PCLK, the field rate of demonstration than the field rate of display frame 271 fast 0.001Hz.
With the next Fig. 3 that please refer to, Fig. 3 illustrates an execution mode of the phase comparator of the embodiment of the invention.In the illustrating of Fig. 3, phase comparator 300 comprises trigger 310,320 and arithmetic logic unit 330.Trigger 310,320 all has clock pulse terminal CK, data terminal D, reset terminal RST and output O.The data terminal D of trigger 310 couples reference voltage V DD, and its clock pulse terminal CK receives power supply signal ACP, and its reset terminal RST receives reset signal R, and its output O produces phase lead signal PD1.The data terminal D of trigger 320 couples reference voltage V DD, and its clock pulse terminal CK receives vertical synchronizing signal VSYNC, and its reset terminal RST receives reset signal R, and its output produces phase lag signal PD2.Arithmetic logic unit 330 couples trigger 310,320 with receiving phase anticipating signal PD1 and phase lag signal PD2.Arithmetic logic unit 330 produces reset signal R according to phase lead signal PD1 and phase lag signal PD2 at its output.In the present embodiment, arithmetic logic unit 330 is a NAND gate 331.
On the action details, when the phase place of the leading vertical synchronizing signal VSYNC of phase place of power supply signal ACP, the output O of trigger 310 can produce the phase lead signal PD1 of logic high (being equal to reference voltage V DD) earlier.And when the vertical synchronizing signal VSYNC transition that falls behind when phase place, the output of trigger 320 just can produce the phase lag signal PD2 of logic high.Note that the output of arithmetic logic unit 330 at the same time can produce the reset signal R of logic low, and and then reset flip-flop 310,320.That is to say that phase lag signal PD2 only can just disappear at once in of short duration appearance, phase lead signal PD1 then can produce an effective pulse signal.
Relative, when the phase place of the phase lag vertical synchronizing signal VSYNC of power supply signal ACP, the output O of trigger 320 can produce the phase lag signal PD2 of logic high (being equal to reference voltage V DD) earlier.And when the vertical synchronizing signal VSYNC transition that falls behind when phase place, the output of trigger 320 just can produce the phase lead signal PD1 of logic high.Note that the output of arithmetic logic unit 330 at the same time can produce the reset signal R of logic low, and and then reset flip-flop 310,320.That is to say that phase lead signal PD1 only can just disappear at once in of short duration appearance, phase lag signal PD2 then can produce an effective pulse signal.
That is to say that as long as observe phase lead signal PD1 and what person of phase lag signal PD2 produces effective pulse signal, whether in advance the phase place that just can learn power supply signal ACP the phase place of vertical synchronizing signal VSYNC.Wherein, phase lead signal PD1 and phase lag signal PD2 form the phase difference state PD shown in Fig. 1,2.
Below more with reference to Fig. 4, a waft embodiment of removing method of the look that Fig. 4 illustrates the monitoring arrangement of the embodiment of the invention.Its step comprises: at first, receive the power supply signal and the vertical synchronizing signal that exchange, wherein vertical synchronizing signal is to produce (S410) according to the picture element scan clock pulse.Then, relatively power supply signal also obtains phase difference state (S420) with the phase place of vertical synchronizing signal, and the phase place that phase difference state wherein comprises power supply signal in advance or lag behind the phase place of vertical synchronizing signal.Then, the phase difference state that is obtained according to step S420 in scan line selected many adjusted scan line (S430), and, when scan line is adjusted in scanning, adjust the pulse bandwidth (S440) of picture element scan clock pulse.That is to say that when the phase place at power supply signal is ahead of the phase place of vertical synchronizing signal, the pulse bandwidth of adjusting and reducing the picture element scan clock pulse is to transfer the phase place of fast vertical synchronizing signal.And when, transferring to increase the pulse bandwidth of picture element scan clock pulse to transfer the phase place of slow vertical synchronizing signal during in the phase place of vertical synchronizing signal in the phase lag of power supply signal.
In sum, the present invention is according to the phase difference state of power supply signal and vertical synchronizing signal, come when being adjusted scan line and scan, dynamically adjust the pulse bandwidth of picture element scan clock pulse, adjusting the frequency of vertical synchronizing signal, so reach the field rate and the power supply signal that make monitoring arrangement can be synchronous.Thus, the picture element scan clock pulse can be adjusted dynamically according to the phase difference state, can effectively solve the phenomenon because the asynchronous look that produces with power supply signal of field rate of monitoring arrangement wafts.
Though the present invention discloses as above with embodiment; yet it is not in order to limit the present invention; those of ordinary skill in the technical field under any; without departing from the spirit and scope of the present invention; when doing a little change and retouching, so protection scope of the present invention is as the criterion when looking appended the scope that claim defined.
Claims (13)
1. a monitoring arrangement provides a picture element scan clock pulse with scanning multi-strip scanning line, comprising:
One phase comparator, the power supply signal and the vertical synchronizing signal that receive to exchange, the relatively phase place of this power supply signal and this vertical synchronizing signal and obtain a phase difference state;
One clock pulse manager couples this phase comparator, according to this phase difference state in described multi-strip scanning line selected many adjusted scan line, and described many when being adjusted scan line, adjust the pulse bandwidth of this picture element scan clock pulse in scanning; And
One sequential generator couples this phase comparator and this clock pulse manager, receives this picture element scan clock pulse and produces this vertical synchronizing signal.
2. monitoring arrangement as claimed in claim 1, wherein when the phase place of leading this vertical synchronizing signal of the phase place of this power supply signal, described many when being adjusted scan line in scanning of this clock pulse managers lower the pulse bandwidth of this picture element scan clock pulse.
3. monitoring arrangement as claimed in claim 1, wherein when the phase place of this vertical synchronizing signal of phase lag of this power supply signal, described many when being adjusted scan line in scanning of this clock pulse managers increase the pulse bandwidth of this picture element scan clock pulse.
4. monitoring arrangement as claimed in claim 1 is adjusted scan line and is evenly distributed between described multi-strip scanning line according to scanning sequency for wherein said many.
5. monitoring arrangement as claimed in claim 1, adjusted scan line and be distinguished into a plurality of scanline groups of being adjusted for wherein said many, described a plurality of scanline groups of being adjusted is evenly distributed between described multi-strip scanning line according to scanning sequency, and each described number of scanning lines amount of being adjusted in the scanline groups of being adjusted equates.
6. monitoring arrangement as claimed in claim 1, wherein this clock pulse manager also receives a main clock pulse, and the pulse bandwidth of this picture element scan clock pulse decides for the pulse wave number according to this main clock pulse.
7. monitoring arrangement as claimed in claim 1, wherein this phase comparator comprises:
One first trigger has clock pulse terminal, data terminal, reset terminal and output, and its data terminal couples a reference voltage, and its clock pulse termination is received this power supply signal, and its reset terminal receives a reset signal, and its output produces a phase lead signal;
One second trigger has clock pulse terminal, data terminal, reset terminal and output, and its data terminal couples this reference voltage, and its clock pulse termination is received this vertical synchronizing signal, and its reset terminal receives this reset signal, and its output produces a phase lag signal; And
One arithmetic logic unit couples this first and second trigger to receive this phase lead signal and this phase lag signal, and this arithmetic logic unit produces this reset signal according to this phase lead signal and this phase lag signal at its output.
8. the look of the monitoring arrangement removing method that wafts, this monitoring arrangement provides a picture element scan clock pulse with scanning multi-strip scanning line, comprising:
Receive the power supply signal and the vertical synchronizing signal that exchange, wherein this vertical synchronizing signal is to produce according to this picture element scan clock pulse;
The phase place of this power supply signal and this vertical synchronizing signal and obtain a phase difference state relatively;
In described multi-strip scanning line, select many according to this phase difference state and adjusted scan line; And
In scanning described many when being adjusted scan line, adjust the pulse bandwidth of this picture element scan clock pulse.
9. the look as claimed in claim 8 removing method that wafts wherein when the phase place of leading this vertical synchronizing signal of this power supply signal, described many when being adjusted scan line in scanning, lowers the pulse bandwidth of this picture element scan clock pulse.
10. the look as claimed in claim 8 removing method that wafts wherein when this power supply signal falls behind the phase place of this vertical synchronizing signal, described many when being adjusted scan line in scanning, increases the pulse bandwidth of this picture element scan clock pulse.
The removing method 11. look as claimed in claim 8 wafts is adjusted scan line and is evenly distributed between described multi-strip scanning line according to scanning sequency for wherein said many.
The removing method 12. look as claimed in claim 8 wafts, adjusted scan line and divided a plurality of scanline groups of being adjusted for wherein said many, described a plurality of scanline groups of being adjusted is evenly distributed between described multi-strip scanning line according to scanning sequency, and each described number of scanning lines amount of being adjusted in the scanline groups of being adjusted equates.
The removing method 13. look as claimed in claim 8 wafts wherein also accept a main clock pulse described many of scanning when being adjusted scan line, and the pulse wave number of this main clock pulse of foundation is adjusted the pulse bandwidth of this picture element scan clock pulse.
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| CN2010101639781A CN102223466A (en) | 2010-04-16 | 2010-04-16 | Monitoring device and floating color eliminating method thereof |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN112752129A (en) * | 2019-10-31 | 2021-05-04 | 西安诺瓦星云科技股份有限公司 | Video source synchronous output method, device, system and computer readable storage medium |
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| US20050200704A1 (en) * | 2002-03-05 | 2005-09-15 | Toshiaki Kodake | Imager and stripe noise removing method |
| US20050253941A1 (en) * | 2002-06-06 | 2005-11-17 | Sony Corporation | Image processing circuit, image processing method, and camera device |
| CN101325721A (en) * | 2007-06-15 | 2008-12-17 | 盛群半导体股份有限公司 | Circuit and method for adjusting image frequency |
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| US20050200704A1 (en) * | 2002-03-05 | 2005-09-15 | Toshiaki Kodake | Imager and stripe noise removing method |
| US20050253941A1 (en) * | 2002-06-06 | 2005-11-17 | Sony Corporation | Image processing circuit, image processing method, and camera device |
| CN101325721A (en) * | 2007-06-15 | 2008-12-17 | 盛群半导体股份有限公司 | Circuit and method for adjusting image frequency |
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| CN112752129A (en) * | 2019-10-31 | 2021-05-04 | 西安诺瓦星云科技股份有限公司 | Video source synchronous output method, device, system and computer readable storage medium |
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Application publication date: 20111019 |