CN102194827A - High-dielectric-constant material-based irradiation-resistance SOI (Silicon on Insulator) device and manufacturing method thereof - Google Patents
High-dielectric-constant material-based irradiation-resistance SOI (Silicon on Insulator) device and manufacturing method thereof Download PDFInfo
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- CN102194827A CN102194827A CN 201010128019 CN201010128019A CN102194827A CN 102194827 A CN102194827 A CN 102194827A CN 201010128019 CN201010128019 CN 201010128019 CN 201010128019 A CN201010128019 A CN 201010128019A CN 102194827 A CN102194827 A CN 102194827A
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Abstract
The invention discloses a high-dielectric-constant-material-based irradiation-resistance SOI (Silicon on Insulator) device which comprises a substrate silicon layer, a buried oxide layer, an active region silicon layer, a gate oxide layer and an isolation oxide layer, wherein a source region, a drain region and a channel region are formed on the active region silicon layer. The high-dielectric-constant-material-based irradiation-resistance SOI device is characterized in that: an isolation layer is formed between the buried oxide layer and the active region silicon layer and is made of a high-dielectric-constant material. The SOI device with the novel structure is based on a mainstream SOI manufacturing technology and is completely compatible to the traditional technology; the irradiation-resistance capability of the SOI device is improved while the excellent property of the original SOI device is kept; and the high-dielectric-constant-material-based irradiation-resistance SOI device with the structure has remarkable advantages in the aspects of reducing the increased power consumption of an SOI integrated circuit due to total dose irradiation and enhancing the reliability of a chip and has wide application prospects.
Description
Technical field
The invention belongs to integrated circuit and space technology application.The present invention relates to a kind of based on main flow integrated circuit technology preventing total dose radiation performance SOI device preparation, that can significantly improve device, especially a kind of New type of S OI device architecture of realizing with High-K (high-k) material.
Background technology
Advantages such as integrated circuit technique is low, powerful owing to cost, volume is little have become the important motivity that promotes electronics and information industry and social development.Integrated circuit (IC) chip is widely used in fields such as computer, communication, automobile, Industry Control and consumer electronics.Integrated circuit (IC) chip is widely used in the space technology equally, uses integrated circuit (IC) chip to make the with better function of satellite in a large number, and volume and weight is littler, and the development of integrated circuit (IC) chip is significant for the development of space technology.
For the body silicon device, the SOI device has higher integrated level, lower power consumption and better short-channel properties, thereby and because latch-up has fundamentally been eliminated in the existence of oxygen buried layer the reliability of device is significantly improved.The SOI technology is widely used in its good device property that the SOI device is the basic comprising unit of integrated circuit in the Deep Sub-Micron VLSI chip, along with the SOI technology more and more is widely used in the integrated circuit manufacturing, it is significant for improving chip reliability and useful life to study the SOI device with good resistance total dose irradiation ability.
Be illustrated in figure 1 as the SOI device architecture profile of conventional isolation structure, described SOI device architecture comprises layer-of-substrate silicon 1, buries oxide layer 2, source region 4, drain region 5, polysilicon gate 6, isolating oxide layer 7, gate oxide 8 and channel region 9; In space environment is used, the SOI device integrated circuit is subjected to the influence of space radiation, irradiation mainly is to have introduced the oxide trap electric charge for the influence of SOI device integrated circuit in oxygen buried layer 2, as shown in Figure 3, these trapped charges attract the electronics in the silicon layer to form spurious leakage raceway groove 12 on the one hand, the leakage current of device is increased, this part charge effect will be coupled in the gate oxide on the other hand, thereby causing the grid-control ability drop of device to make device performance degeneration, is the reinforcing emphasis of SOI device at the reinforcement measure of oxygen buried layer.
Because the extensive use of SOI technology in integrated circuit (IC) chip, the new device structure that proposes anti-irradiation under the prerequisite that does not change the main flow semiconductor fabrication process is significant for the reliability that improves the SOI integrated circuit.
Summary of the invention
One of purpose of the present invention is to provide a kind of New type of S OI device architecture that can improve device preventing total dose radiation effect (reducing the device performance degeneration that the total dose irradiation effect causes); Another object of the present invention is to provide this novel anti irradiation SOI preparation of devices method.
In order to realize above-mentioned goal of the invention one, technical scheme of the present invention is:
A kind of anti-irradiation SOI device based on high dielectric constant material, comprise substrate silicon layer, bury oxide layer, active area silicon layer, gate oxide and isolating oxide layer, form source region, drain region and channel region on the described active area silicon layer, it is characterized in that described burying between oxide layer and the active area silicon layer has separator.
Described separator adopts high dielectric constant material.
Described high dielectric constant material is H
fO
2
Described high dielectric constant material is Al
2O
3
Described high dielectric constant material thickness is the 10-20 nanometer.
Described separator is grown or is deposited on and buries on the oxide layer.
Described separator is fabricated under the described active area silicon layer by the method by wafer bonding.
In order to realize another above-mentioned goal of the invention, technical scheme of the present invention is:
A kind of anti-irradiation SOI device preparation method based on high dielectric constant material, its step comprises:
1) prepare two monocrystalline silicon, a slice is as the active area silicon layer, and a slice is used thermal oxidation technology to generate and buried oxide layer as silicon substrate on the described silicon substrate;
2) use depositing technics, at the separator that buries deposit one deck high dielectric constant material on the oxide layer;
3) adopt wafer bonding technology that the separator of high dielectric constant material is fabricated into the active area silicon layer;
4) mask is leaked in the use source, stops active area silicon layer channel part, and being mixed in the channel part two ends forms source region and drain region;
5) carry out channel part and mix, the length of mask definition gate oxide, manufacturing gate oxide layers on channel part are leaked in the use source;
6) deposit polysilicon gate on gate oxide generates the isolation between isolating oxide layer realization polysilicon gate and source region, the drain region afterwards;
7) the follow-up conventional procedure of SOI device that carries out, making finishes.
Compared with prior art, the invention has the beneficial effects as follows:
1, based on the SOI manufacturing technology of main flow, compatible fully with traditional handicraft.
2, the SOI device with novel isolation structure has improved its anti-irradiation ability when keeping original SOI device good characteristic.
3, new construction increases and strengthens the chip reliability aspect remarkable advantages and wide application prospect are arranged for reducing SOI integrated circuit (IC) power consumption that total dose irradiation causes.
Description of drawings
Fig. 1 is conventional SOI device architecture profile;
Fig. 2 is a New type of S OI device architecture profile of the present invention;
The spurious leakage raceway groove of Fig. 3 for causing behind the conventional device structure irradiation;
The spurious leakage raceway groove of Fig. 4 for causing behind the new device structure irradiation of the present invention;
Fig. 5 is for the silicon chip preparation and bury oxide layer growth step schematic diagram;
Fig. 6 is a high dielectric constant material separator growth step schematic diagram
Fig. 7 is wafer bonding and silicon layer attenuate step schematic diagram;
Fig. 8 leaks the implantation step schematic diagram for the source;
Fig. 9 is a gate oxide making step schematic diagram;
Figure 10 is polysilicon gate deposit and subsequent step schematic diagram
Wherein:
The 1-silicon substrate; 2-buries oxide layer; The 3-separator; The 4-source region; The 5-drain region; The 6-polysilicon gate; 7-oxidation separator; The 8-gate oxide; The 9-channel region; 10-photoresist mask; 11-active area silicon layer; The spurious leakage raceway groove that the 12-total dose irradiation causes;
Embodiment
Below in conjunction with the drawings and specific embodiments the present invention is described in further detail:
Fig. 2 has represented that the SOI device of new structure of the present invention and the SOI device of the conventional structure shown in Fig. 1 compare, and New type of S OI device architecture shown in Figure 2 mainly is to have increased one deck separator 3 on the oxide layer 2 in traditional burying.This layer separator 3 is by after being grown on the oxygen buried layer 2, is fabricated into below the silicon layer by wafer bonding technology.The oxide trapped charge that total dose irradiation is introduced causes the degeneration of device property relevant with the trap quantity and the dielectric constant of oxygen buried layer, under the oxide trap amount of charge situation of same quantity, improve the dielectric constant of dielectric layer, will reduce the device OFF state Leakage Current that oxide charge causes.
Fig. 3 has represented that conventional device is subjected to occurring behind the total dose irradiation situation of spurious leakage raceway groove, it is a large amount of trapped charge of generation in the oxide layer that buries that total dose irradiation makes device, these trapped charges will attract to form spurious leakage raceway groove 12 near charge carrier partly with it in the silicon layer, leak source region 4 and drain region 5 connections of raceway groove with device, thereby parasitic leakage current occurs, the size of parasitic leakage current depends on the power of leaking raceway groove.Fig. 4 has shown that the situation of spurious leakage raceway groove appears in soi structure device of the present invention after being subjected to same irradiation, because the separator 3 of one deck high dielectric constant material is arranged on the oxygen buried layer 2 of soi structure device of the present invention, the high-k of insolated layer materials weakens the influence of the trapped charge of same quantity, thereby make spurious leakage raceway groove 12 attenuates, as shown in Figure 4, the parasitic leakage current that irradiation is caused reduces, and reaches the purpose that improves the anti-irradiation ability of device.
The High-K separator that soi structure device of the present invention uses mainly is to have played the effect that utilizes its high dielectric constant to weaken oxide trap electric charge in the oxygen buried layer, material therefor be have high-k and can with the dielectric material of semi-conducting material compatibility, as H
fO
2, Al
2O
3Deng.
Soi structure device architecture of the present invention is because the generating mode of its High-K separator that adopts and main flow SOI substrate manufacture craft are compatible fully, only need on silicon dioxide layer, grow or the High-K material of deposit one deck and traditional cmos process compatibility, do not need to increase other mask, reduced cost of manufacture, the technology simple possible.
Be example with NMOS below, introduce soi structure preparation of devices method of the present invention in detail:
1) silicon chip preparation and oxygen buried layer growth step: as shown in Figure 5, prepare two monocrystalline silicon pieces, wherein a slice is as active area silicon layer 11, and another sheet is as silicon substrate 1, and using thermal oxidation technology (wet-oxygen oxidation) to generate thickness on silicon substrate 1 is the silicon dioxide oxygen buried layer 2 of 50～500 nanometers;
2) high-k separator growth step: as shown in Figure 6, use depositing technics, deposit one layer thickness is the high dielectric constant material separator 3 of 10～20 nano thickness on the silicon substrate that has oxide layer of burying 21 that step 1) is prepared, and described high dielectric constant material is H
fO
2Perhaps Al
2O
3
3) wafer bonding and silicon layer attenuate step: as shown in Figure 7, adopting active area silicon layer 11 that wafer bonding technology makes the first step and the silicon substrate 1 with silicon dioxide oxygen buried layer 2 to make becomes a silicon chip with high dielectric constant material separator 3 structures, uses plasma-assisted chemical caustic solutions etc. to carry out attenuate for the silicon fiml 11 of top layer afterwards; Obtaining thickness is the active area silicon layer 11 (device region forms source region, drain region, channel region on it) of 50～200 nanometers;
4) the SOI device source is leaked the mask implantation step: as shown in Figure 8, make mask 10 blocking device channel regions 9 parts with photoresist, use ion implantation technology, inject arsenic As at the two ends of channel region 9, adopting rta technique to make the two ends of channel region 9 form doping content afterwards is 10
20Cm
-3About N type doping source region 4 and N type doped drain 5;
5) growth of gate oxide layer step: as shown in Figure 9, after source-drain area is made, P type silicon layer channel region 9 is injected Ga mix, doping content is 1 * 10
17Cm
-3About, define the length (about 50～100 nanometers) of gate oxide 8 with photoresist, use dry-oxygen oxidation technology, making thickness is the silicon dioxide gate oxide 8 of 3～5 nanometers, and anneals in blanket of nitrogen to reduce interfacial state;
6) polysilicon gate depositing step and subsequent preparation technology: as shown in figure 10; deposition thickness is the N type heavily doped polysilicon grid 6 of 20～100 nano thickness on the above-mentioned oxide layer that completes, afterwards wet-oxygen oxidation generate isolating oxide layer 7 with protection device and realize polysilicon gate 6 and source region 4, drain region 5 between isolation.
7) element manufacturing finishes, and subsequent technique such as punching, line, area of isolation etc. repeat no more.
More than by specific embodiment anti-irradiation SOI device based on high dielectric constant material provided by the present invention and preparation method thereof has been described, those skilled in the art is to be understood that, in the scope that does not break away from essence of the present invention, can make certain deformation or modification to the present invention; Its concrete true mode also is not limited to disclosed content among the embodiment.
Claims (8)
1. anti-irradiation SOI device based on high dielectric constant material, comprise substrate silicon layer, bury oxide layer, active area silicon layer, gate oxide and isolating oxide layer, form source region, drain region and channel region on the described active area silicon layer, it is characterized in that described burying between oxide layer and the active area silicon layer has separator.
2. SOI device as claimed in claim 1 is characterized in that, described separator adopts high dielectric constant material.
3. SOI device as claimed in claim 2 is characterized in that, described high dielectric constant material is H
fO
2
4. SOI device as claimed in claim 2 is characterized in that, described high dielectric constant material is Al
2O
3
5. SOI device as claimed in claim 2 is characterized in that, described high dielectric constant material thickness is the 10-20 nanometer.
6. SOI device as claimed in claim 1 is characterized in that, described separator is grown or is deposited on and buries on the oxide layer.
7. SOI device as claimed in claim 1 is characterized in that, described separator is fabricated under the described active area silicon layer by the method for wafer bonding.
8. anti-irradiation SOI device preparation method based on high dielectric constant material, its step comprises:
1) prepare two monocrystalline silicon, a slice is as the active area silicon layer, and a slice is used thermal oxidation technology to generate and buried oxide layer as silicon substrate on the described silicon substrate;
2) use depositing technics, at the separator that buries deposit one deck high dielectric constant material on the oxide layer;
3) adopt wafer bonding technology that the separator of high dielectric constant material is fabricated into the active area silicon layer;
4) mask is leaked in the use source, stops active area silicon layer channel part, and being mixed in the channel part two ends forms source region and drain region;
5) carry out channel part and mix, the length of mask definition gate oxide, manufacturing gate oxide layers on channel part are leaked in the use source;
6) deposit polysilicon gate on gate oxide generates the isolation between isolating oxide layer realization polysilicon gate and source region, the drain region afterwards;
7) the follow-up conventional procedure of SOI device that carries out, making finishes.
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Cited By (9)
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| CN102610644A (en) * | 2011-12-22 | 2012-07-25 | 北京大学 | SOI (silicon on insulator) device for restraining current leakage of back gate arising from radiation and preparation method thereof |
| CN103022139A (en) * | 2012-12-28 | 2013-04-03 | 上海集成电路研发中心有限公司 | Semiconductor structure with insulating buried layer and manufacturing method thereof |
| CN108269739A (en) * | 2016-12-30 | 2018-07-10 | 无锡华润上华科技有限公司 | The forming method of polysilicon gate |
| CN109860097A (en) * | 2018-12-28 | 2019-06-07 | 中国科学院微电子研究所 | A kind of reinforcement means of silicon-on-insulator material and its anti-integral dose radiation |
| CN110098112A (en) * | 2019-05-17 | 2019-08-06 | 电子科技大学 | A kind of implementation method of resistant to total dose SOI integrated circuit device structure |
| CN112379240A (en) * | 2020-11-13 | 2021-02-19 | 中国科学院新疆理化技术研究所 | Method for evaluating total dose radiation performance of radiation-resistant reinforced SOI material |
| CN113990846A (en) * | 2021-09-28 | 2022-01-28 | 哈尔滨工业大学 | SOI device capable of resisting total dose irradiation and preparation method thereof |
| WO2022195226A1 (en) * | 2021-03-18 | 2022-09-22 | Soitec | Ncfet transistor comprising a semiconductor-on-insulator substrate |
| WO2024087189A1 (en) * | 2022-10-28 | 2024-05-02 | 苏州大学 | Anti-radiation field effect transistor device and application thereof in anti-radiation environment |
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Cited By (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102610644A (en) * | 2011-12-22 | 2012-07-25 | 北京大学 | SOI (silicon on insulator) device for restraining current leakage of back gate arising from radiation and preparation method thereof |
| CN102610644B (en) * | 2011-12-22 | 2014-08-13 | 北京大学 | SOI (silicon on insulator) device for restraining current leakage of back gate arising from radiation and preparation method thereof |
| CN103022139A (en) * | 2012-12-28 | 2013-04-03 | 上海集成电路研发中心有限公司 | Semiconductor structure with insulating buried layer and manufacturing method thereof |
| CN108269739A (en) * | 2016-12-30 | 2018-07-10 | 无锡华润上华科技有限公司 | The forming method of polysilicon gate |
| CN109860097A (en) * | 2018-12-28 | 2019-06-07 | 中国科学院微电子研究所 | A kind of reinforcement means of silicon-on-insulator material and its anti-integral dose radiation |
| CN110098112A (en) * | 2019-05-17 | 2019-08-06 | 电子科技大学 | A kind of implementation method of resistant to total dose SOI integrated circuit device structure |
| CN112379240A (en) * | 2020-11-13 | 2021-02-19 | 中国科学院新疆理化技术研究所 | Method for evaluating total dose radiation performance of radiation-resistant reinforced SOI material |
| CN112379240B (en) * | 2020-11-13 | 2024-04-05 | 中国科学院新疆理化技术研究所 | Method for evaluating total dose radiation performance of radiation-resistant reinforced SOI material |
| WO2022195226A1 (en) * | 2021-03-18 | 2022-09-22 | Soitec | Ncfet transistor comprising a semiconductor-on-insulator substrate |
| CN113990846A (en) * | 2021-09-28 | 2022-01-28 | 哈尔滨工业大学 | SOI device capable of resisting total dose irradiation and preparation method thereof |
| WO2024087189A1 (en) * | 2022-10-28 | 2024-05-02 | 苏州大学 | Anti-radiation field effect transistor device and application thereof in anti-radiation environment |
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Application publication date: 20110921 |