CN102193888B - Data transmission system and programmable serial peripheral interface controller - Google Patents
Data transmission system and programmable serial peripheral interface controller Download PDFInfo
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- CN102193888B CN102193888B CN 201010132312 CN201010132312A CN102193888B CN 102193888 B CN102193888 B CN 102193888B CN 201010132312 CN201010132312 CN 201010132312 CN 201010132312 A CN201010132312 A CN 201010132312A CN 102193888 B CN102193888 B CN 102193888B
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Abstract
The embodiment of the invention provides a data transmission system and a programmable serial peripheral interface controller. The data transmission system comprises a serial peripheral interface and a programmable controller. The serial peripheral interface is coupled between a first device and at least one second device. The programmable controller is used for controlling the serial peripheral interface to be switched between a single-port data transmission mode and a multi-port data transmission mode, wherein when more than one second device is coupled to the serial peripheral interface, the serial peripheral interface is switched to the multi-port data transmission mode and used for controlling multi-port data transmission between the first device and the second device, the first device simultaneously transmits data to each second device through a first transmission bus end of the serial peripheral interface, and the first device simultaneously receives data from each second device through a second transmission bus end of the serial peripheral interface.
Description
Technical field
The present invention is about a kind of data transmission system, especially in regard to a kind of data transmission system that programmable Multi-ported Data transmission is provided by Serial Peripheral Interface (Serial Peripheral Interface is called for short SPI).
Background technology
Serial Peripheral Interface (Serial Peripheral Interface, be called for short SPI) is a kind of 4 line locking sequence data transportation protocols, and its framework be from/main structure, is present a kind of element and interelement connecting interface of being widely used in.
Yet, restriction due to framework, make present Serial Peripheral Interface be limited to single main device and application from device data transmission (single port data transmission), namely single master goes out from entering (MOSI), main entering from going out (MISO) data transmission.For day by day novel system applies, especially calculate simultaneously and the system of immediate reaction data content at needs, only provide the element of the Serial Peripheral Interface of single port data transmission all can't satisfy the system requirements of this respect at present.
Therefore, the Serial Peripheral Interface that needs a kind of improvement, it can utilize existing hardware structure that the data transmission of multiport (multi port) is provided, and can have more programmable characteristic, in order to flexibly to switch on the data transmission of single port and multiport, make under fixing hardware structure, can satisfy different system requirements.
Summary of the invention
The Serial Peripheral Interface that the present invention provides in a plurality of embodiment utilize existing hardware structure that the Multi-ported Data transmission is provided, and the Serial Peripheral Interface of Improvement type can further switch on the data-transmission mode of single port and multiport.
According to one embodiment of the invention, a kind of data transmission system comprises Serial Peripheral Interface and Programmable Logic Controller.Serial Peripheral Interface is coupled between first device and at least one the second device, comprise transmitting clock signal in first device therewith the sequence clock pulse end between at least one the second device, in order to transmit chip select signal in first device therewith between at least one the second device, by this chip selection end of the transmission of log-on data, in order to the transmission of data from first device so far at least one the second device one first transfer bus end and at least one second install so far one second transfer bus end of first device since then in order to the transmission of data.Programmable Logic Controller switches on single port data transmission mode and Multi-ported Data transmission mode in order to control Serial Peripheral Interface, wherein when being coupled to Serial Peripheral Interface more than second device, Serial Peripheral Interface switches to the Multi-ported Data transmission mode, carry out the Multi-ported Data transmission in order to control between first device and these the second devices, this moment, first device transferred data to each second device simultaneously by the first transfer bus end, and first device passes through the second transfer bus end simultaneously from each the second device receive data.
According to another embodiment of the present invention, a kind of data transmission system comprises a serial peripheral interface and a Programmable Logic Controller.Serial Peripheral Interface is coupled to a first device, comprise transmitting a clock pulse signal to a sequence clock pulse end of at least one the second device, in order to transmit a chip select signal, by this chip selection end of the transmission of log-on data, in order to transmit data to the first transfer bus end of at least one the second device and in order to receive the second transfer bus end of the data that this at least one second device transmits.Programmable Logic Controller switches on single port data transmission mode and Multi-ported Data transmission mode in order to control this Serial Peripheral Interface, wherein when being coupled to Serial Peripheral Interface more than second device, Serial Peripheral Interface switches to the Multi-ported Data transmission mode, carry out the Multi-ported Data transmission in order to control between first device and described these second devices, this moment, first device transferred data to each second device simultaneously by the first transfer bus end, and first device passes through the second transfer bus end simultaneously from each the second device receive data.
According to another embodiment of the present invention, propose a kind of programmable serial peripheral interface controller, in order to control the data-transmission mode of a serial peripheral interface, comprise a data transmission selector switch, carry out data allocations in order to control parameter according to port number.wherein port number is controlled parameter and is represented the number that carries out simultaneously at least one second device of data transmission with a first device, this data-transmission mode is changeable in a single port data transmission mode and a Multi-ported Data transmission mode, this first device and at least one the second device transmit data bit by this Serial Peripheral Interface, when being coupled to Serial Peripheral Interface more than second device, Serial Peripheral Interface is switched to this Multi-ported Data transmission mode, carry out the Multi-ported Data transmission in order to control between first device and these the second devices, this moment, first device transferred data to each second device simultaneously by the first transfer bus end, and first device passes through the second transfer bus end simultaneously from each the second device receive data.
The Serial Peripheral Interface that the embodiment of the present invention provides, it can utilize existing hardware structure that the data transmission of multiport (multi port) is provided, and can have more programmable characteristic, in order to flexibly to switch on the data transmission of single port and multiport, make under fixing hardware structure, can satisfy different system requirements.In addition, the data transmission system framework that the embodiment of the present invention proposes, can reach and utilize Serial Peripheral Interface (SPI) to carry out simultaneously the purpose that reads or write of long numeric data, improve by this using value of Serial Peripheral Interface (SPI).
Description of drawings
Fig. 1 shows a data transmission system described according to one embodiment of the invention;
Fig. 2 shows Programmable Logic Controller calcspar described according to one embodiment of the invention;
Fig. 3 shows data transmission flow process figure in data transmission system in described according to one embodiment of the invention;
Fig. 4 A and Fig. 4 B show the signal waveforms in data transmission system described according to one embodiment of the invention;
Fig. 5 shows a described according to another embodiment of the present invention data transmission system.
Drawing reference numeral
100,500～data transmission system;
101,102-0,102-n, 501-0,501-1,502-0,502-1,502-2,502-3,502-4,502-5,502-6,502-7～data transmission device;
103,503-0,503-1～Serial Peripheral Interface;
104,200～Programmable Logic Controller;
105,105-0,105-1,105-2,105-3,106,106-0,106-1,106-2,106-3～shift register;
201～data transmission selector switch;
202～transmission digit counter;
203～logic comparator;
204～package comparer;
205～port number is controlled parameter;
206～transmission position parameter;
207～transmission package parameter;
DI[0], DI[1], DI[2], DI[3], DI[n], DO[0], DO[1], DO[2], DO[3], DO[n], SPI_DI[n:0], SPI_DI1[3:0], SPI_DI2[3:0], SPI_DO[n:0], SPI_DO1[3:0], SPI_DO2[3:0]～data bit;
MOSI, MISO～transfer bus end;
MOSI[n:0], MISO[n:0]～transfer bus;
SCLK～sequence clock pulse end;
SS～chip selection end;
SPI_SCLK～clock signal;
SPI_SS, SPI_SS1, SPI_SS2～chip select signal.
Embodiment
For above and other purpose of the present invention, feature and advantage can be become apparent, a plurality of embodiment cited below particularly, and coordinate appended accompanying drawing, be described in detail below.
Fig. 1 shows a data transmission system 100 described according to one embodiment of the invention, comprises a plurality of data transmission devices 101 and 102-0～102-n and is coupled to a serial peripheral interface 103 between data transmission device.Wherein data transmission device can comprise a main device (for example, 101) and at least one from device (for example, 102-0～102-n, n are positive integer).Serial Peripheral Interface 103 comprises sequence clock pulse end SCLK, chip selection end SS and the transfer bus end MOSI (master goes out from entering) and MISO (master enters from going out) that is coupled between data transmission device.Main device 101 transmits a clock pulse signal SPI_SCLK extremely from device 102-0～102-n by sequence clock pulse end SCLK, in order to provide clock signal extremely from device, and to from device 102-0～102-n, carry out data transmission in order to start from device by chip select signal by chip selection end SS transmission one chip select signal SPI_SS.
According to one embodiment of the invention, transfer bus MOSI[n:0] in order to provide autonomous device to the one or more data transmission of list from device, data bit SPI_DO[n:0 as shown in the figure], and transfer bus MISO[n:0] in order to provide since installing the extremely one or more data transmission of list of main device, data bit SPI_DI[n:0 as shown in the figure].In embodiments of the invention, clock signal SPI_SCLK and chip select signal SPI_SS are common to a plurality of between device, so when a plurality of when being selected from device, respectively can carry out two-way data transmission with main device simultaneously from device, that is, a plurality of data bit can be transmitted in parallel and two-wayly main device and from the device between.
according to one embodiment of the invention, data transmission system 100 can also comprise a Programmable Logic Controller (programmable serial peripheral interface controller), a data-transmission mode in order to control data transmission system 100 interior Serial Peripheral Interface 103, wherein Programmable Logic Controller can be disposed at separately in data transmission system, perhaps flexibly be integrated in main device 101 (Programmable Logic Controller 104 as shown in Figure 1), at least one in device or Serial Peripheral Interface 103, therefore hardware configuration of the present invention is not limited to the category as shown in the first figure.according to one embodiment of the invention, Programmable Logic Controller can switch on a single port (single port) transmission mode and a multiport (multi port) data-transmission mode according to system requirements, wherein when being coupled to Serial Peripheral Interface 103 more than one from device, Programmable Logic Controller can switch to the Multi-ported Data transmission mode in response to system requirements, in order to control main device and to transmit from carrying out Multi-ported Data between device, as above-mentioned, this moment data bit can be transmitted in parallel and two-wayly main device with from (following will do more detailed introduction for single port data transmission mode and Multi-ported Data transmission mode) between installing.
Fig. 2 shows Programmable Logic Controller calcspar described according to one embodiment of the invention.As above-mentioned, Programmable Logic Controller can be disposed at separately data transmission system, perhaps flexibly is integrated in main device, at least one in device or Serial Peripheral Interface, and therefore enforcement of the present invention is not limited to any hardware configuration.As shown in Figure 2, Programmable Logic Controller 200 can comprise data transmission selector switch 201, transmission digit counter 202, logic comparator 203 and package comparer 204.Data transmission selector switch 201 carries out data allocations in order to control parameter 205 according to a port number.Port number is controlled parameter 205 can in order in the setting data transmission system, carry out the number from device of data transmission simultaneously with main device.for example, when data transmission system can provide at most 4 to carry out data transmission with main device simultaneously from device, port number is controlled parameter 205 can be set as 1～4, wherein when port number control parameter 205 is set as 1, the representative data transmission system is single port data transmission mode at present, therefore the same time only one carry out data transmission from device and main device, on the other hand, when port number control parameter 205 is set as 4, the representative data transmission system is the Multi-ported Data transmission mode at present, therefore the same time can have 4 to carry out data transmission with main device simultaneously from device.
Fig. 2 demonstrates one 4 port data transmission mode examples, under this pattern, port number is controlled parameter 205 and is set to 4, therefore can support at most 4 and carry out simultaneously data transmission from device and 1 main device, transfer bus MOSI[3:0 wherein], MISO[3:0] each transmission line be respectively coupled to as shown in Figure 1 main device and respectively between device, in order to transmit everybody (DO[0 as shown in Figure 1]～DO[n] and DI[0]～DI[n]) self-corresponding from device to each.According to one embodiment of the invention, main device can comprise multi-level input shift register 105 and multi-level Output Shift Register 106 (as shown in Figure 1), be received from the respectively data bit from installing in order to deposit respectively, and the respectively data bit from installing is delivered in tendency to develop.More particularly, 4 port data transmission mode examples as shown in Figure 2, main device can comprise a plurality of input shift register 105-0～105-3 and Output Shift Register 106-0～106-3, each input shift register is self-corresponding from installing (from the one of device 102-0～102-n in order to store respectively, n=3 in this example wherein) data bit that receives, and each Output Shift Register is delivered to the corresponding data bit from device in order to store tendency to develop respectively.
In the process of the data transmission of Multi-ported Data transmission mode, but 201 parallel processing of data transmission selector switch from respectively from the device data bit, in order to being distributed, described these data bit are stored in corresponding input shift register 105-0～105-3, and parallel processing is from each Output Shift Register 106-0～106-3 position, and is corresponding to device in order to described these data bit are exported to.Therefore, input shift register 105-0～105-3 can be self-corresponding from installing parallel receive data (namely respectively, simultaneously from each correspondence from the device receive data), and Output Shift Register 106-0～106-3 can parallel output data to respectively from device (that is, export simultaneously data to each correspondence from device).Thus, main device can transfer data to each from device simultaneously by transfer bus end MOSI, and by transfer bus end MISO simultaneously from each from the device receive data.
The resulting bit comparison result of logic comparator 203 can further be sent to package comparer 204.Package comparer 204 to obtain a package comparative result, wherein transmits the package sum that package parameter 207 representatives are transmitted in a transmission cycle domestic demand in order to this comparative result and a transmission package parameter 207 are compared.For example, when transmission package parameter 207 was set as 1, representative was at package of a transmission cycle domestic demand transmission, and wherein according to one embodiment of the invention, this transmission cycle can be the cycle of chip select signal SPI SS.Therefore, transmit when completing when comparative result demonstrates an existing package, package comparer 204 compares this comparative result and transmission package parameter 207, can learn that the data transmission in present transmission cycle is completed.It should be noted that, port number is controlled the systematic parameters such as parameter 205, transmission position parameter 206 and transmission package parameter 207 and can be stored in the built-in storage of system, and can change according to the variation of different system requirements and transmission mode its setting value (following will further do more detailed introduction for the systematic parameter setting value).
Fig. 3 shows data transmission flow process figure in data transmission system in described according to one embodiment of the invention.When the transmission beginning (step S301), whether the needs Multi-ported Data is transmitted (step S302) to Programmable Logic Controller at present according to the system requirements judgement.If not, Programmable Logic Controller (is for example set corresponding systematic parameter, port number is controlled parameter 205, transmission position parameter 206 and transmission package parameter 207 etc.) (step S303), and then begin to carry out single port Data transmitting and receiving (step S304).On the other hand, if Programmable Logic Controller is set corresponding systematic parameter (step S305), and then begin to carry out the Multi-ported Data transmission and receive (step S306).Then, Programmable Logic Controller judges whether data transmission finishes (step S307), and as above-mentioned, Programmable Logic Controller judges whether also have package to need to transmit in this transmission, if need to be transmitted without package, to represent that this transmission finishes.If also have package to be transmitted, the representative transmission not yet finishes, and Programmable Logic Controller can further be set corresponding systematic parameter (step S305) according to system requirements, and continues the Multi-ported Data transmission and receive (step S306).
Fig. 4 A and Fig. 4 B show the signal waveforms in data transmission system described according to one embodiment of the invention, are a pair of port data transmission mode example at this.According to one embodiment of the invention, chip select signal SPI_SS can be designed to the control signal with low state action (active low), therefore when chip select signal SPI_SS transfers low level to by high levels, main device and from the device between data transmission start, and until chip select signal SPI_SS is pulled the cycle of high levels, may be defined as a transmission cycle.Therefore, Fig. 4 A and Fig. 4 B show the signal waveforms in a transmission cycle, and wherein the difference of Fig. 4 A and Fig. 4 B only is, Fig. 4 A can express the variation of data bit content, and Fig. 4 B can express the transmission sequence of data bit.
As shown in Fig. 4 A, transfer bus MISO[0] and MISO[1] and MOSI[0] and MOSI[1] can carry out simultaneously the transmission of bit data, therefore the same time for main device, can receive and the data that transmit 2 simultaneously.Fig. 4 B clearly shows the transmission sequence of data bit, wherein respectively input data bit DI and outputs data bits DO respectively with two numerical codings, DI nm as shown in the figure and DO nm (n=0～1, m=0～f), wherein the first yardage word n represents the bit data of n transfer bus, second code m represents that what transmit on this transfer bus is m position, so DI 0f represents the 16th position of transmitting on the 0th transfer bus.As shown in the figure, data bit sequentially is transmitted on transfer bus, and be stored to corresponding shift register (or sequentially being transferred into corresponding transfer bus from shift register), therefore in embodiments of the invention, processor (not shown) in data transmission system can directly be taken out data (or transmitting data to corresponding shift register) from shift register, and does not need to carry out extra bit data restructuring.
As above-mentioned, Programmable Logic Controller is in order to the data-transmission mode of control system, wherein according to one embodiment of the invention, under single port data transmission mode and Multi-ported Data transmission mode, systematic parameter all can flexibly be set, make data transmission system under fixing hardware structure, (for example also can reach the demand of different application, the many package transmission of multidigit or the many package transmission of unit etc.), below will set for the systematic parameter of single port data transmission mode and Multi-ported Data transmission mode and do more detailed description.
Suppose as shown in Figure 2, data transmission system can be supported at most 4 and be carried out simultaneously data transmission from device and 1 main device, therefore the same time can have at most the data of 4 to be transfused to simultaneously and output, so under the Multi-ported Data transmission mode, port number is controlled parameter 205 can be set to 2,3 or 4.When port number control parameter 205 was set to 4, main device can carry out two-way data transmission with 4 that are coupled to Serial Peripheral Interface from device simultaneously.When port number control parameter 205 was set to 2 or 3, main device can carry out two-way data transmission with 2 or 3 that are coupled to Serial Peripheral Interface from device simultaneously.According to one embodiment of the invention, not coupling this moment from the transfer bus end pin position MOSI of device and MISO can be universal input and output (General Purpose InputOutput by default, be called for short GPIO) pin position use, therefore would not cause the waste of pin position.
And under single port data transmission mode, port number is controlled parameter 205 and is set 1, and main device carries out two-way data transmission with 1 that is coupled to Serial Peripheral Interface from device.This moment is in order to increase the utilization rate of multi-level input and Output Shift Register, data transmission selector switch 201 can be orderly sent to each input shift register with the data bit from device input by correspondence, and the data bit that will be stored in each Output Shift Register is orderly sent to corresponding to device.In particular, with reference to figure 2, under single port data transmission mode, port number is controlled parameter 205 and is set 1, transmit package parameter 207 and can be set as 1～4 this moment, and when transmission package parameter 207 was set as 4, representing had 4 packages to be transmitted in a transmission cycle.Therefore, in transmission cycle, data transmission selector switch 201 can be orderly sent to the data bit from each package of device input by correspondence in input shift register 105-0,105-1,105-2 and 105-3, and will be stored in each Output Shift Register 106-0,106-1,106-2 and 106-3 interior each packet data position and be orderly sent to corresponding to installing.Therefore the shift register degree of depth of supposing the system is 16, within a transmission cycle, the data of 16 * 4=64 position can be arranged at most by transmitted in both directions.Identical concept also can be applicable under the Multi-ported Data transmission mode, the setting value that port number is controlled parameter 205 less than can be simultaneously with main device carry out data transmission in the situation of a maximum quantity of device (for example this example, port number is controlled parameter 205 and is set to 2 or 3).Thus, even system is not applied to the transmission mode of maximum port number, be no matter that transfer bus end pin position MOSI and MISO or I/O shift register all can effectively be used, can not cause waste.
Fig. 5 shows a described according to another embodiment of the present invention data transmission system 500.Data transmission system 500 comprises a plurality of data transmission device 501-0～501-1 and 502-0～502-7 and is coupled to Serial Peripheral Interface 503-0 and 503-1 between data transmission device, wherein data transmission device 501-0 and 501-1 are main device, and 502-0～502-7 is from device.In this embodiment, clock signal SPI_SCLK is common between data transmission device, main device 501-0 selects first group from device 502-0～502-3 by chip select signal SPI_SS1, and main device 501-1 selects second group from device 502-4～502-7 by chip select signal SPI_SS2.Main device 501-0 transmits data bit SPI_DO1[3:0 by transfer bus] to from device 502-0～502-3, wherein each data bit DO[0], DO[1], DO[2] with DO[3] sequentially be transferred into corresponding to installing 502-0～502-3.Main device 501-0 also by transfer bus since device 502-0～502-3 data with clock information SPI_DI1[3:0], each data bit DI[0 wherein], DI[1], DI[2] and DI[3] sequentially self-correspondingly be transferred into main device 501-0 from device 502-0～502-3.Similarly, main device 501-1 transmits data bit SPI_DO2[3:0 by transfer bus] to from device 502-4～502-7, wherein each data bit DO[0], DO[1], DO[2] with DO[3] sequentially be transferred into corresponding to installing 502-4～502-7.Main device 501-1 also by transfer bus since device 502-4～502-7 data with clock information SPI_DI2[3:0], each data bit DI[0 wherein], DI[1], DI[2] and DI[3] sequentially self-correspondingly be transferred into main device 501-1 from device 502-4～502-7.
The data transfer mode that is applied to data transmission system 500 can with reference to figure 1 and relevant paragraph, repeat no more in this.By finding out in Fig. 1, Fig. 2, Fig. 5, each element and data transmission device in data transmission system can flexibly be configured, wherein the transmission figure place that can support at most of data transmission system also can flexibly be designed according to different application demands, therefore above-described embodiment in order to clear elaboration concept of the present invention, is not only to limit scope of the present invention.in addition, according to data transmission system framework proposed by the invention, the data-transformation facility that not only can keep the Serial Peripheral Interface (SPI) of original four-wire system, (for example port number is controlled parameter 205 more can to pass through systematic parameter, transmission position parameter 206 and transmission package parameter 207 etc.) setting will input and export the data proper placement to each multi-level shift LD, utilize Serial Peripheral Interface (SPI) to carry out simultaneously the purpose that reads or write of long numeric data to reach, improve by this using value of Serial Peripheral Interface (SPI).
Though the present invention discloses as above with embodiment; so it is not to limit scope of the present invention, any those skilled in the art, without departing from the spirit and scope of the present invention; when can do a little change and retouching, so protection scope of the present invention is when being as the criterion with claim institute confining spectrum.
Claims (11)
1. a data transmission system, is characterized in that, described data transmission system comprises:
One first device and at least one the second device, wherein said first device is main device, described at least one the second device is from device; And
One serial peripheral interface is coupled between described first device and described at least one the second device, comprising:
One sequence clock pulse end is in order to transmit a clock pulse signal between described first device and described at least one the second device;
One chip selection end is in order to transmit a chip select signal between described first device and described at least one the second device, the transmission of log-on data by this;
One first transfer bus end installs from described first device extremely described at least one second in order to the transmission of data; And
One second transfer bus end installs to described first device from described at least one second in order to the transmission of data; And
One Programmable Logic Controller switches on a single port data transmission mode and a Multi-ported Data transmission mode in order to control described Serial Peripheral Interface;
Wherein when being coupled to described Serial Peripheral Interface more than described second device, described Serial Peripheral Interface switches to described Multi-ported Data transmission mode, carry out the Multi-ported Data transmission in order to control between described first device and described the second device, this moment, described first device transferred data to each described second device simultaneously by described the first transfer bus end, and described first device passes through described the second transfer bus end simultaneously from each described the second device receive data.
2. data transmission system as claimed in claim 1, is characterized in that, described Programmable Logic Controller is integrated in described first device, at least one described the second device or described Serial Peripheral Interface.
3. data transmission system as claimed in claim 2, it is characterized in that, described data transmission system also comprises a plurality of input shift registers and a plurality of Output Shift Register, be arranged in described first device, when described Serial Peripheral Interface switches to described Multi-ported Data transmission mode, described input shift register is respectively from described the second parallel receive data of device, and the parallel output data of described Output Shift Register difference are to described the second device.
4. data transmission system as claimed in claim 3, is characterized in that, described Programmable Logic Controller comprises:
One data transmission selector switch carries out data allocations in order to control parameter according to a port number, and wherein said port number is controlled parameter and represented the number that carries out simultaneously described at least one second device of data transmission with described first device.
5. data transmission system as claimed in claim 4, is characterized in that, described Programmable Logic Controller also comprises:
One transmission digit counter is in order to be accumulated at a data bits that has been transmitted in a transmission cycle, to obtain a count results;
One logic comparator, in order to described count results and a transmission position parameter are compared, obtaining a bit comparison result, wherein said transmission position parameter depends on a degree of depth of each input shift register and/or each Output Shift Register; And
One package comparer, in order to described bit comparison result and a transmission package parameter are compared, to obtain a package comparative result, the package sum that wherein said transmission package parameter representative is transmitted in described transmission cycle domestic demand, and the position sum that each package comprises determines according to a described transmission parameter.
6. a data transmission device, is characterized in that, described data transmission device comprises:
One serial peripheral interface comprises:
One sequence clock pulse end is in order to transmit a clock pulse signal at least one from device;
One chip selection end is in order to transmit a chip select signal, the transmission of log-on data by this;
One first transfer bus end is in order to transmit data to described at least one from device; And
One second transfer bus end is in order to receive described at least one data that transmit from device; And
One Programmable Logic Controller switches on a single port data transmission mode and a Multi-ported Data transmission mode in order to control described Serial Peripheral Interface;
Wherein when being coupled to described Serial Peripheral Interface more than a said slave device, described Serial Peripheral Interface switches to described Multi-ported Data transmission mode, carry out the Multi-ported Data transmission between described data transmission device and said slave device in order to control, transferring data to simultaneously each said slave device by described the first transfer bus end, and by described the second transfer bus end simultaneously from each said slave device receive data.
7. a programmable serial peripheral interface controller, in order to control a data-transmission mode of a serial peripheral interface, is characterized in that, described programmable serial peripheral interface controller comprises:
One data transmission selector switch carries out data allocations in order to control parameter according to a port number;
wherein said port number is controlled parameter and is represented the number that carries out simultaneously at least one second device of data transmission with a first device, described data-transmission mode switches on a single port data transmission mode and a Multi-ported Data transmission mode, described first device and described at least one the second device transmit data bit by described Serial Peripheral Interface, when being coupled to described Serial Peripheral Interface more than described second device, described Serial Peripheral Interface is switched to described Multi-ported Data transmission mode, carry out the Multi-ported Data transmission in order to control between described first device and described the second device, this moment, described first device transferred data to each described second device simultaneously by one first transfer bus end, and described first device passes through one second transfer bus end simultaneously from each described the second device receive data.
8. programmable serial peripheral interface controller as claimed in claim 7, it is characterized in that, when described Multi-ported Data transmission mode, a plurality of input shift registers that described data transmission selector switch is controlled described first device with respectively from each described the second parallel receive data of device, and a plurality of Output Shift Registers of controlling described first device with parallel output data respectively to each described the second device.
9. programmable serial peripheral interface controller as claimed in claim 8, is characterized in that, described programmable serial peripheral interface controller also comprises:
One transmission digit counter is in order to be accumulated at a data bits that has been transmitted in a transmission cycle, to obtain a count results; And
One logic comparator, in order to described count results and a transmission position parameter are compared, obtaining a bit comparison result, wherein said transmission position parameter depends on a degree of depth of each input shift register and/or each Output Shift Register.
10. programmable serial peripheral interface controller as claimed in claim 8, it is characterized in that, when a setting value of controlling parameter when described port number equals can be simultaneously to carry out the maximum quantity of described at least one the second device of data transmission with described first device, described data transmission selector switch will be sent to respectively each corresponding described input shift register by the described data bit of described the second parallel input of device, and will be stored in respectively parallel one second device that is sent to correspondence of described data bit of described Output Shift Register.
11. programmable serial peripheral interface controller as claimed in claim 8, it is characterized in that, a setting value of controlling parameter when described port number is when can be simultaneously carrying out the maximum quantity of described at least one the second device of data transmission with described first device, described data transmission selector switch will be orderly sent to described input shift register by the described data bit of the described second device input of correspondence, and the described data bit that will be stored in described Output Shift Register is orderly sent to corresponding described the second device.
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|---|---|---|---|---|
| CN102693200A (en) * | 2012-01-12 | 2012-09-26 | 河南科技大学 | SPI (serial peripheral interface) communication port based on CPLD (complex programmable logic device) |
| TWI471731B (en) * | 2013-03-29 | 2015-02-01 | Mediatek Inc | Memory access method, memory access control method, spi flash memory device and spi controller |
| IN2013MU02016A (en) * | 2013-06-13 | 2015-06-05 | Mediatek Inc | |
| CN104503934B (en) * | 2014-12-02 | 2017-10-24 | 天津国芯科技有限公司 | A kind of expansible serial transmission device |
| TWI567561B (en) * | 2015-11-26 | 2017-01-21 | 新唐科技股份有限公司 | Bus system |
| JP6457417B2 (en) * | 2016-03-22 | 2019-01-23 | ファナック株式会社 | Serial communication branch device and serial communication system |
| CN112506839B (en) * | 2020-12-07 | 2023-02-03 | 天津津航计算技术研究所 | One-to-many SPI bus switching method and device |
| CN115037411B (en) * | 2021-03-05 | 2024-03-19 | 信骅科技股份有限公司 | Signal receiving and transmitting system and signal receiver thereof |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101211326A (en) * | 2006-12-29 | 2008-07-02 | 佛山市顺德区顺达电脑厂有限公司 | Interface converting device |
| CN101359316A (en) * | 2007-08-03 | 2009-02-04 | 大唐移动通信设备有限公司 | Method and apparatus for implementing general-purpose serial bus USB OTG |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TW587790U (en) * | 2002-06-18 | 2004-05-11 | King Byte Information Corp | Device for adapting memory card interface to USB interface |
-
2010
- 2010-03-12 CN CN 201010132312 patent/CN102193888B/en active Active
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101211326A (en) * | 2006-12-29 | 2008-07-02 | 佛山市顺德区顺达电脑厂有限公司 | Interface converting device |
| CN101359316A (en) * | 2007-08-03 | 2009-02-04 | 大唐移动通信设备有限公司 | Method and apparatus for implementing general-purpose serial bus USB OTG |
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