CN102165529B

CN102165529B - Serial-connected memory system with output delay adjustment

Info

Publication number: CN102165529B
Application number: CN200980138194.9A
Authority: CN
Inventors: 吴学俊
Original assignee: Examine Vincent Zhi Cai Management Co
Current assignee: Nova chip Canada Company
Priority date: 2008-09-30
Filing date: 2009-09-17
Publication date: 2014-12-31
Anticipated expiration: 2029-09-17
Also published as: TW201027556A; WO2010037205A1; JP2012504263A; EP2329496A1; EP2329496A4; CN102165529A; KR20110081958A; JP5599852B2; JP2013008386A

Abstract

Systems and methods for correcting clock duty cycle and/or performing output delay adjustment are provided for application in serial- connected devices operating as slave devices. A master device provides a clock to the first slave device. Each slave device passes the clock to the next slave device in turn. The last slave device returns the clock to the master device. The master device compares the outgoing and returned clocks and determines if a duty cycle correction and/or an output delay adjustment is needed. If so, the master device generates and outputs commands for slave devices to perform duty cycle and/or output delay adjustment. The slave devices each have a circuit for performing duty cycle correction and/or output delay adjustment. In some implementations, each slave device is a memory device, and the master device is a memory controller.

Description

There is the serial memory system exporting and postpone adjustment

Technical field

The present invention generally relates to the solid state memory system with one group of serial memory device.

Background technology

Traditional nand flash memory system use a large amount of for ordering, the parallel signal of addressing and data transfer operation.This is the very general mode of config memory system and causes Dynamic System very fast.This random access memory device for such as DRAM (dynamic RAM), SRAM (static RAM) is especially true.

Owing to needing each storage arrangement be sent to by a large amount of parallel signals in accumulator system, bring a little problem in this way.System power supply also must have higher capacity, thinks the peak power that parallel signal conveying is higher.By using higher running frequency, the handling capacity of the write and read of traditional nand flash memory directly can be increased.Such as, the running frequency (for the tRC in nand flash memory, it equals 25ns) of current about 40MHz can be increased to about 100 to 200MHz.Although this method seems simple and direct, under so high frequency, signal quality has prominent question, and this is just provided with the restriction in practical application to the running frequency of traditional nand flash memory.

Especially, traditional nand flash memory uses the one group of I/O that walks abreast (I/O) pin and other element communication, and according to the word configuration expected, described pin number is 8 or 16, for receiving command instruction, receiving input data and provide output data.This is commonly referred to as parallel interface.High-speed cruising will cause well-known such as crosstalk, signal offsets the variation effect that communicates with signal attenuation, thus reduces signal quality.Above-mentioned parallel interface uses a large amount of pin to read and writes data.Along with the increase of input pin and number of, lines, many less desirable effects are also in increase.These effects comprise intersymbol interference, signal skew and crosstalk.

In order to solve some such problems, providing and there are several cascade system configurations that a group connects into the storage arrangement of ring.These comprise " Multiple Independent Serial Link Memory " (US20070076479A1), " Daisy Chain Cascading Devices " (US20070109833A1), " Memory with Output Control " (US20070153576A1), " Daisy chain cascade configuration recognition technique " (US2007233903A1) and " Independent Link and Bank Selection " (US2007143677A1), the invention of these applications is identical with of the present invention per capita, all comprise in the present invention by reference at this.These systems have serial input/output data pin usually, and are respectively used to enable and forbid serial input port and Serial output port to provide 2 control signals of the Memory Controller of the serial data communication with maximum flexibility.Some such memory system configuration adopt the shared bus topology being used for system clock distribution, and it is called as " share with clock system " or " multiple spot clock system ".Some such frameworks are used in each memory chip the point-to-point serial clock framework with DLL (delay lock loop) or PLL (phaselocked loop), with 2 clock signals in synchronous each storage arrangement, one of them is the input clock received from last device or controller, and another is the output clock being delivered to next device.

Summary of the invention

According to a broad aspect, the invention provides a kind of be used in multiple series connection from device from the method device, the method comprises: receive the order of specifying and adjusting clock duty cycle from main device; Receive input clock signal; Clock signal through duty cycle correction is produced from described input clock signal according to described order; Export the described clock signal through duty cycle correction.

In certain embodiments, be storage arrangement from device, and main device is Memory Controller.

In certain embodiments, the method comprises further: receive the order of specifying said slave device how to adjust the delay by being applied at least one signal exported by said slave device from main device; Receive at least one input signal, at least one input signal described at least comprises described input clock signal; For each of at least one input signal: the delay form producing described input signal according to described order; Export the described delay form of described input signal, the described delay form of described input clock signal comprises the delay form of the described clock signal through duty cycle correction.

In certain embodiments, receive to specify from main device and the order that clock duty cycle adjusts is comprised: receive the order comprising command identifier, it is duty cycle correction order that this command identifier identifies described order, and described order also comprises the data how instruction adjusts dutycycle.

Which in certain embodiments, receive order to comprise further and receive instruction and be used as will perform the unit address of described order from device of device.

In certain embodiments, the method comprises further: if described order has the unit address of the unit address of coupling said slave device, then perform according to described order the step producing the described clock signal through duty cycle correction; If it is the unit address of broadcaster address that described order has, then perform according to described order the step producing the described clock signal through duty cycle correction.

In certain embodiments, the clock signal produced through duty cycle correction comprises: clock signal a) producing half frequency from described input clock signal; B) clock signal of described half frequency is postponed with selected in multiple delay with half frequency clock signal be delayed; C) half frequency clock signal of described half frequency clock signal and described delay is combined to produce the described clock signal through duty cycle correction.

In certain embodiments, the described data that how instruction adjusts described duty cycle correction comprise the instruction of selected in described multiple delay.

According to the aspect of another broad sense, the invention provides a kind of be used in comprise main device and multiple series connection from the method the accumulator system of device, said slave device comprises at least the first from device and last from device, and described method comprises: in main device: a) export and be used as described first from the first clock signal of the input clock signal of device; B) receive second clock signal, it is the described last clock signal from device; C) produce the duty cycle correction order relevant to the dutycycle of described second clock signal and export described duty cycle correction order; In described multiple series connection from first of device from device: a) receive described first clock signal from described main device, as described first from the described input clock signal of device; B) clock signal is produced from described input signal; Described multiple series connection from device each other from device: a) receive the last clock signal from device, as the input clock signal from device; B) clock signal is produced from described input clock signal; Be used as from least one each of multiple tandem arrangements of device: a) receive described duty cycle correction order; B) clock signal through duty cycle correction is produced according to described duty cycle correction order from described input clock signal; C) the described clock signal through duty cycle correction is exported, as the clock signal of said slave device;

In certain embodiments, each is storage arrangement from device, and main device is Memory Controller.

In certain embodiments, the method comprises further: in main device: a) export at least one output signal, at least one output signal described comprises described first clock signal, as described first from the input clock signal of device; B) receive second clock signal, it is the described last clock signal from device; C) the phase deviation amount between described first clock signal and described second clock signal is determined; D) produce the output relevant to the phase deviation between described first clock signal and described second clock signal postpone to adjust order and export described export to postpone to adjust order.

In certain embodiments, produce the duty cycle correction order relevant to the dutycycle of described second clock signal and export described duty cycle correction order and comprise and produce for by arbitrarily specify the duty cycle correction order that perform of described multiple series connection from device.

In certain embodiments, produce the duty cycle correction order relevant to the dutycycle of described second clock signal and export described duty cycle correction order and comprise the duty cycle correction order produced for being performed from device by all described multiple series connection.

In certain embodiments, receive described duty cycle correction order and comprise: receive the order comprising command identifier, it is duty cycle correction order that this command identifier identifies described order, and comprises the data how instruction adjusts dutycycle.

In certain embodiments, the data that how described instruction adjusts described duty cycle correction comprise the instruction of selected in described multiple delay.

According to another broad aspect, the invention provides a kind of be used in comprise multiple series connection from the structure of device from device, should comprise from device: order input, for receiving the order of specifying and adjusting dutycycle from main device; Clock inputs, for receiving input clock signal; Duty-cycle correction circuit, for inputting the clock signal of generation through duty cycle correction according to control command from described clock; Clock exports, for exporting the described clock signal through duty cycle correction.

In certain embodiments, said slave device is storage arrangement.

In certain embodiments, described order input is also specified exporting the order postponing adjustment for receiving from described main device; Export delay regulating circuit to be used for according to described order from the described clock signal be delayed through the signal of duty cycle correction; The wherein said clock for exporting the described clock signal through duty cycle correction exports the clock signal of described delay.

In certain embodiments, should comprise further from device: command process circuit, for the treatment of described order, wherein said order comprises: identify the command identifier that described order is duty cycle correction order; The data of dutycycle how are adjusted with instruction.

In certain embodiments, should comprise further from device: unit address register; Wherein said order comprises the unit address which indicates perform described order from device further, if described unit address mates the content of described unit address register, said slave device is configured to perform described order.

In certain embodiments, this duty-cycle correction circuit comprises: a) clock divider circuit, for producing the clock signal of half frequency from described input clock signal; B) delay circuit, for being postponed the clock signal of described half frequency with half frequency clock signal be delayed by selected in multiple delay; C) combiner, for combining half frequency clock signal of described half frequency clock signal and described delay to produce the described clock signal through duty cycle correction.

In certain embodiments, this delay circuit comprises M unit delay part, M >=2, this duty-cycle correction circuit comprises further: N to M demoder, for by the signal decoding received on N number of incoming line be postpone described half frequency clock signal with half frequency clock signal be delayed in the selection of number of effective described unit delay part, N >=1.

According to another broad aspect, the invention provides a kind of system, comprising: as the multiple tandem arrangements from device according to claim 13, described multiple tandem arrangement comprises at least the first from device and last from device; Be connected to described first from device and the described last main device from device; Described main device is configured to export and is used as described first from the first clock signal of the input clock signal of device; Clock inputs, and for receiving second clock signal, described second clock signal is the described last clock signal from device; For determining the duty detecting device of the dutycycle of described second clock signal; Command generator, for generation of specifying the duty cycle correction order adjusted the clock duty cycle relevant to the dutycycle of described second clock signal; Wherein, be used as from first of described multiple tandem arrangement of device from device: a) receive described first clock signal from described main device, as described first from the described input clock signal of device; B) clock signal is produced from described input clock signal; Wherein, be used as from described multiple tandem arrangement of device each other from device: a) receive the last clock signal from device, as this input clock signal from device; B) clock signal is produced from described input clock signal; Wherein said multiple series connection is from least one of device: a) receive described duty cycle correction order; B) clock signal through duty cycle correction is produced according to described control command; C) the described clock signal through duty cycle correction is exported, as the clock signal of said slave device.

In certain embodiments, described system is accumulator system, and each is storage arrangement from device, and described main device is Memory Controller.

In certain embodiments, this accumulator system also comprises: phase detector, for determining the phase deviation amount between described first clock signal and described second clock signal; Wherein, described command generator also produces the output relevant to phase deviation amount and postpones to adjust and order; Wherein, in described multiple series connection from first of device from device: a) receive described first clock signal from described main device, as described first from the described input clock signal of device; B) clock signal is produced from described input clock signal; Wherein, described multiple series connection from device each other from device: a) receive the last clock signal from device, as the input clock signal from device; B) clock signal is produced from described input clock signal; Wherein said multiple series connection is from least one of device: a) receive described output and postpone adjustment order; B) input clock signal by postponing described device according to described control command produces the clock signal of described device.

In certain embodiments, described command generator is configured to produce the duty cycle correction order relevant to the dutycycle of described second clock signal, and exports described duty cycle correction order by producing the duty cycle correction order be used for by being used as to perform from the appointment one of described multiple tandem arrangement of device.

In certain embodiments, described command generator is configured to produce the duty cycle correction order relevant to the dutycycle of described second clock signal, and exports described duty cycle correction order by producing the duty cycle correction order be used for by being used as to perform from all described multiple tandem arrangement of device.

According to the aspect of a broad sense, the invention provides a kind of be used in multiple series connection from device from the method device, the method comprises and receives the order of specifying said slave device how to adjust the delay by being applied at least one signal exported by said slave device from main device; Receive at least one input signal, at least one input signal described at least comprises input clock signal; For each of at least one input signal: the delay form producing described input signal according to described order; Export the described delay form of described input signal.

In certain embodiments, described method comprises: export data output signal; Wherein at least one input signal comprises data input signal and the delay form wherein exporting described data input signal performs as the part exporting described data output signal, make: a) sometimes, data output signal is the described delay form of data input signal; B) sometimes, data output signal is the delay form of signal will produced from device this locality after postponing to be applied to the signal that produces from device this locality according to order.

In certain embodiments, receiving from main device specifies the order of the adjustment to the delay being applied at least one signal exported from device to comprise: it is export the order postponing the command identifier that adjustment is ordered that reception comprises the described order of mark, and described order also comprises the data how instruction adjusts described delay.

In certain embodiments, described method also comprises: for each of at least one input signal, if described order has the unit address of the unit address of coupling said slave device, perform the step producing the delay form of described input signal according to described order; For each of at least one input signal, if it is the unit address of broadcaster address that described order has, perform the step producing the delay form of described input signal according to described order.

In certain embodiments, for each input signal, the delay form producing described input signal comprises: a) postpone described input signal to produce the delay form of described input signal with selected in multiple delay.

In certain embodiments, the data that how described instruction adjusts described delay comprise the instruction of selected in described multiple delay.

In certain embodiments, described multiple input signal comprises: clock signal; Command strobes signal; Data strobe signal; Comprise the data-signal of order and data.

According to the aspect of another broad sense, the invention provides a kind of being used in comprise main device and be used as from the method the accumulator system of multiple tandem arrangements of device, said slave device comprises at least the first from device and last from device, described method comprises: in described main device: a) export at least one output signal, at least one output signal described comprises the first clock signal, as described first from the input clock signal of device; B) receive second clock signal, it is the described last clock signal from device; C) the phase deviation amount between described first clock signal and described second clock signal is determined; D) produce the output relevant to the phase deviation amount between described first clock signal and described second clock signal postpone to adjust order and export described export to postpone to adjust order.

In certain embodiments, described method comprises further: be used as from first of described multiple tandem arrangement of device from device: a) receive at least one output signal described from described main device, as described first from least one input signal corresponding of device; B) for each input signal, output signal is produced based on described input signal; Be used as from described multiple tandem arrangement of device each other from device: a) receive the last output signal from device, it corresponds at least one input signal of said slave device; B) for each input signal, output signal is produced based on described input signal; Described at least one from device, a) receive described output postpone adjustment order; And b) by producing described output signal according to the described delay form postponing the described input signal of adjustment order generation that exports.

In certain embodiments, described method comprises further: at least one output signal described of wherein said main device comprises multiple output signal.

In certain embodiments, the adjustment order that is delayed comprises the delay adjustment order from the specific execution device produced for by described multiple series connection.

In certain embodiments, the adjustment order that is delayed comprises the delay adjustment order performed from device produced for by all described multiple series connection.

In certain embodiments, comprise according to the described delay form postponing the described input signal of adjustment order generation that exports the delay form producing the described input signal postponed with selected in multiple delay.

In certain embodiments, the adjustment order that is delayed comprises: produce the order comprising command identifier, and this command identifier identifies described order and postpones adjustment order for exporting, and comprises the data how instruction adjusts delay.

In certain embodiments, the data that how described instruction adjusts delay comprise the instruction of selected in described multiple delay.

In certain embodiments, described method comprises further: described main device exports and postpones adjustment order, described output delay adjustment order adjusts delay, until described phase deviation is acceptable by increasing delay one unit delay part at one from device at every turn.

According to the aspect of another broad sense, present invention also offers a kind of be used in comprise multiple series connection from the structure of device from device, said slave device comprises: order input, how to perform for receiving instruction from main device the order exporting and postpone adjustment; Clock inputs, for receiving input clock signal; Export delay regulating circuit, for the clock signal be delayed from the input of described clock according to described order; Clock exports, for exporting the clock signal of delay.

In certain embodiments, said slave device is storage arrangement.

In certain embodiments, said slave device comprises: command process circuit, for the treatment of described order, wherein said order comprise mark described order be export postpone adjustment order command identifier, and comprise instruction how to adjust described export postpone data.

In certain embodiments, said slave device also comprises: unit address register; Wherein said order comprises the unit address which indicates perform described order from device further, if described device identification mates the content of described unit address register, said slave device is configured to perform described order.

In certain embodiments, described output delay regulating circuit comprises: for each of multiple input signals comprising described input clock signal, delay circuit postpones described input signal to produce the delay form of described input signal with selected in multiple delay.

In certain embodiments, each output delay circuit comprises M unit delay part, M >=2, described duty-cycle correction circuit also comprises: N to M demoder, signal decoding for receiving on N number of incoming line is the selection of the number of effective described unit delay part in the delay form producing described input signal, N >=1.

According to the aspect of another broad sense of the present invention, the present invention also provides a kind of accumulator system, comprising: multiple series connection is from device, and it comprises at least the first from device and last from device; Be connected to described first from device and the described last main device from device; Described main device is configured to export and is used as described first from the first clock signal of the input clock signal of device; Clock inputs, and for receiving second clock signal, it is the described last clock signal from device; Phase detector, for determining the phase deviation amount between described first clock signal and described second clock signal; Command generator, postpones to adjust for generation of the output relevant to phase deviation amount and orders; Wherein, in described multiple series connection from first of device from device: a) receive described first clock signal from described main device, as described first from the described input clock signal of device; B) clock signal is produced from described input clock signal; Wherein, described multiple series connection from device each other from device: a) receive the last clock signal from device, as the input clock signal from device; B) clock signal is produced from described input clock signal; Wherein said multiple series connection from device at least one: a) receive described output postpone adjustment order; B) produced the clock signal of described device by the input clock signal postponing described device according to described control command.

In certain embodiments, described command generator is configured to produce for postponing adjustment order by described multiple series connection from the specific output performed device.

In certain embodiments, described command generator is configured to produce for being postponed to adjust from the output that device performs by all described multiple series connection.

In certain embodiments, generation output postpones adjustment order and comprises: produce the order comprising command identifier, and it is that output postpones adjustment order that this command identifier identifies described order, and comprises the data how instruction adjusts output delay.

The clock duty cycle without the need to DLL or PLL provided for serial memory system corrects and/or the method and apparatus of phrase synchronization, and it generally includes the Memory Controller and multiple memory chip that connect into loop configuration.In certain embodiments, Memory Controller has phase place/duty cycle detector, for detecting clock signal all over the phase place after the whole ring of row and dutycycle, and each storage arrangement has one or more controller programmable delay line, and it is used to the phase place and/or the dutycycle that adjust this clock.These adjustment are carried out, until phase place detected by this Memory Controller and dutycycle are acceptable by the order sent from this Memory Controller.

Method and apparatus described herein can be applied to the semiconductor IC system of any kind of the conductor integrated circuit device with any kind, conductor integrated circuit device as have between neighboring devices general-purpose interface cascaded structure from device.The example of integrated circuit type comprises central processor unit, Graphics Processing Unit, display controller IC, disk drive IC, such as NAND flash-EEPROM, NOR flash-EEPROM, the storage arrangement of AND flash-EEPROM, DiNOR flash-EEPROM, serial flash-EEPROM, DRAM, SRAM, ROM, EPROM, FRAM, MRAM and PCRAM.

Accompanying drawing explanation

Fig. 1 is the system chart of the serial memory system with controller programmable duty cycle correcting scheme;

Fig. 2 is the block diagram of the storage arrangement with controller programmable duty cycle correcting scheme;

Fig. 3 is the block diagram of the programmable delay line for duty cycle correction;

Fig. 4 is the sequential chart that controller programmable duty cycle corrects;

Fig. 5 is the process flow diagram of duty ratio correction method;

Fig. 6 is the sequential chart writing duty cycle register order;

Fig. 7 is the block diagram for exporting the programmable delay line postponing adjustment;

Fig. 8 is the controller sequential chart exporting delay adjustment able to programme;

Fig. 9 performs the process flow diagram exporting the method postponing adjustment; With

Figure 10 writes the sequential chart exporting delay time register order.

Embodiment

Below in the detailed description of the specific embodiment of the invention, with reference to as wherein a part of Figure of description, the certain specific embodiments that the present invention can implement is made an explanation.It is enough detailed that these embodiments describe, the present invention is realized to enable those of ordinary skill in the art, should be appreciated that and also can use other embodiments, and logic, machinery, electric changing with other can be made without departing from the present invention.Therefore, detailed description below does not should be understood to restriction the present invention, and protection scope of the present invention is determined by appended claim.

Quoted in the introduction those memory system configuration adopt the shared bus topology for system clock distribution, it is called as " sharing clock system " or " multiple spot clock system ".If system clock is applied to too many storage arrangement concurrently and this clock signal is too far away from clock source transmission, the distance that then total load of clock signal and clock transmit in the physical layout of accumulator system can limit maximum operation clock frequency, this clock source normally Memory Controller.

Some memory system configuration quoted in background technology are used in each storage arrangement the point-to-point serial clock framework with DLL or PLL, with the clock signal of two in synchronous memory devices, one of them is the input clock received from last device or controller, and another is the output clock being delivered to next device.But each storage arrangement has DLL or PLL on sheet can cause a large amount of power consumptions.Use DLL or PLL on sheet, various chip to chip clock delay (by various interconnection load and different such as multi-chip stacking or encapsulation wire-bonded load and cause) accumulated by a large amount of tandem arrangement, and be unacceptable for system cloud gray model.

With reference now to Fig. 1, show the system chart of the serial memory system adopting controller programmable duty cycle correcting scheme, this serial memory system always is labeled as 101.Accumulator system 101 comprises Memory Controller 10, as the master control set being connected to first memory device 100-1.Storage arrangement 100-1 is that from first of device, these connect into loop configuration from device to comprise device 100-1 to 100-8 a series of, and last device 100-8 connects and gets back to Memory Controller 10.In the example shown, provide highly multiplexed unidirectional point-to-point bus architecture, with from Memory Controller 10 by such as ordering, the information transmission of address and data is to storage arrangement 100-1 to 100-8.This bus architecture comprises from Memory Controller 10 to each link the link 90 of first memory device 100-1 and every a pair adjacent memory device, these comprise link 90-1 to 90-7, and the link 90-8 between last storage arrangement 100-8 and Memory Controller 10.

In the example shown, each link comprises the one group of signal exported by last device (Memory Controller 10 or storage arrangement), for being received by following device.Each link comprises one group of output port of last device, one group of input port of following device and the physical interconnections between output port and input port.For convenience's sake, the signal exported with them is named by output port, and the signal received with them is also named by input port.In the example shown, the signal (and output port) of last device is called as CSO (command strobes output), DSO (data strobe output), Qn (data output), CKO/CKO# (Differential clock output signal).The corresponding signal (and input port) of following device is called as CSI (command strobes input), DSI (data strobe input), Dn (data input), CKI/CKI# (differential clock input signal).Other port or signal (such as, CE# (chip is enabled) or RST# (reset) or energization pins) can also be had, in order to better understand and simplify and do not illustrate.Physical interconnections comprises differential clocks bus S111, S111-1 to S111-8 for differential clock signal, for S112, the S112-1 to S112-8 of command strobes, for S113, the S113-1 to S113-8 of data strobe, with for S114, the S114-1 to S114-8 of data.

In certain embodiments, data export Qn and data input Dn can have different data widths, arrange, n=0 for 1 link; 2 links are arranged, n=0,1; 4 links are arranged, n=0,1,2,3; 8 links are arranged, n=0,1,2,3,4,5,6,7; Etc..In certain embodiments, the width of link can be programmed by link configuration register, to utilize the valid data input and output pin of 1,2,4 or 8 device encapsulation.As long as these storage arrangements and the device with less or larger maximum link width are programmed to use and identical link width, above-mentioned feature allows them to run with loop configurations together.See such as " Switching Method of Link and Bit Width " (WO 2008/070978), be all contained in this by reference at this.

CKI/CKI# is input clock.The command/address bag on the Dn port of CSI cropping is latched at the rising edge of CKI or the negative edge of CKI#.Latch by the data packets on the Dn of DSI cropping at the rising edge of CKI or the negative edge of CKI#.

CKO/CKO# is the output clock of the delay form of CKI/CKI#.CSO, DSO and Qn signal with the negative edge of the rising edge of CKO or CKO# for reference; Such as wrap in the negative edge of the rising edge of CKO or CKO# by the read data on the Qn of DSO cropping accessed.

When command strobes input (CSI) is high, latch the command/address bag by Dn at the rising edge of CKI or the negative edge of CKI#.

Command strobes exports the echoed signal that (CSO) is CSI.It repeats CSI conversion with stand-by period tlOL, in a particular embodiment, and 2 stand-by period clock period that stand-by period tlOL is is reference with the negative edge of the rising edge of CKO or CKO#.The stand-by period of 2 clock period realizes details; More generally, it can be the clock period of any amount being suitable for given design.

When data strobe input (DSI) is high, and when storage arrangement is " reading mode ", it enables read data outgoing route and Qn impact damper (not shown).If DSI is low, Qn impact damper keeps the data of previously access.When DSI is height, storage arrangement is " WriteMode ", it is enabled Dn impact damper and receives data packets at the rising edge of CKI or the negative edge of CKI#.

Data strobe exports the echoed signal that (DSO) is DSI.It repeats DSI conversion with the stand-by period tlOL that the negative edge of the rising edge of CKO or CKO# is reference.As already pointed out, tlOL is 2 clock period in a particular embodiment.

Data input signal Dn (n=0,1,2,3,4,5,6 or 7) carries order, address and/or input data information.As fruit chip is configured to " 1 linking scheme ", D0 is unique useful signal and in a byte of 8 clock period receiving packages.As fruit chip is configured to " 2 linking schemes ", D0 and D1 is useful signal and in a byte of 4 clock period receiving packages.As fruit chip is configured to " 4 linking schemes ", D0, D1, D2 and D3 are useful signal and in a byte of 2 clock period receiving packages.As fruit chip is configured to " 8 linking schemes ", D0, D1, D2, D3, D4, D5, D6 and D7 are useful signal and in a byte of 1 clock period receiving package.

Data output signal Qn (n=0,1,2,3,4,5,6 or 7) carries output data during read operation, or ignore receive on Dn order, address or input data.As fruit chip is configured to " 1 linking scheme ", Q0 is unique useful signal and sends a byte of bag 8 clock period.As fruit chip is configured to " 2 linking schemes ", Q0 and Q1 is useful signal and sends a byte of bag 4 clock period.As fruit chip is configured to " 4 linking schemes ", Q0, Q1, Q2 and Q3 are useful signal and send a byte of bag 2 clock period.As fruit chip is configured to " 8 linking schemes ", Q0, Q1, Q2, Q3, Q4, Q5, Q6 and Q7 are useful signal and send a byte of bag 1 clock period.

Should be expressly understood that, they comprise for neighboring devices to and the accumulator system of series connection between the port that transmits relevant with concrete realization with the quantity of signal, must not be those described in Fig. 1.More generally, between often pair of connected device, a clock signal is at least transmitted.Can also transmit other signal between the device be connected, these concrete example provides above.Being also noted that, the specific quantity of storage arrangement, 8 in the example of Fig. 1, is the details relevant with specific implementation.In series architecture, the device of any suitable number can be interconnected.Note, expression " series connection " within a context refers to the arranged in series of storage arrangement, one then another, instead of the character of link between often pair of neighboring devices, it can be serial or parallel connection in nature.

Memory Controller 10 comprises phase detector 11, duty detecting device (duty detector) 13 and command generator 12.In certain embodiments, Memory Controller 10 only comprises phase detector 11, only performs to export in this case to postpone adjustment.In certain embodiments, Memory Controller 10 only comprises duty detecting device 13, only performs duty cycle correction in this case.In certain embodiments, comprise phase detector 11 and duty detecting device 13, can perform in this case and export delay adjustment and duty cycle correction.Supposition is last a kind of situation in the following detailed description.Phase detector 11 and duty detecting device 13 are connected to command generator 12 respectively by signal bus S11 and S12.Command generator 12 has the output signal bus S 13 being connected to CSO and Qn port, and via these ports, it can export order.

Memory Controller 10 drives differential clocks bus from its port CKO/CKO#, S111, and 8 storage arrangement 100-1 to 100-8 pass through their clock port CKI/CKI# with the CKO/CKO# port accepts differential clocks bus of circulation style from last device of connecting.Memory Controller 10 drives 3 differential bus S112, S113 and S114 respectively by its port CSO, DSO and Qn.First memory device 100-1 receives 3 bus S112, S113 and S114 respectively by its port CSI, DSI and Dn, and first memory device 100-1 drives (repetition) 3 corresponding bus S112-1, S113-1 and S114-1 respectively by its output port CSO, DSO and Qn again with the stand-by period of 2 clock period (=tIOL).Second memory device 100-2 receives 3 bus S112-1, S113-1 and S114-1 respectively by its input port CSI, DSI and Dn.The method is applied to 8 whole storage arrangement 100-1 to 100-8, last bus S112-8, S113-8 with S114-8 to be connected with Dn respectively by input port CSI, DSI of Memory Controller and to get back to Memory Controller 10.

Be in operation, in order to carry out duty cycle correction, the dutycycle of CKI/CKI# monitored by duty detecting device 13, and CKI/CKI# is the clock input after having have passed device 100-1 to 100-8 all in ring.If duty detecting device 13 detects duty cycle error from CKI/CKI#, namely depart from the dutycycle of expectation dutycycle, it sends " Duty_Add " by signal bus S 12 and indicates dutycycle be shorter than the dutycycle of expectation and should be extended, or sends " Duty_Sub " and indicate dutycycle be longer than the dutycycle of expectation and should be shortened.Responsively, command generator 12 produces suitable " writing duty cycle register " order bag.

Be in operation, postpone adjustment to export, the phase place of CKI/CKI# monitored by phase detector 11.If phase detector 11 detects the phase error (PE) between CKI/CKI# and CKO/CKO#, it sends " PE " signal by signal bus S11.Responsively, command generator 12 produces suitable " write and export delay time register " order bag.

Command generator 12 sends suitable order bag according to the signal received at S11 and S12, and sends command information by signal bus S13 and CSO, Qn port.

With reference now to Fig. 2, show the block diagram of the example embodiment of the storage arrangement 100-1 to 100-8 of Fig. 1.Device always is labeled as 100, comprises memory core 150, command/address bag logical circuit 130, packet logical circuit 140 and duty cycle correction logical circuit 120.Memory core 150 according to the difference of design can be the memory cell array of monomer or its can be the memory cell array of many bodies.Packet logical circuit 140 processes and preserves be necessary data transmission information.As described in detail later, command/address bag logical circuit 130 processes all command instructions of being transmitted by internal signal " dn_lat " and/or address information according to internal control signal " csi_lat ".

Clock input is managed

Device 100 comprises clock input sink 102D for CKI/CKI#, and it can be such as difference type input buffer, to process differential clocks input CKI and CKI#.The external interface level conversion of CKI/CKI# signal is the internal logic levels of internal clock signal " cki_i " by clock input sink 102D.Internal clock signal cki_i may be used for other internal logic circuit block for different operating.As will be described in detail below, duty cycle correction logical circuit 120 obtains internal clock signal cki_i, and produces the clock signal clk_dcc through duty cycle correction.Clock signal " clk_dcc " through duty cycle correction is postponed by controller programmable delay line PDL2 105D, and its inhibit signal " clk_dcc_d " is finally driven to the input port of output driver block 108D, output driver block 108D exports external clock output signal CKO/CKO#.

Command strobes input processing

Device 100 comprises command strobes receiver 102A, and it produces the signal " csi_i " be buffered according to CSI input signal.The signal csi_i be buffered is connected to the D port of D flip-flop 103A.Trigger 103A is driven by clock signal " cki_i ", and latches the state of " csi_i " signal at each rising edge of " cki_i ".The signal be latched " csi_lat " is supplied to command/address bag logical circuit 130, and is supplied to the D port of another trigger 103E, its clock input port is driven by the clock signal clk_dcc through duty cycle correction.The output signal " cso_i " of trigger 103E is postponed by controller programmable delay line PDL2 105A, and its inhibit signal " cso_d " is finally driven to the input port of output driver block 108A, output driver block 108A exports external signal CSO subsequently.The bypass of corresponding CSI to CSO, two-stage flip-flop logic circuit 103A and 103E provides being input to of two clock period to export the stand-by period (=tIOL).

Data strobe input processing

Device 100 comprises data strobe input sink 102C, and it produces the signal " dsi_i " be buffered according to DSI input signal.The signal " dsi_i " be buffered is connected to the D port of D flip-flop 103C.Trigger 103C is driven by clock signal " cki_i ", and latches the state of " dsi_i " signal at each rising edge of " cki_i ".The signal be latched " dsi_lat " is supplied to command/address bag logical circuit 130 and packet logical circuit 140, and is supplied to the D port of another trigger 103G, its clock input port is driven by the clock signal clk_dcc through duty cycle correction.The output signal " dso_i " of trigger 103G is postponed by controller programmable delay line PDL2 105C, and its inhibit signal " dso_d " is finally driven to the input port of output driver block 108C, and output driver block 108C exports external signal DSO.The bypass of corresponding DSI to DSO, two-stage flip-flop logic circuit 103C and 103G provides identical being input to of two clock period to export the stand-by period (=tIOL).

Data processing

Device 100 comprises data sink 102B, for receiving external signal Dn.Note, the quantity of receiver 102B can be one or more according to the bit width of Dn port.Such as, if Dn port is designed to D0, D1-D7, for the data I/O implementation of 8 bit wides, then receiver 102B will by repetition 8 times.The output " dn_i " of receiver 102B is provided to the D port of D flip-flop 103B.Trigger 103B is driven by clock signal " cki_i ", and latches the state of " dn_i " signal at each rising edge of " cki_i ".The signal " dn_lat " be latched is provided to command/address bag logical circuit 130, and is provided to packet logical circuit 140.The signal " dn_lat " be latched also is provided to an input port of multiplexer 104.Another port of multiplexer 104 is driven by the signal " core_data " from packet logical circuit 140.The output of multiplexer 104 is connected to the D input end of trigger 103F, the input end of clock of trigger 103F is driven by the clock signal clk_dcc through duty cycle correction, and trigger 103F latches the state of the output of multiplexer 104 at each rising edge of " clk_dcc ".The signal " q_i " be latched is postponed by another controller programmable delay line PDL2 105B, and its inhibit signal " q_d " is finally driven to the input port of output driver block 108B, and output driver block 108B exports external signal Qn.For the bypass of Dn to Qn, two-stage flip-flop logic circuit 103B and 103F provides identical being input to of two clock period to export the stand-by period (=tIOL).

Internal signal dn_i comprises command context (as inputted institute's cropping by command strobes) and data input (as inputted institute's cropping by data strobe) (in other instances).Each device has unit address, and in certain embodiments, unit address is kept in unit address register 131.Each order comprises unit address part, and it comprises the unit address of a storage arrangement of order institute addressing.Can also there is broadcast address, this requires by the order of all device process.Storage arrangement 100 assigns to process each order by testing fixture Address Part.If the unit address that the unit address information in the command/address bag received and storage arrangement 100 oneself are preserved matches, then this command/address bag logical circuit 130 processes this order, and sends " id_match " signal to mark this order for this storage arrangement.This id_match signal is used to the data flow path handling multiplexer 104.As the result of unit address matching process, " if id_match " be high logic state (more generally, be in defined " matching status "), multiplexer 104 is selected to export " core_data ", makes the data from memory core 150 can be transferred to trigger 103F.On the other hand, as the result of unit address matching process, " if id_match " be low logic state (more generally, be in defined " not matching status "), multiplexer 104 is selected to export " dn_lat ", makes the data received from data input Dn can be transferred to trigger 103F with retransmitted at output Qn.

Such multiplexer 104 allows to select between the following option: data a) received from data input Dn by selecting the dn_lat input of multiplexer 104 to carry out bypass, and b) by selecting the input of the Nuclear Data of multiplexer 104 to export core_data.Usually signal " core_data " is transferred to packet logical circuit 140 from memory core 150, such as the request from Memory Controller 10 as " page reading " operation a part.Subsequently, after completing " page reading " operation, Memory Controller 10 can operate to this storage arrangement request " burst reading " with the order being addressed to storage arrangement.In this case, the corresponding address information of unit address part is ordered and is comprised in storage arrangement process " burst reading ".If the unit address that the unit address information in the command/address bag received and storage arrangement 100 oneself are preserved matches, then this command/address bag logical circuit 130 sends " id_match " signal, to handle the data flow path of multiplexer 104.As the result of unit address matching process, if " id_match " is high logic state, multiplexer 104 is selected to export " core_data ", makes the data being previously transferred to packet logical circuit 140 from memory core 150 can be transferred to trigger 103F.

Note, be addressed to storage arrangement in order, when this order is not burst read-out command, in certain embodiments, although, there are not the data that will export, but still select the core_data input of multiplexer 104.Under these circumstances, this core_data signal can be stationary singnal.This causes data input Dn not to be resent to next device.This can reduce the power consumption in this device by the needs eliminating the data relevant to the order not being addressed to this device of device process subsequently.This sequence number submitted on January 23rd, 2008 is no.12/018, describes in detail in the U. S. application " Semiconductor Device and Method for Reducing Power Consumption in a System Having Interconnected Devices " of 272.

Therefore, in certain embodiments, data input signal Dn delay form as data output signal (Qn) one-component and produce.Some time, data output signal is the delay form of data input signal.For described embodiment, this will be the situation when there is content in data input signal, and it is not used in particular memory device, and other scheme is also possible.And, according to order by after postponing to be applied to signal that storage arrangement this locality produces, some time, data output signal comprises the delay form of signal that storage arrangement this locality produces.For described embodiment, the signal that storage arrangement this locality produces is called as core_data, and it exports from packet logical circuit 140, but other scheme is possible.

Command/address bag logical circuit 130 has DCR (duty cycle correction register) 132 and ODR (output delay time register) 134, DCR 132 produces the output DCR<0:3> of duty-cycle correction circuit 120, to control the quantity of duty cycle correction, the execution of this duty cycle correction is described in detail as follows, ODR 134 produces packet delay line 105A, 105B, the output ODR<0:1> of 105C and 105D, to control to export the quantity postponed, the application that this output postpones is as described in detail by below.One of effective order is " writing duty cycle correction register " order, for numerical value is write DCR 132.Similarly, one of effective order is " write and export delay time register " order, for numerical value is write ODR 134.

Write duty cycle correction register command

The use " write duty cycle correction register " and order takes implementation described herein, wherein by numerical value being write duty cycle correction register to control in the quantity performing the delay be employed in duty cycle correction.More generally, any order having and make device setting how perform duty cycle correction effect can be adopted, be referred to as duty cycle correction order herein.Therefore, described " writing duty cycle correction register " order can think the concrete example of duty cycle correction order.

Write and export delay time register order

" write and export delay time register " use of ordering and have employed described implementation, wherein by numerical value write is exported the quantity that delay time register controls the delay be employed.More generally, any order having and make device that the quantitative effect of institute's application delay is set can be adopted, be called to export to postpone to adjust herein and order.Therefore, described " write and export delay time register " order can be thought to export the concrete example postponing adjustment order.

Duty cycle correction

In the example shown, duty-cycle correction circuit 120 comprises Clock dividers 123 and controller programmable delay line 121, and controller programmable delay line 121 comprises " 4 to 16 demoder " block and " programmable delay line (PDL1) ".Clock dividers 123 and respective output clk_ref and clk_del of controller programmable delay line 121 are imported into XOR (XOR) door 122, and the output of XOR gate 122 is the clock clk_dcc through duty cycle correction.

Clock dividers 123 obtains outputing signal clk_ref, and its frequency is the half of input signal " cki_i ".Clock divider circuit is known in the art.In shown particular example, Clock dividers 123 comprises D flip-flop 103D, and it is driven by its clock input port by internal clock signal cki_i.The output port Q of D flip-flop 103D is connected to input port D by phase inverter logical circuit 124, to obtain the output signal of half frequency.

Controller programmable delay line 121 produces output signal clk_del, and it is the delay form of clk_ref.By the selection signal determination retardation of " 4 to 16 demoder " logic circuit block, the selection signal of " 4 to 16 demoder " logic circuit block is controlled by the DCR<0:3> signal message received from command/address bag logical circuit 130.Xor logic door 122 receives 2 half clock signal clk_ref and clk_del, and exports the full clock signal clk_dcc through dutycycle adjustment.

Fig. 3 is the block diagram of the example embodiment of programmable delay line 121 for duty cycle correction, and duty cycle correction such as may be used for the duty-cycle correction circuit 120 of Fig. 2.Each respective input that half frequency clock signal clk_ref is driven to 16 unit delay block UNIT_0 to UNIT_15.Each unit delay block has same structure, will describe unit delay block UNIT_15 by way of example.Unit delay block comprises 2 NAND (with non-) logic gate 1211 and 1212 and an inverted logic door 1213.One NAND logic gate 1211 receives clk_ref input in its first input, receives the output from 4 to 16 demoders 1210 in its second input.The output of the one NAND logic gate 1211 is imported into the first input of the second logic NAND door 1212.For unit delay block UNIT_15, the second input of the second logic NAND door 1212 is connected to Vdd.For all unit delay blocks except rightmost unit delay block UNIT_0, the output of the 2nd NAND door 1212 is connected to the second input of the 2nd NAND door 1212 of next unit delay block by phase inverter 1213.The output of the 2nd NAND door of rightmost unit delay block UNIT_0 is connected by phase inverter and produces total output clock clk_del signal.4 to 16 decoder blocks 1210 have the input bus DCR<0:3> of 4 bit wides, as its input.Decoder block 1210 decoding inputs and exports 16 bit wide bus SEL<15:0>, and wherein every bar line of bus is connected to each of 16 unit delay blocks.Shown unit delay logical circuit is for generation of the known circuit engineering of register control lag locking ring.Also other unit delay logic circuit can alternatively be adopted.The use of 16 unit delay blocks is details relevant to specific implementation.Such as, more generally, N to M demoder can be adopted to be M control signal by the signal decoding that N number of input line receives, for M unit delay block, wherein N >=1 and M >=2.

Be in operation, " 4 to 16 demoder " logical circuit 1210 produces 16 SEL<15:0> and exports, make 16 to select in signals only 1 be high logic state, select signals to be all low logic state for other 15.Therefore, only have selected 1 unit delay block by clk_ref Signal transmissions by the unit delay block on the right of this selected unit delay block.Control inputs DCR<0:3> inputs for selecting which unit delay block process clk_ref.The minimum delay is selected by selecting rightmost unit delay block UNIT_0, in this case, clk_del is the clk_ref signal postponed by a unit delay block, and by selecting leftmost unit delay block UNIT_15 to select maximum-delay, in this case, clk_del is the clk_ref signal postponed by whole 16 unit delay blocks.

For most treatment technology, the unit delay amount of shown unit delay block is approximately 100ps ~ 150ps.But, in certain embodiments, adopt thinner unit delay circuit block, to realize having the higher running frequency more carefully postponing regulating power.Unit delay time is identified as in figure 3 " tUD ", and the total delay time of whole programmable delay line is identified as " tPDL1 ", and it is " tUD " 16 times.

In certain embodiments, because SEL<7> position is in the centre position of lag line, the default setting of bootloader has logic high state in SEL<7> position.But in other design variation, default setting can be different, in order to prepare for running with highest frequency, recommend that there is minimum delay setting.

Fig. 4 is the example of the sequential chart of controller programmable duty cycle trimming process, and as shown in Figure 3, except CKI, it is the original input clock signal by carrying out duty cycle correction to wherein all signals.Only in order to example is convenient, this sequential chart shows the clock input signal CKI of a unusual distortion at top.Half clock signal clk_ref is from " Clock dividers " block 123 of Fig. 2, and two rising edge alignment of its rising edge and negative edge and CKI.Suppose for this example, such as, when showing the DCR<0:3> numerical value that is set to " 0111b " for being initialised without any change, the dutycycle of the distortion of clock signal clk_dcc is such as 45% to open, and 55% closes.After DCR<0:3> numerical value change is " 1000b ", be activated the result changing to SEL (8) and be activated from SEL (7) as selection control programmable delay line 121, the dutycycle of this clock signal clk_dcc is corrected as 50% and opens and 50% pass.

The control of duty cycle correction

Recall, the content of DCR 132 is used to the retardation controlling to be caused by the controller programmable delay line 121 in duty-cycle correction circuit 120, controls duty cycle correction thus.As mentioned above, the content of DCR 132 can write with " writing duty cycle register " order.

Fig. 5 is the process flow diagram of the duty cycle correction process from controller visual angle gained.The method starts from block 5-1, the power supply of device for opening.Now, the lag line that initialization is all is also all device distributor addresses.At block 5-2, Memory Controller 10 uses duty detecting device 13 to monitor the dutycycle of CKI/CKI#.If there is duty cycle error, block 5-3 selects "Yes" path, then send " Duty_Add " or " Duty_Sub " signal S12 at block 5-4 duty detecting device 13.After this, command generator 12 sends " writing duty cycle register " order with numerical value " DCR+1 " or " DCR-1 ".If still there is duty cycle error, block 5-6 selects "Yes" path, then the method turns back to step 5-4, to adjust duty cycle register further.If no longer there is duty cycle error, block 5-6 selects "No" path, then at this moment complete duty cycle correction at 5-7.Similarly, if duty cycle error do not detected at block 5-3, then also the method is completed at 5-7.

Table 1 is below the example command package definition for writing duty cycle register (DCR).First byte is " unit address (=DA) " part, and the second byte is command code (=CMD=FAh), and the 3rd byte comprises register value (=DCR<0:3>).In certain embodiments, provide broadcast address, such as FFh.If DA is set to broadcast address, mean that this order is broadcasting command, therefore expect that each storage arrangement performs this order.Otherwise the particular memory device of only mating this DA performs this order.In certain embodiments, in order to make controller 10 have more dirigibility, also achieve " reading duty cycle register " order.

Table 1. is for the example command package definition of duty cycle register (DCR)

Order	First byte	Second byte	3rd byte
				Write duty cycle register (DCR)	DA	FAh	DCR<0:3>

^*attention:

1) if DA (unit address) is FFh (=255d), it is broadcasting command, so each device is by this order 2 of response) DA=unit address

Table 2 is example position definition of duty cycle register (=DCR).Show pure exemplary definition, if therefore system configuration needs unit delay to adjust thinner granularity, in order to adapt to the better manageability of programmable delay line, this table can easily be expanded.Such as, if Bit<7:0> is input as " 0000 1000b=08h " from controller, DCR<3:0> will only accept Bit<3:0> (=" 1000b ") for effective register value and upper 4 Bit<7:4> will be left in the basket.But, in other design variation, thinner unit delay circuit can be realized for higher frequencies of operation, and other position configuration can be used.

The example position definition of table 2 duty cycle register and output delay time register

Fig. 6 operates the example of the sequential chart of " writing duty cycle register " order packet sequence based on SDR (single data rate).In the timing diagram, in the T1 moment, the negative edge of the rising edge of CKI or CKI# latches the high state of CSI and the DA (=unit address=00h) information simultaneously latched on Dn port.If DA is set to FFh (=metric 255), this means that " writing duty cycle register " order is broadcasting command, so expect that each storage arrangement performs this order.In certain embodiments, this broadcasting command is used to duty cycle correction operation.But this disclosed circuit also allows duty cycle correction operation in isolated system to adjust more flexibly.At next rising edge time T2, storage arrangement latches CMD (=order=FAh) information, rises on a third along T3, DCR (=duty cycle register numerical value=08h) information.CSO exports and Qn output port repeats CSI respectively with two clock latency tIOL (=input to export stand-by period) and inputs and Dn input signal.There is the definition of another stand-by period, it is tWDCR (=write the duty cycle register stand-by period), and it writes the time of duty cycle register bag and the time for processing dutycycle adjustment in duty-cycle correction circuit 120 middle controller programmable delay line 121 for process in memory chip.In certain embodiments, as shown in Figure 6, tWDCR numerical value is set to 4 clock period.After the tWDCR time (such as, at T8), other order bags any can be sent to storage arrangement by Memory Controller 10.

All devices in described embodiment hypothesis series architecture realize duty cycle correction.More generally, at least one device realizes duty cycle correction.

Export and postpone adjustment

Refer again to Fig. 1, provide described programmable delay line 105A, 105B, 105C and 105D make programmably delay output signal CSO, Qn, DSO and CKO/CKO# to allow phase correction.Fig. 1 also illustrates and exports delay time register signal bus ODR<0:1>, and it connects 2 to 4 decoder logic blocks 106.2 to 4 decoder logic blocks 106 export 4 and select signal bus SEL2<0:3>.These SEL2<0:3> select signal to be all connected to 4 controller programmable delay lines 105A, 105B, 105C and 105D.

Fig. 7 illustrates for exporting the exemplary circuit block embodiment postponing adjustment.In the example shown, programmable delay line 105A, 105B, 105C and 105D comprise 4 unit delay parts, its with use in Fig. 3 identical.This means to be only 4/16 of the delay scope of the adjustment of dutycycle to exporting the scope postponing adjustment.But this is only specific embodiments, the delay element of other quantity alternatively can be adopted.Each programmable delay line 105A, 105B, 105C and 105D receive respective signal cso_i, q_i, dso_i and clk_dcc input as lag line, and produce output cso_d, q_d, dso_d and clk_dcc_d of respective delay.If accumulator system has multidigit export configuration, such as 8 bit wide I/O configurations, q_i and q_d signal will correspondingly increase, and such as quantity is 8, and also correspondingly increase for the quantity of the delay line block of q_i and q_d, and such as quantity is 8.

Be in operation, " 2 to 4 demoder " logical one 06 produces SEL2<0:3> and exports, make 4 to select in signals only 1 be high logic state, other 3 select signals to be logic low state.Respective input signal is passed through remaining unit delay Bulk transport the right to selected unit delay block by only selected unit delay block.Which unit delay block control inputs ODR<0:1> for selecting input respective for process.The minimum delay is selected by selecting rightmost unit delay block UNIT_0, in this case, each output signal is its respective input signal postponed by 1 unit delay block, otherwise, maximum-delay is selected by selecting leftmost unit delay block UNIT_3, in this case, each output signal is its respective input signal postponing units chunk postpone by 4.

" 2 to the 4 demoder " logical one 06 with 4 unit delay blocks is achieved in this exemplary circuit design.But, more generally, the delay unit of required any amount and corresponding decode logic can be used.Default delay can be used during bootloader to arrange.In this example, default selection such as can be set to SEL2<0>, and storage arrangement will have the delay of minimum number for each outgoing route at power supply opening or in some other design variation after hard replacement.4 unit delay blocks are used to be specific implementations.Such as, more generally, N to M demoder can be adopted to be M control signal by the signal decoding received on N number of incoming line, for M unit delay block, wherein N >=1 and M >=2.

Fig. 8 exports for controller is able to programme the example sequential chart postponing adjustment.Be depicted as the clock clk_dcc through duty cycle correction of the content changing front and rear exporting delay time register, and the delay form clk_dcc_d of this signal.Can find out, at output delay time register from after " 00b=0d " changes to " 01b=1d ", the clock of delay has been delayed by quantity 2x tUD, but before adjustment, it has been delayed 1x tUD.The command strobes postponed before also show output after adjustment exports cso_i, and the output cso_d of this delay adjustment.Again, before output delay time register changes, the command strobes of delay has been postponed 1x tUD.After output delay time register changes, the command strobes of delay has been postponed quantity 2x tUD.

Export the control postponing adjustment

The content recalling ODR 134 is used to the retardation controlling to be caused by lag line 105A, 105B, 105C and 105D, controls thus to export to postpone adjustment amount.As mentioned above, the content of ODR 134 can write with " write and export delay time register " order.

When the phase detector 11 in Memory Controller 10 detect there is unacceptable phase differential between itself CKI/CKI# and CKO/CKO# signal time, transmission one is had " write export delay time register " order bag of increasing one unit delay amount with the first memory device 100-1 allowing Fig. 1 by controller 10.After enough clock period of first memory device, such as referring to the tWODR (write and export the delay time register stand-by period) described by Figure 10 and total tIOL stand-by period, if phase differential is still unacceptable, another " write and export delay time register " can order bag to be sent to second memory device by controller 10, such as, send to the second memory device 100-2 of Fig. 1.This sequence of operation can continue always, until storer 10 obtains acceptable phase differential.After last storage arrangement of instruction adjusts its output delay, increasing one unit delay values of Memory Controller 10 in order bag points to first memory device, and proceed this operation for remaining storage arrangement, until this phase differential reaches acceptable scope.

Process above illustrates in the flowchart of fig. 9.The method starts from block 9-1, power supply opening.At this point, the lag line that initialization is all and unit address.At block 9-2, Memory Controller 10 uses phase detector 11 to monitor phase error between CKI/CKI# and CKO/CKO#.If there is phase error, after 9-3, select "Yes" path, then send " PE " signal S11 at block 9-4 phase detector 11.After this, while monitoring phase error, " write and export delay time register " order that command generator 12 will have numerical value " ODR+1 " is sent to one at a time from first to last each storage arrangement.At block 9-6, if still there is phase error, select "Yes" path, then the method turns back to block 9-4.If no longer there is phase error, select "No" path after block 9-6, then complete phase correction at 9-7.Similarly, if phase error do not detected at block 9-3, then the method terminates, and completes phase correction at block 9-7.

Table 3 is for writing the example command package definition exporting delay time register order.First byte is " unit address (=DA) " part, and the second byte comprises command code (=CMD=FBh), and the 3rd byte comprises register value (ODR<0:1>).In certain embodiments, provide broadcast address, such as FFh.If DA is set to broadcast address, mean that this order is broadcasting command, therefore expect that each storage arrangement performs this order.Otherwise the particular memory device of only mating this DA performs this order.In certain embodiments, in order to make controller 10 have more dirigibility, also achieve " read output delay time register ".Such as, need then again to configure setting suitably between the devices subsequently and if this can use by controller the numerical value read from all storage arrangements.

Table 3 is for the example command package definition of controller programmable delay circuit register

Order	First byte	Second byte	3rd byte
				Write and export delay time register (ODR)	DA	FBh	ODR<0:1>

^*attention:

Table 4 is the example position definition exporting delay time register (=ODR).Show pure exemplary definition, if therefore system configuration needs unit delay to adjust thinner granularity, in order to adapt to the better manageability of programmable delay line, this table can easily be expanded.

The example position definition of table 4 duty cycle register and output delay time register

Figure 10 operates the example of the sequential chart of " write and export delay time register " order packet sequence based on SDR (single data rate).In the timing diagram, in the T1 moment, the negative edge of the rising edge of CKI or CKI# latches the high state of CSI and the DA (=unit address=00h) information simultaneously latched on Dn port.At next rising edge time T2, storage arrangement latches CMD (=order=FBh) information, rises edge on a third, ODR (=export delay time register numerical value=01h) information.CSO exports and Qn output port repeats CSI respectively with two clock latency tIOL (=input to export stand-by period) and inputs and Dn input signal.There is the definition of another stand-by period, it is tWODR (=write export delay time register stand-by period), its for write export delay time register wrap in memory chip processing time and for exporting the processing time postponing adjustment in controller programmable delay line 2 (=PDL2 105 A-D).In certain embodiments, as shown in Figure 10, tWODR numerical value is set to 4 clock period.After the tWODR time (such as, at T8), other order bags any can be sent to storage arrangement by Memory Controller 10.

More generally, the embodiment of the application provides the Method and circuits performing and export and postpone adjustment embodiment, and in this embodiment, create the delay form of at least one input signal, this at least one input signal at least comprises clock signal.The other input signal transmitted between device can be there is, do not carried out output and postpone adjustment.For some signals, the delay form producing input signal comprises the delay form producing input signal conditionally export for exporting.That is, some signals can transmit conditionally between neighboring devices.Be described below in detail concrete example, wherein the input data signal of storage arrangement is sent to next storage arrangement at some time.

Above-described embodiment hypothesis employs the programmable delay line comprising same units delay block.In certain embodiments, programmable delay line is divided into 2 or more parts, such as " coarse adjustment " and " fine tuning " lag lines, with allow for duty cycle correction delay adjustment and/or export the further programmability postponing to adjust.

In described detailed example, near the input of each signal, there is the first trigger, near it exports, there is the second trigger.This generates the stand-by period of two clock period.It will be appreciated, of course, that and can cause other clock latencies by comprising different functionalities between input and output.

In the described embodiment, after output lag line is positioned at last trigger, last trigger is positioned near the output of each signal.In certain embodiments, before output lag line is positioned at last trigger.

In certain embodiments, suppose that the device connected in a series arrangement is roughly the same.In certain embodiments, these are roughly the same storage arrangements.In other embodiments, dissimilar storage arrangement can be used, as long as they have compatible serial line interface.

Detailed embodiment has been supposed to adopt different clock signals.More generally, single-ended or differential clock signal can be used.Similarly, other input/output signals can be single-ended signal or differential signal arbitrarily.

In certain embodiments, provide single MCP (multi-chip package), it comprises multiple storage arrangement and controller, can as described in operate.

Method and apparatus hypothesis described herein is characterized as the series architecture being connected with controller and storage stack device in ring.In such embodiments, storage arrangement is from device, and Memory Controller is main device.More generally, method and apparatus described herein can be applied to the semiconductor IC system of any kind of the semiconductor circuit arrangement with any kind, this semiconductor circuit arrangement be configured in cascaded structure from device, this cascaded structure has common interface between neighboring devices, and has device to be configured to be used as to control by this duty cycle correction from device execution and/or the main device of phase correction in this cascaded structure.The example of integrated circuit type comprises central processor unit, Graphics Processing Unit, display controller IC, disk drive IC, such as NAND flash-EEPROM, NOR flash-EEPROM, the storage arrangement of AND flash-EEPROM, DiNOR flash-EEPROM, serial flash-EEPROM, DRAM, SRAM, ROM, EPROM, FRAM, MRAM and PCRAM.

Embodiment hypothesis more described herein is that single data rate runs.Those of ordinary skill in the art are appreciated that more generally by reading this open text, and above-described embodiment can be applied to the system with other data rates by suitable amendment, such as dual rate is run.

In the above teachings, numerous modifications and variations of the present invention are possible.Therefore, should be appreciated that within the scope of the appended claims, the present invention can realize in the mode outside concrete scheme described herein.

Claims

1. be used in multiple series connection from device from the method device, the method comprises:

The order of specifying coming autonomous devices or last series connection and adjusting from the clock duty cycle of the input clock signal of device is received from main device;

Input clock signal is received from device from described main device or last series connection;

Clock signal through duty cycle correction is produced from described input clock signal according to described order;

Export the described clock signal through duty cycle correction to described main device or series connection subsequently from device.

2. method according to claim 1, wherein said is storage arrangement from device, and described main device is Memory Controller.

3. method according to claim 1, comprises further:

The order of specifying said slave device how to adjust the delay by being applied at least one signal exported by said slave device is received from main device;

Receive at least one input signal, at least one input signal described at least comprises described input clock signal;

For each of at least one input signal:

The delay form of described input signal is produced according to described order;

Export the described delay form of described input signal, the described delay form of described input signal comprises the delay form of the described clock signal through duty cycle correction.

4. method according to claim 1, wherein receive to specify from main device and the order that clock duty cycle adjusts is comprised: receive the order comprising command identifier, it is duty cycle correction order that this command identifier identifies described order, and described order also comprises the data how instruction adjusts dutycycle.

5. method according to claim 4, wherein receives order and comprises further and receive instruction and be used as will perform the unit address of described order from which device of device.

6. method according to claim 5, comprises further:

If described order has the unit address of the unit address of coupling said slave device, then perform according to described order the step producing the described clock signal through duty cycle correction;

If it is the unit address of broadcaster address that described order has, then perform according to described order the step producing the described clock signal through duty cycle correction.

7. method according to claim 4, wherein:

The clock signal produced through duty cycle correction comprises:

A) clock signal of half frequency is produced from described input clock signal;

B) clock signal of described half frequency is postponed with selected in multiple delay with half frequency clock signal be delayed;

C) half frequency clock signal of described half frequency clock signal and described delay is combined to produce the described clock signal through duty cycle correction.

8. method according to claim 7, wherein indicates the described data how adjusting described duty cycle correction to comprise the instruction of selected in described multiple delay.

9. be used in and comprise main device and multiple series connection from the method the accumulator system of device, said slave device comprises at least the first from device and last from device, and described method comprises:

In described main device:

A) export and be used as described first from the first clock signal of the input clock signal of device;

B) receive second clock signal, it is the described last clock signal from device;

C) produce the duty cycle correction order relevant to the dutycycle of described second clock signal and export described duty cycle correction order;

In described multiple series connection from first of device from device:

A) described first clock signal is received from described main device, as described first from the described input clock signal of device;

B) clock signal is produced from described input clock signal;

Described multiple series connection from device each other from device:

A) the last clock signal from device is received, as this input clock signal from device;

B) clock signal is produced from described input clock signal;

At least one each of multiple series connection from device:

A) described duty cycle correction order is received;

B) clock signal through duty cycle correction is produced according to described duty cycle correction order from described input clock signal;

C) the described clock signal through duty cycle correction is exported, as the clock signal of said slave device.

10. method according to claim 9, wherein each is storage arrangement from device, and described main device is Memory Controller.

11. methods according to claim 9 or 10, comprise further:

In described main device:

A) export at least one output signal, at least one output signal described comprises described first clock signal, as described first from the input clock signal of device;

C) the phase deviation amount between described first clock signal and described second clock signal is determined;

D) produce the output relevant to the phase deviation between described first clock signal and described second clock signal postpone to adjust order and export described export to postpone to adjust order.

12. methods according to claim 9 or 10, wherein produce the duty cycle correction order relevant to the dutycycle of described second clock signal and export described duty cycle correction order and comprise and produce for by arbitrarily specify the duty cycle correction order that perform of described multiple series connection from device.

13. methods according to claim 12, wherein produce the duty cycle correction order relevant to the dutycycle of described second clock signal and export described duty cycle correction order and comprise the duty cycle correction order produced for being performed from device by all described multiple series connection.

14. methods according to claim 9, wherein receive described duty cycle correction order and comprise: receive the order comprising command identifier, it is duty cycle correction order that this command identifier identifies described order, and comprises the data how instruction adjusts dutycycle.

15. methods according to claim 14, wherein:

The clock signal produced through duty cycle correction comprises:

16. methods according to claim 15, the data how wherein said instruction adjusts described duty cycle correction comprise the instruction of selected in described multiple delay.

17. 1 kinds be used in comprise multiple series connection from the structure of device from device, said slave device comprises:

Command input circuit, for receiving the order indicating and adjust dutycycle from main device;

Clock input circuit, for receiving input clock signal;

Duty-cycle correction circuit, for producing clock signal through duty cycle correction according to described order from described input clock signal;

Clock output circuit, for exporting the described clock signal through duty cycle correction to described main device or series connection subsequently from device.

18. is according to claim 17 from device, wherein said from device be storage arrangement.

19. according to claim 17 or 18 from device, wherein:

Described command input circuit is also specified exporting the order postponing adjustment for receiving from described main device;

Export delay regulating circuit to be used for according to described order from the described clock signal be delayed through the signal of duty cycle correction;

The wherein said clock output circuit for exporting the described clock signal through duty cycle correction exports the clock signal of described delay.

20. according to claim 17 or 18 from device, also comprise:

Command process circuit, for the treatment of described order,

Wherein said order comprises:

Identify the command identifier that described order is duty cycle correction order; With

How instruction adjusts the data of dutycycle.

21. is according to claim 20 from device, also comprises:

Unit address register;

Wherein said order comprises the unit address which indicates perform described order from device further, if described unit address mates the content of described unit address register, said slave device is configured to perform described order.

22. according to claim 17 or 18 from device, wherein said duty-cycle correction circuit comprises:

A) clock divider circuit, for producing the clock signal of half frequency from described input clock signal;

B) delay circuit, for being postponed the clock signal of described half frequency with half frequency clock signal be delayed by selected in multiple delay;

C) combiner, for combining half frequency clock signal of described half frequency clock signal and described delay to produce the described clock signal through duty cycle correction.

23. is according to claim 22 from device, and wherein said delay circuit comprises M unit delay part, M>=2, and described duty-cycle correction circuit also comprises:

N to M demoder, for by the signal decoding received on N number of incoming line be postpone described half frequency clock signal with half frequency clock signal be delayed in the selection of number of effective described unit delay part, N>=1.

24. 1 kinds of accumulator systems, comprising:

As the multiple tandem arrangements from device according to claim 17, described multiple tandem arrangement comprises at least the first from device and last from device;

Be connected to described first from device and the described last main device from device;

Described main device is configured to export and is used as described first from the first clock signal of the input clock signal of device;

For receiving the clock input circuit of the second clock signal being the described last clock signal from device;

For determining the duty detecting device of the dutycycle of described second clock signal;

Command generator, for generation of specifying the duty cycle correction order adjusted the clock duty cycle relevant to the dutycycle of described second clock signal;

Wherein, be used as from first of described multiple tandem arrangement of device from device:

B) clock signal is produced from described input clock signal;

Wherein, be used as from described multiple tandem arrangement of device each other from device:

B) clock signal is produced from described input clock signal;

At least one of wherein said multiple tandem arrangement:

A) described duty cycle correction order is received;

B) clock signal through duty cycle correction is produced according to duty cycle correction order;

25. accumulator systems according to claim 24, wherein, each is storage arrangement from device, and described main device is Memory Controller.

26. accumulator systems according to claim 24 or 25, also comprise:

Phase detector, for determining the phase deviation amount between described first clock signal and described second clock signal;

Wherein, described command generator also produces the output relevant to phase deviation amount and postpones to adjust and order;

Wherein, at described multiple tandem arrangement first from device:

B) clock signal is produced from described input clock signal;

Wherein, described multiple tandem arrangement each other from device:

A) the last clock signal from device is received, as the input clock signal of said slave device;

B) clock signal is produced from described input clock signal;

At least one device of wherein said multiple tandem arrangement:

A) receive described output and postpone adjustment order;

B) by exporting according to described the clock signal that the input clock signal postponing adjustment order delay at least one device described produces at least one device described.

27. accumulator systems according to claim 24 or 25, wherein said command generator is configured to produce the duty cycle correction order relevant to the dutycycle of described second clock signal and by producing for exporting described duty cycle correction order by as the duty cycle correction order performed from the appointment one of described multiple tandem arrangement of device.

28. accumulator systems according to claim 24 or 25, wherein said command generator is configured to produce the duty cycle correction order relevant to the dutycycle of described second clock signal and by producing for exporting described duty cycle correction order by as the duty cycle correction order performed from all described multiple tandem arrangement of device.

29. accumulator systems according to claim 24 or 25, wherein receive described duty cycle correction order to comprise: receive the order comprising command identifier, it is duty cycle correction order that this command identifier identifies described order, and comprises the data how instruction adjusts dutycycle.

30. 1 kinds are used in and comprise main device and be used as from the method the accumulator system of multiple tandem arrangements of device, and said slave device comprises at least the first from device and last from device, and described method comprises:

In described main device:

A) export at least one output signal, at least one output signal described comprises the first clock signal, as described first from the input clock signal of device;

D) produce the output relevant to the phase deviation amount between described first clock signal and described second clock signal postpone to adjust order and export described export to postpone to adjust order.

31. methods according to claim 30, wherein each is storage arrangement from device, and described main device is Memory Controller.

32. methods according to claim 30 or 31, comprise further:

Be used as from first of described multiple tandem arrangement of device from device:

A) at least one output signal described is received from described main device, as described first from least one input signal corresponding of device;

B) for each input signal, output signal is produced based on described input signal;

Be used as from described multiple tandem arrangement of device each other from device:

A) receive the last output signal from device, it corresponds at least one input signal of said slave device;

Said slave device at least one in,

A) receive described output and postpone adjustment order; And

B) by producing described output signal according to the described delay form postponing the described input signal of adjustment order generation that exports.

33. methods according to claim 32, comprise further:

At least one output signal described of wherein said main device comprises multiple output signal.

34. methods according to claim 30 or 31, the adjustment order that is wherein delayed comprises and producing for adjusting order by described multiple series connection from the specific delay performed device.

35. methods according to claim 30 or 31, the adjustment order that is wherein delayed comprises and producing for adjusting order by the delay performed from device of all described multiple series connection.

36. methods according to claim 32, wherein comprise according to the described delay form postponing the described input signal of adjustment order generation that exports the delay form producing the described input signal postponed with selected in multiple delay.

37. methods according to claim 36, the adjustment order that is wherein delayed comprises: produce the order comprising command identifier, and this command identifier identifies described order and postpones adjustment order for exporting, and comprises the data how instruction adjusts delay.

38. according to method according to claim 37, and the data how wherein said instruction adjusts delay comprise the instruction of selected in described multiple delay.

39. methods according to claim 30 or 31, comprise further:

Described main device exports and postpones adjustment order, and described output postpones adjustment order by increasing by 1 unit delay part at one from device adjusts delay, until described phase deviation amount is acceptable at every turn.

40. methods according to claim 32, at least one input signal wherein said comprises:

Clock signal;

Command strobes signal;

Data strobe signal;

Comprise the data-signal of order and data.

41. 1 kinds of accumulator systems, comprising:

Multiple series connection is from device, and described multiple series connection comprises at least the first from device and last from device from device;

Clock input circuit, for receiving second clock signal, it is the described last clock signal from device;

Command generator, postpones to adjust for generation of the output relevant to described phase deviation amount and orders;

Wherein, in described multiple series connection from first of device from device:

B) clock signal is produced from described input clock signal;

Wherein, described multiple series connection from device each other from device:

A) the last clock signal from device is received, as the input clock signal from device;

B) clock signal is produced from described input clock signal;

Wherein said multiple series connection is from least one device of device:

A) receive described output and postpone adjustment order;

B) export according to described the clock signal postponing to adjust and order the input clock signal by postponing at least one device described to produce at least one device described.

42. accumulator systems according to claim 41, wherein, each is storage arrangement from device, and described main device is Memory Controller.

43. accumulator systems according to claim 41 or 42, wherein said command generator is configured to produce for postponing adjustment order by described multiple series connection from the specific output performed device.

44. accumulator systems according to claim 41 or 42, wherein said command generator is configured to produce for postponing adjustment order by all described multiple series connection from the output that device performs.

45. accumulator systems according to claim 41 or 42, wherein produce output delay adjustment order to comprise: produce the order comprising command identifier, it is that output postpones adjustment order that this command identifier identifies described order, and comprises the data how instruction adjusts output delay.