CN102157426B - Wafer support and wafer processing process - Google Patents
Wafer support and wafer processing process Download PDFInfo
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- CN102157426B CN102157426B CN201110031967.2A CN201110031967A CN102157426B CN 102157426 B CN102157426 B CN 102157426B CN 201110031967 A CN201110031967 A CN 201110031967A CN 102157426 B CN102157426 B CN 102157426B
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- wafer
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- thin wafer
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- wafer support
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Abstract
The invention discloses a kind of wafer support, this device is circle ring column structure, thus can not block the semiconductor device area in ultra thin wafer front, therefore can carry out performance test in time before packaging, problem in timely feedback and evaluation process, reduces process risk; Simultaneously, the invention also discloses a kind of wafer processing process, this treatment process make use of above-mentioned wafer support and supports ultra thin wafer in chip back surface treatment process process, and performance test is carried out after chip back surface treatment process, thus the problem in time in feedback and evaluation process, reduce process risk.
Description
Technical field
The present invention relates to technical field of integrated circuits, particularly relate to a kind of wafer support and wafer processing process.
Background technology
Along with the progress of integrated circuit technique, semiconductor integrated circuit while integrated level, speed and reliability improve constantly to compact future development.And along with the introducing of silicon through hole (TSV, Through Silicon Via) 3D encapsulation technology, more and more higher to the requirement of chip thickness, ultra thin wafer arises at the historic moment.So-called ultra thin wafer refers to that thickness is equal to or less than the wafer of 100um.Meanwhile, because ultra thin wafer has low resistance, low dissipation power and good heat-conductive characteristic, therefore, in power electronic device, the focus of research is also become.
Ultra thin wafer is realized by chip back surface reduction process usually, so-called chip back surface reduction process refers to after the manufacture of wafer surface circuit completes, carry out thinning to chip back surface silicon materials sheet or grinding is thinning (backside grinding), make it reach required thickness.
But, because the intensity of ultra thin wafer is low, therefore its very easily bending and distortion, and easily break in process treatment process.
In order to solve the problem that ultra thin wafer is easily out of shape and breaks in process treatment process, the measure taked at present is increase temporary support carrier in the front of wafer, particularly, temporary support carrier is adhered to the front of wafer by viscous layer, so that chip back surface is thinning, and follow-up ultra thin wafer process and the back side process.Described temporary support carrier can be the virtual silicon wafer of rigidity, chip glass, polymer, Polymers compound substrate or thick diaphragm.The temporary support carrier of described rigidity contributes to during process and manufacturing process, reducing chip warpage and preventing wafer breakage.
But existing temporary support carrier is the front covering whole ultra thin wafer, thus the wafer scale functional test in ultra thin wafer front cannot be carried out in time, and after device package can only be waited, carry out performance test again; Thus can not obtain the result of performance test in time, thus can not feed back in time and the problem in evaluation process, bring great risk, and no matter quality all needs encapsulation due to all devices, thus too increase production cost.
Therefore, be necessary to improve existing ultra thin wafer bracing or strutting arrangement.
Summary of the invention
The object of the present invention is to provide a kind of wafer support and wafer processing process, to solve the problem that existing ultra thin wafer can not carry out performance test in time.
For solving the problem, the present invention proposes a kind of wafer support, is fixed on the front of ultra thin wafer, for supporting ultra thin wafer in chip back surface treatment process, wherein, the front preparation of described ultra thin wafer has semiconductor device, and described wafer support is circle ring column structure.
Optionally, the external diameter of described circle ring column structure is equal to or greater than the diameter of ultra thin wafer, and its internal diameter is greater than the diameter of semiconductor device area, ultra thin wafer front.
Optionally, the material of described wafer support is rigidity exotic material.
Optionally, the material of described wafer support is any one in glass, quartz, resin, metal.
Optionally, described chip back surface treatment process comprises one or more in photoetching, ion implantation, annealing, wet etching or dry etching, sputtering, evaporation.
Optionally, the thickness of described ultra thin wafer is less than or equal to 100um.
Meanwhile, for solving the problem, the present invention also proposes a kind of wafer processing process, and the preparation of this front wafer surface has semiconductor device, and this treatment process comprises the steps:
Thinning diaphragm (tape) is pasted front wafer surface;
Thinning and etching is carried out, until wafer thickness reaches the requirement of ultra thin wafer to chip back surface;
Remove described thinning diaphragm;
Above-mentioned wafer support is fixed on the front of ultra thin wafer;
Back side treatment process is carried out to described ultra thin wafer;
Performance test is carried out to the semiconductor device in described ultra thin wafer front;
The blue film of cutting (dicing tape) is pasted at the back side of described ultra thin wafer;
Remove described wafer support; And
Described ultra thin wafer is cut.
Optionally, the external diameter of described circle ring column structure is equal to or greater than the diameter of ultra thin wafer, and its internal diameter is greater than the diameter of semiconductor device area, ultra thin wafer front.
Optionally, the material of described wafer support is rigidity exotic material.
Optionally, the material of described wafer support is any one in glass, quartz, resin, metal.
Optionally, described chip back surface treatment process comprises one or more in photoetching, ion implantation, annealing, wet etching or dry etching, sputtering, evaporation.
Optionally, the thickness of described ultra thin wafer is less than or equal to 100um.
Compared with prior art, wafer support provided by the invention is circle ring column structure, thus can not block the semiconductor device area in ultra thin wafer front, therefore can carry out performance test in time before packaging, problem in timely feedback and evaluation process, reduces process risk.
Compared with prior art, wafer processing process provided by the invention make use of above-mentioned wafer support and supports ultra thin wafer in chip back surface processing procedure, and performance test is carried out after chip back surface treatment process, thus the problem in time in feedback and evaluation process, reduce process risk.
Accompanying drawing explanation
The structural representation of the wafer support that Fig. 1 provides for the embodiment of the present invention;
The flow chart of steps of the wafer processing process that Fig. 2 provides for the embodiment of the present invention.
Embodiment
The wafer support proposed the present invention below in conjunction with the drawings and specific embodiments and wafer processing process are described in further detail.According to the following describes and claims, advantages and features of the invention will be clearer.It should be noted that, accompanying drawing all adopts the form that simplifies very much and all uses non-ratio accurately, only in order to object that is convenient, the aid illustration embodiment of the present invention lucidly.
Core concept of the present invention is, provides a kind of wafer support, and this device is circle ring column structure, thus the semiconductor device area in ultra thin wafer front can not be blocked, therefore can carry out performance test in time before packaging, the problem in time in feedback and evaluation process, reduces process risk; Simultaneously, a kind of wafer processing process is also provided, this treatment process make use of above-mentioned wafer support and supports ultra thin wafer in chip back surface treatment process process, and performance test is carried out after chip back surface treatment process, thus the problem in time in feedback and evaluation process, reduce process risk.
Please refer to Fig. 1, the structural representation of the wafer support that Fig. 1 provides for the embodiment of the present invention, as shown in Figure 1, the wafer support 101 that the embodiment of the present invention provides is fixed on the front of ultra thin wafer 100, for supporting ultra thin wafer 100 in chip back surface treatment process, wherein, the front preparation of described ultra thin wafer 100 has semiconductor device, and described wafer support 101 is circle ring column structure.
Further, the external diameter of described circle ring column structure is equal to or greater than the diameter of ultra thin wafer, and its internal diameter is greater than the diameter of semiconductor device area, ultra thin wafer front.
Wafer support 101 device provided due to the embodiment of the present invention is circle ring column structure, thus the semiconductor device area in ultra thin wafer 100 front can not be blocked, therefore can carry out performance test in time before packaging, the problem in time in feedback and evaluation process, reduces process risk.
Further, the material of described wafer support 101 is rigidity exotic material; Thus described ultra thin wafer 100 can be supported preferably, and can not be damaged because of high technological temperature in chip back surface treatment process process.
Further, the material of described wafer support 101 is any one in glass, quartz, resin, metal.
Further, described chip back surface treatment process comprises one or more in photoetching, ion implantation, annealing, wet etching or dry etching, sputtering, evaporation.
Further, the thickness of described ultra thin wafer is less than or equal to 100um.
Please continue to refer to the flow chart of steps of the wafer processing process that Fig. 2, Fig. 2 provide for the embodiment of the present invention, as shown in Figure 2, the wafer processing process that the embodiment of the present invention provides comprises the steps:
S101, thinning diaphragm is pasted front wafer surface; Wherein, this front wafer surface has been prepared semiconductor device; Described thinning diaphragm is a kind of front wafer surface device diaphragm, and the semiconductor device of protection front wafer surface does not sustain damage in subsequent processes;
S102, to chip back surface carry out thinning and etching, until wafer thickness reaches the requirement of ultra thin wafer; In thinning and etching process, the semiconductor device of described thinning diaphragm to described front wafer surface shields;
S103, remove described thinning diaphragm;
S104, above-mentioned wafer support is fixed on the front of ultra thin wafer; Particularly, described wafer support is affixed to the front of ultra thin wafer;
S105, back side treatment process is carried out to described ultra thin wafer;
S106, performance test is carried out to the semiconductor device in described ultra thin wafer front;
S107, the back side of described ultra thin wafer paste cutting blue film; Wherein, the blue film of described cutting is a kind of diaphragm, and protection ultra thin wafer is not damaged in cutting process;
S108, remove described wafer support; And
S109, described ultra thin wafer to be cut; Particularly, described ultra thin wafer is cut into crystal grain (die) for follow-up encapsulation.
Further, the external diameter of described circle ring column structure is equal to or greater than the diameter of ultra thin wafer, its internal diameter is greater than the diameter of semiconductor device area, ultra thin wafer front, thus while providing support to ultra thin wafer, exposes the semiconductor device area in ultra thin wafer front completely.
Further, the material of described wafer support is rigidity exotic material; Thus described ultra thin wafer 100 can be supported preferably, and can not be damaged because of high technological temperature in chip back surface treatment process process.
Further, the material of described wafer support is any one in glass, quartz, resin, metal.
Further, described chip back surface treatment process comprises one or more in photoetching, ion implantation, annealing, wet etching or dry etching, sputtering, evaporation.
Further, the thickness of described ultra thin wafer is less than or equal to 100um.
In sum, the invention provides a kind of wafer support, this device is circle ring column structure, thus the semiconductor device area in ultra thin wafer front can not be blocked, therefore can carry out performance test in time before packaging, the problem in time in feedback and evaluation process, reduces process risk; Simultaneously, additionally provide a kind of wafer processing process, this treatment process make use of above-mentioned wafer support and supports ultra thin wafer in chip back surface treatment process process, and performance test is carried out after chip back surface treatment process, thus the problem in time in feedback and evaluation process, reduce process risk.
Obviously, those skilled in the art can carry out various change and modification to invention and not depart from the spirit and scope of the present invention.Like this, if these amendments of the present invention and modification belong within the scope of the claims in the present invention and equivalent technologies thereof, then the present invention is also intended to comprise these change and modification.
Claims (12)
1. a wafer support, be fixed on the front of ultra thin wafer, for supporting ultra thin wafer in chip back surface treatment process, wherein, the front preparation of described ultra thin wafer has semiconductor device, it is characterized in that, described wafer support is circle ring column structure, for carrying out the performance test of ultra thin wafer before packaging.
2. wafer support as claimed in claim 1, it is characterized in that, the external diameter of described circle ring column structure is equal to or greater than the diameter of ultra thin wafer, and its internal diameter is greater than the diameter of semiconductor device area, ultra thin wafer front.
3. wafer support as claimed in claim 1 or 2, it is characterized in that, the material of described wafer support is rigidity exotic material.
4. wafer support as claimed in claim 3, is characterized in that, the material of described wafer support is any one in glass, quartz, resin, metal.
5. wafer support as claimed in claim 1, is characterized in that, described chip back surface treatment process comprises one or more in photoetching, ion implantation, annealing, wet etching or dry etching, sputtering, evaporation.
6. wafer support as claimed in claim 1, it is characterized in that, the thickness of described ultra thin wafer is less than or equal to 100um.
7. a wafer processing process, the preparation of this front wafer surface has semiconductor device, it is characterized in that, comprises the steps:
Thinning diaphragm is pasted front wafer surface;
Thinning and etching is carried out, until wafer thickness reaches the requirement of ultra thin wafer to chip back surface;
Remove described thinning diaphragm;
Wafer support according to claim 1 is fixed on the front of ultra thin wafer;
Back side treatment process is carried out to described ultra thin wafer;
Performance test is carried out to the semiconductor device in described ultra thin wafer front;
The blue film of cutting is pasted at the back side of described ultra thin wafer;
Remove described wafer support; And
Described ultra thin wafer is cut.
8. wafer processing process as claimed in claim 7, it is characterized in that, the external diameter of described circle ring column structure is equal to or greater than the diameter of ultra thin wafer, and its internal diameter is greater than the diameter of semiconductor device area, ultra thin wafer front.
9. wafer processing process as claimed in claim 7 or 8, it is characterized in that, the material of described wafer support is rigidity exotic material.
10. wafer processing process as claimed in claim 9, is characterized in that, the material of described wafer support is any one in glass, quartz, resin, metal.
11. wafer processing process as claimed in claim 7, is characterized in that, described chip back surface treatment process comprises one or more in photoetching, ion implantation, annealing, wet etching or dry etching, sputtering, evaporation.
12. wafer processing process as claimed in claim 7, it is characterized in that, the thickness of described ultra thin wafer is less than or equal to 100um.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
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| CN201110031967.2A CN102157426B (en) | 2011-01-28 | 2011-01-28 | Wafer support and wafer processing process |
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| Application Number | Priority Date | Filing Date | Title |
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| CN201110031967.2A CN102157426B (en) | 2011-01-28 | 2011-01-28 | Wafer support and wafer processing process |
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| CN102157426A CN102157426A (en) | 2011-08-17 |
| CN102157426B true CN102157426B (en) | 2015-10-07 |
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Families Citing this family (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104752189A (en) * | 2013-12-30 | 2015-07-01 | 中芯国际集成电路制造(上海)有限公司 | WLCSP wafer back thinning process |
| CN105390408A (en) * | 2014-09-03 | 2016-03-09 | 中芯国际集成电路制造(上海)有限公司 | Wafer structure and thinning method therefor |
| US10326044B2 (en) * | 2017-08-18 | 2019-06-18 | Micron Technology, Inc. | Method and apparatus for processing semiconductor device structures |
| CN111355118B (en) * | 2018-12-20 | 2021-07-20 | 中科芯电半导体科技（北京）有限公司 | VCSEL structure epitaxial material structure for photoluminescence test and preparation method |
| CN110459501A (en) * | 2019-05-30 | 2019-11-15 | 中国电子科技集团公司第五十五研究所 | A kind of reinforcing holding structure and preparation method thereof for disk to be thinned |
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| CN1897225A (en) * | 2005-07-12 | 2007-01-17 | 探微科技股份有限公司 | Chip thinning method |
| CN101256951A (en) * | 2007-02-28 | 2008-09-03 | 万国半导体股份有限公司 | Method and apparatus for ultra thin wafer backside processing |
| CN101350332A (en) * | 2007-07-20 | 2009-01-21 | 万国半导体股份有限公司 | Ultra thin wafers having an edge support ring and manufacture method thereof |
| CN101415547A (en) * | 2004-08-20 | 2009-04-22 | 塞米图尔公司 | System for thinning a semiconductor workpiece |
| CN101593676A (en) * | 2009-04-15 | 2009-12-02 | 秦拓微电子技术(上海)有限公司 | Gong-shaped ultra-thin wafers preparation method and technology |
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| KR20050120925A (en) * | 2004-06-21 | 2005-12-26 | 삼성테크윈 주식회사 | Wafer support device and method for electrodeless ni-bumping therewith |
| GB2459301B (en) * | 2008-04-18 | 2011-09-14 | Xsil Technology Ltd | A method of dicing wafers to give high die strength |
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| CN101415547A (en) * | 2004-08-20 | 2009-04-22 | 塞米图尔公司 | System for thinning a semiconductor workpiece |
| CN1897225A (en) * | 2005-07-12 | 2007-01-17 | 探微科技股份有限公司 | Chip thinning method |
| CN101256951A (en) * | 2007-02-28 | 2008-09-03 | 万国半导体股份有限公司 | Method and apparatus for ultra thin wafer backside processing |
| CN101350332A (en) * | 2007-07-20 | 2009-01-21 | 万国半导体股份有限公司 | Ultra thin wafers having an edge support ring and manufacture method thereof |
| CN101593676A (en) * | 2009-04-15 | 2009-12-02 | 秦拓微电子技术(上海)有限公司 | Gong-shaped ultra-thin wafers preparation method and technology |
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Owner name: SHANGHAI HUAHONG GRACE SEMICONDUCTOR MANUFACTURING Free format text: FORMER OWNER: HONGLI SEMICONDUCTOR MANUFACTURE CO LTD, SHANGHAI Effective date: 20140505 |
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Effective date of registration: 20140505 Address after: 201203 Shanghai Zhangjiang hi tech park Zuchongzhi Road No. 1399 Applicant after: Shanghai Huahong Grace Semiconductor Manufacturing Corporation Address before: 201203 Shanghai Guo Shou Jing Road, Pudong New Area Zhangjiang hi tech Park No. 818 Applicant before: Hongli Semiconductor Manufacture Co., Ltd., Shanghai |
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